[(set (match_operand:SI 0 "general_operand" "=d")
(match_operator 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))]
""
- "test%C1 %0"
+ "test%C1 %0"
[(set_attr "type" "compare")])
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=d")
(match_operator 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))]
""
- "test%C1 %0"
+ "test%C1 %0"
[(set_attr "type" "compare")])
\f
;; These control RTL generation for conditional jump insns
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32)
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
return \"subo %n2,%1,%0\";
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"addo %2,%1,%0\";
}"
[(set_attr "type" "mult")])
+(define_insn "umulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+ ""
+ "*
+{
+ if (i960_bypass (insn, operands[1], operands[2], 0))
+ return \"emul %2,%1,%0\";
+ return \"emul %1,%2,%0\";
+}"
+ [(set_attr "type" "mult")])
+
;; This goes after the move/add/sub/mul instructions
;; because those instructions are better when they apply.
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
- (not:SI (and:SI (match_operand:SI 1 "arith_operand" "%dI")
- (match_operand:SI 2 "arith_operand" "dI"))))]
+ (ior:SI (match_operand:SI 1 "arith_operand" "dI")
+ (match_operand:SI 2 "power2_operand" "n")))]
""
"*
{
- if (i960_bypass (insn, operands[1], operands[2], 0))
- return \"nand %2,%1,%0\";
- return \"nand %1,%2,%0\";
+ operands[2] = gen_rtx (CONST_INT, VOIDmode,
+ bitpos (INTVAL (operands[2])));
+ return \"setbit %2,%1,%0\";
}")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
- (ior:SI (match_operand:SI 1 "arith_operand" "dI")
- (match_operand:SI 2 "power2_operand" "n")))]
+ (ior:SI (ashift:SI (const_int 1)
+ (match_operand:SI 1 "register_operand" "d"))
+ (match_operand:SI 2 "arith_operand" "dI")))]
+ ""
+ "setbit %1,%2,%0")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (and:SI (match_operand:SI 1 "arith_operand" "dI")
+ (match_operand:SI 2 "cmplpower2_operand" "n")))]
""
"*
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- bitpos (INTVAL (operands[2])));
- return \"setbit %2,%1,%0\";
+ bitpos (~INTVAL (operands[2])));
+ return \"clrbit %2,%1,%0\";
}")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
- (ior:SI (match_operand:SI 1 "power2_operand" "n")
+ (and:SI (ashift:SI (const_int 1)
+ (match_operand:SI 1 "register_operand" "d"))
(match_operand:SI 2 "arith_operand" "dI")))]
""
+ "clrbit %1,%2,%0")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (xor:SI (match_operand:SI 1 "arith_operand" "dI")
+ (match_operand:SI 2 "power2_operand" "n")))]
+ ""
"*
{
- operands[1] = gen_rtx (CONST_INT, VOIDmode,
- bitpos (INTVAL (operands[1])));
- return \"setbit %1,%2,%0\";
+ operands[2] = gen_rtx (CONST_INT, VOIDmode,
+ bitpos (INTVAL (operands[2])));
+ return \"notbit %2,%1,%0\";
}")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (xor:SI (ashift:SI (const_int 1)
+ (match_operand:SI 1 "register_operand" "d"))
+ (match_operand:SI 2 "arith_operand" "dI")))]
+ ""
+ "notbit %1,%2,%0")
+
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (match_operand:SI 1 "arith_operand" "%dI")
return \"nor %1,%2,%0\";
}")
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (not:SI (ior:SI (match_operand:SI 1 "arith_operand" "%dI")
- (match_operand:SI 2 "arith_operand" "dI"))))]
- ""
- "*
-{
- if (i960_bypass (insn, operands[1], operands[2], 0))
- return \"nor %2,%1,%0\";
- return \"nor %1,%2,%0\";
-}")
-
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(xor:SI (match_operand:SI 1 "arith_operand" "%dI")
(define_insn "muldf3"
[(set (match_operand:DF 0 "register_operand" "=d*f")
- (mult:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
+ (mult:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
(match_operand:DF 2 "fp_arith_operand" "rGH")))]
"TARGET_NUMERICS"
"mulrl %1,%2,%0"
(define_insn "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=d*f")
- (mult:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
+ (mult:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
(match_operand:SF 2 "fp_arith_operand" "rGH")))]
"TARGET_NUMERICS"
"mulr %1,%2,%0"
(define_insn "multf3"
[(set (match_operand:TF 0 "register_operand" "=f")
- (mult:TF (match_operand:TF 1 "nonmemory_operand" "fG")
+ (mult:TF (match_operand:TF 1 "nonmemory_operand" "%fG")
(match_operand:TF 2 "nonmemory_operand" "fG")))]
"TARGET_NUMERICS"
"mulr %1,%2,%0"