return r;
}
-int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
int r;
r = amdgpu_ras_block_late_init(adev, adev->gfx.ras_if);
int pipe, int queue);
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
-int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, void *ras_info);
+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
void *err_data,
#include "amdgpu.h"
#include "amdgpu_ras.h"
-int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
return amdgpu_ras_block_late_init(adev, adev->hdp.ras_if);
}
struct amdgpu_hdp_ras *ras;
};
-int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, void *ras_info);
+int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
void amdgpu_hdp_ras_fini(struct amdgpu_device *adev);
#endif /* __AMDGPU_HDP_H__ */
#include "amdgpu.h"
#include "amdgpu_ras.h"
-int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
return amdgpu_ras_block_late_init(adev, adev->mmhub.ras_if);
}
struct amdgpu_mmhub_ras *ras;
};
-int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev, void *ras_info);
+int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
#endif
#include "amdgpu.h"
#include "amdgpu_ras.h"
-int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
int r;
r = amdgpu_ras_block_late_init(adev, adev->nbio.ras_if);
struct amdgpu_nbio_ras *ras;
};
-int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info);
+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
#endif
int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
enum amdgpu_ras_block block, uint32_t sub_block_index);
- int (*ras_late_init)(struct amdgpu_device *adev, void *ras_info);
+ int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
void (*ras_fini)(struct amdgpu_device *adev);
ras_ih_cb ras_cb;
const struct amdgpu_ras_block_hw_ops *hw_ops;
}
int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
- void *ras_ih_info)
+ struct ras_common_if *ras_block)
{
int r, i;
int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
- void *ras_ih_info);
+ struct ras_common_if *ras_block);
void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
void *err_data,
return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, true);
}
-int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
int r;
struct amdgpu_umc_ras *ras;
};
-int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_info);
+int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
void *ras_error_status,
return psp_xgmi_terminate(&adev->psp);
}
-static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
if (!adev->gmc.xgmi.supported ||
adev->gmc.xgmi.num_physical_nodes == 0)
ras_error_status);
}
-static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
return amdgpu_mca_ras_late_init(adev, &adev->mca.mp0);
}
ras_error_status);
}
-static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
return amdgpu_mca_ras_late_init(adev, &adev->mca.mp1);
}
ras_error_status);
}
-static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev, void *ras_info)
+static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
return amdgpu_mca_ras_late_init(adev, &adev->mca.mpio);
}