arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port

Enable USB Super-Speed HOST port.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603142251.14563-5-kishon@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 8424cd0..077b876 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -5,6 +5,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include "k3-am642.dtsi"
@@ -85,6 +87,12 @@
                >;
        };
 
+       main_usb0_pins_default: main-usb0-pins-default {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+               >;
+       };
+
        main_i2c1_pins_default: main-i2c1-pins-default {
                pinctrl-single,pins = <
                        AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@@ -235,6 +243,33 @@
        disable-wp;
 };
 
+&serdes_ln_ctrl {
+       idle-states = <AM64_SERDES0_LANE0_USB>;
+};
+
+&serdes0 {
+       serdes0_usb_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_USB3>;
+               resets = <&serdes_wiz0 1>;
+       };
+};
+
+&usbss0 {
+       ti,vbus-divider;
+};
+
+&usb0 {
+       dr_mode = "host";
+       maximum-speed = "super-speed";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_usb0_pins_default>;
+       phys = <&serdes0_usb_link>;
+       phy-names = "cdns3,usb3-phy";
+};
+
 &cpsw3g {
        pinctrl-names = "default";
        pinctrl-0 = <&mdio1_pins_default