-======================================================================
-Changes since U-Boot 1.1.4:
-======================================================================
+commit 7c52c4b943ff52bbe8796a7e2d3e476ceaf3f512
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Oct 24 21:35:55 2006 +0200
+
+ Switch to automatically generated CHANGELOG file.
+ (use "make CHANGELOG" to update it from time to time)
+
+commit 7ade0c634a979c32fa91a74e8f5775f24651fbe6
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 24 18:06:48 2006 +0200
+
+ Fix bug in PPC440 NAND driver cpu/ppc4xx/ndfc.c
+ Patch by Stefan Roese, 24 Oct 2006
+
+commit 8ae3b713b2286e0c3213b7802062e4c1599010de
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 17:24:55 2006 +0200
+
+ Merge with /home/wd/git/u-boot/master
+
+commit 47a6989c10685d2ab3efcf95228ce50d2a496d3e
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 15:32:57 2006 +0200
+
+ Code cleanup
+
+commit 3a78e3e75b633ecb6413114ffd11e2f000c4f11e
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:51:36 2006 +0200
+
+ Move atstk1000 files into vendor specific directory.
+ Patch by Haavard Skinnemoen, 12 Sep 2006
+
+commit 6ccec4492e77428fd6eafd3dfe94fbdf08e91d37
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:42:37 2006 +0200
+
+ Add ATSTK1000 and ATSTK1002 board support
+ Patch by Haavard Skinnemoen, 06 Sep 2006
+
+ This patch adds support for the ATSTK1000 with the ATSTK1002 CPU
+ daughterboard.
+
+ ATSTK1000 is a full-featured development board for AT32AP CPUs. It
+ has two ethernet ports, a high quality QVGA LCD panel, a loudspeaker,
+ and connectors for USART, PS/2, VGA, USB, MMC/SD cards and
+ CompactFlash cards. For more information, please see this page:
+
+ http://www.atmel.com/dyn/products/tools.asp?family_id=682
+
+ The ATSTK1002 is a daughterboard for the ATSTK1000 supporting the
+ AT32AP7000 chip.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit f93ae788c3640fcde5db383471d45548ff4060d0
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:31:24 2006 +0200
+
+ Add common serial driver for Atmel AT32 and AT91 chips
+ Patch by Haavard Skinnemoen, 06 Sep 2006
+
+ This is a first attempt at creating a common serial driver for Atmel
+ chips. For now, it supports the AT32AP7000 AVR32 chip, but it should
+ be possible to support AT91RM9200 and other ARM-based chips with some
+ minor modifications.
+
+ There's nothing fundamentally AVR32-specific in this driver, but it
+ does use some features which are currently only defined for the
+ AT32AP CPU port:
+ * pm_get_clock_freq: Obtain the clock frequency of a given domain
+ * gd->console_uart: A "struct device" containing information about
+ register mappings, gpio resources and clocks associated with the
+ UART device.
+
+ For more information about these features, please see the "AT32AP
+ CPU" patch.
+
+commit 72a087e04705c26cad982879ebd06b5281bf825a
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:27:35 2006 +0200
+
+ Add AT32AP CPU and AT32AP7000 SoC support
+ Patch by Haavard Skinnemoen, 06 Sep 2006
+
+ This patch adds support for the AT32AP CPU family and the AT32AP7000
+ chip, which is the first chip implementing the AVR32 architecture.
+
+ The AT32AP CPU core is a high-performance implementation featuring a
+ 7-stage pipeline, separate instruction- and data caches, and a MMU.
+ For more information, please see the "AVR32 AP Technical Reference":
+
+ http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
+
+ In addition to this, the AT32AP7000 chip comes with a large set of
+ integrated peripherals, many of which are shared with the AT91 series
+ of ARM-based microcontrollers from Atmel. Full data sheet is
+ available here:
+
+ http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 7b64fef33c66be648826c0ff9758298ef13d0604
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:21:16 2006 +0200
+
+ Add AVR32 architecture support
+ Patch by Haavard Skinnemoen, 6 Sep 2006 16:23:02 +0200
+
+ This patch adds common infrastructure code for the Atmel AVR32
+ architecture. See doc/README.AVR32 for details.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 2da2d9a4766063b9848f3a35ad6025499cf87265
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 13:57:33 2006 +0200
+
+ Use -g instead of -gstabs in AFLAGS_DEBUG
+ Patch by Haavard Skinnemoen, 30 Aug 2006
+
+ In config.mk, -Wa,-gstabs is unconditionally appended to AFLAGS no
+ matter what the target's preferred debugging format is. This patch
+ simply replaces -gstabs with -g, so that the default debugging format
+ for the architecture is used.
+
+commit 965829872169c2996023840d98e1d85ad148d629
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 13:55:18 2006 +0200
+
+ Fix/workaround broken dependency handling with make 3.81
+ Based on patch by Haavard Skinnemoen, 29 Aug 2006 11:20:39 +0200
+
+commit 8318fbf8cc30418b621ea9f39b84b4c1a08f003a
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Mon Oct 23 22:17:05 2006 +0200
+
+ Fix sequoia separate object direcory building problems.
+
+commit 3dfa9cfdcee78b30da3432318b32821ffabe974b
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 20 17:16:35 2006 -0500
+
+ Use generic I2C register block on 85xx and 86xx.
+
+ Replace private IMMAP I2C structures with generic reg block
+ and allow 86xx to have multiple I2C device busses.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit f5012827df11ca0c9be1df5f8b153e188dc2fa7c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 20 15:54:34 2006 -0500
+
+ Fix compilation warnings on a few 85xx boards.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 2047672684cf85cb6f96a1fbc993180aaaf19a99
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 20 15:50:15 2006 -0500
+
+ Converted all 85xx boards to use a common FSL I2C driver.
+ Introduced COFIG_FSL_I2C to select the common FSL I2C driver.
+ And removed hard i2c path from a few u-boot.lds scipts too.
+ Minor whitespace cleanups along the way.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 4d45f69e362b05892c9e92a7907e5820995612aa
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 19 12:02:24 2006 -0500
+
+ Rewrite a series of goto statements as a sequences of
+ conditional expressions instead.
+
+ Use consistent return code 0/-1 for good/bad indicators.
+
+ Include one fewer file if the driver isn't used at all.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 7237c033b02fe295880435f1eb80819a0c987532
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 19 11:02:16 2006 -0500
+
+ Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c
+
+ in an effort to begin to unify the umpteen FSL I2C drivers that
+ are all otherwise very similar.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 13a7fcdf37f6ea9429ae04c9df67f893364cfe4b
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 19 11:33:52 2006 -0500
+
+ * Fix a bunch of compiler warnings for gcc 4.0
+
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
+
+commit 5f3249a0a168e446a4cc9669b2bce0bc456f0a09
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 13 16:47:53 2006 -0500
+
+ Fixed leading whitespace issues.
+ Removed spurious LAWAR thing.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 0ee90cb77e01d6e8ccd37e1bd96678597875c391
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 12 10:42:36 2006 -0500
+
+ Remove unneeded include files and local variable.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 1eaf3a5ff4960a46f3a9063568ba2af7883f07c5
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Oct 10 00:23:32 2006 -0600
+
+ Fix possible uninitialized variable compiler warning.
+
+ When CONFIG_OF_FLAG_TREE is set, the compiler complains that 'len' in
+ do_bootm_linux() may be uninitialized. There is no possibility in the
+ current code that len will get used uninitialized, but this fix follows
+ the existing convention of setting both len and data to zero at the same
+ time.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 7376eb87aaa601f728f9b8e5e9cd2711a67f529e
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Oct 11 15:13:01 2006 -0500
+
+ * Fix a bunch of compiler warnings for gcc 4.0
+
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
+
+commit bf651baa365e5447246aad6a633ccd667cf24a39
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Oct 11 10:10:43 2006 -0500
+
+ Move "ar" flags to config.mk to allow for silent "make -s"
+
+commit 1fd5699a4a24f5c1dab1b32f480bace1ebb9fc3e
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:19:03 2006 -0500
+
+ Coding style changes to remove local varible blocks
+ and reformat a bit nicer.
+
+commit 8b283dbb3a08d1b8d406bc15f119e081b3e2606a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:16:04 2006 -0500
+
+ Fix whitespace issues.
+
+commit 7b382b7125f2397cce63253df62f183e3dfa2770
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:14:45 2006 -0500
+
+ Fix whitespace issues.
+
+commit e10390ddd736b0dad1528eec4b0fe35c0827139a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:06:53 2006 -0500
-* Add monitor functions for indirect access to PPC440 DCR's
- Patch by Leonid Baryudin, 12 Oct 2006
+ Fix whitespace issues.
+
+commit 89875e96ba3f023157bf50d5f8e33bf254964a76
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:03:43 2006 -0500
+
+ Ran lindent and cleaned up whitespace issues.
+ Format for 80-columns too.
-* PPC405EP: Add support for board configuration of CPC0_PCI register
- This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
- Patch by Tolunay Orkun, 07 Apr 2006
+commit 333961ae7095fc66d8a041fce1ac9ee873b09d86
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:02:22 2006 -0500
-* PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
- - Add configuration of Open Drain GPIO Output selection
- - Add configuration of initial value of GPIO output pins
- Patch by Tolunay Orkun, 07 Apr 2006
+ Fix whitespace and 80-col issues.
-* Fix spelling; minor code cleanup.
+commit f55df18187e7a45cb73fec4370d12135e6691ae1
+Author: John Traill <john.traill@freescale.com>
+Date: Fri Sep 29 08:23:12 2006 +0100
-* Fix JFFS2 compilation problem
- Patch by Stefan Roese, 12 Oct 2006
+ Fix missing tCycle/modfreq calculation.
+
+ Signed-off-by: John Traill <john.traill@freescale.com>
-* Cleanup of NAND update patch (remove changelog from cmd_nand.c)
- Patch by Guido Classen, 10 Oct 2006
+commit 8272dc2f58f2473d8995fcc9b916440cfba080f0
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Sep 13 10:33:35 2006 -0500
-* Several improvements to the new NAND subsystem:
- - JFFS2 related commands implemented in mtd-utils style
- - Support for bad blocks
- - Bad block testing commands
- - NAND lock commands
- Please take a look at doc/README.nand for more details
- Patch by Guido Classen, 10 Oct 2006
+ Updated config headers to add default FDT-based booting
-* Define IH_CPU_AVR32
- Make it possible to generate AVR32 uImage files with mkimage and
- make cmd_bootm recognize them.
- Patch by Haavard Skinnemoen, 22 Sep 2006
+commit 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Sep 13 10:34:18 2006 -0500
-* Fix buffer overflow problem in ft_build.c
- Patch by Fredrik Roubert, 09 Oct 2006
+ Add support for eTSEC 3 & 4 on 8548 CDS
+
+ * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS.
+ This will only work on rev 1.3 boards (but doesn't break older boards)
+ * Cleaned up some comments to reflect the expanded role of tsec
+ in other systems
-* Make bootp implementation RFC3046 compliant
- Patch by Joakim Larsson, 27 Jun 2006
+commit 084d648b109c8984f83674043c1a7fa3885ef801
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Sep 13 10:33:56 2006 -0500
-* TQM5200: perform POST memory test only on STK52xx carrier board.
- (and then only if PSC6_3 is read as "1" when booting).
- Patch by Martin Krause, 21 Jun 2006
+ Added code to support 2.6.18 PCI changes in u-boot
+
+ * Added code to swizzle the IRQ map for the PCI
-* Move "ar" flags to config.mk to allow for silent "make -s"
- Based on patch by Mike Frysinger, 20 Jun 2006
+commit afbdc649f8751e4f4f1a6f527edfe139773f2c15
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Sep 19 09:34:10 2006 -0500
-* Coding style cleanup
+ Modified makefile for new build mechanism.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Add support for EP82xxM boards
- Patch by Aaron Sells, 20 Jun 2006
+commit d14ba6a798beb753e7a864500414fcc2d198b8bc
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Sep 14 08:40:36 2006 -0500
-* Fix comments in include/ppc440.h
- Patch by Martin Hicks, 16 Jun 2006
+ Handle 86xx SVR values according to the new Reference Manual.
+ Both 8641 and 8641D have SVR == 0x8090, and are distinguished
+ by the byte in bits 16-23 instead.
+ Thanks to Jason Jin for noticing.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Update for CAM5200 board:
- - Map in a additional chip selects CS4 and CS5.
- - Modify the port configration, configure six UARTs and no PCI,
- ATA and USB.
- - Add custom flash driver to handle specific byte swapping
+commit 88c8f4921fc47fb0eb2384b16586f1bd7f275be7
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Mon Aug 28 14:25:31 2006 +0800
-* Fix TLB setup for Ocotea board
- Patch by Stefan Roese, 30 Sep 2006
+ Fixed an OF-tree off-by-one bug when adding a new property name.
+ This bug will cause the kernel booting to pause a long time.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+ (cherry picked from 2f15776ccc6dc32377d8ba9652b8f58059c27c6d commit)
-* Fix reset problem in sequoia sdram init code
- Patch by Stefan Roese, 23 Sep 2006
+commit 9bff7a69a885adebbd2bd45990494ec4cf998a30
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 29 11:05:09 2006 -0500
-* Disable autoboot abort for FO300 when silent mode is enabled
- (according to S1 switch setting).
+ Remove trailing empty lines.
-* Cleanup examples binaries
+commit cd6d73d5b895a5935ac4fde0a356288142a584e0
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 29 09:48:49 2006 -0500
-* Add support for AMCC Rainier PPX440GRx eval board
- Patch by Stefan Roese, 13 Sep 2006
+ Remove bogus msync and use volatile asm.
-* Add NAND environment support for PPC440EPx Sequoia NAND boot config
- Patch by Stefan Roese, 12 Sep 2006
+commit 778d45049ce5927b65b3ff1d8e6692b654bdd49e
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 29 08:17:14 2006 -0500
-* Update NAND boot documentation
- Patch by Stefan Roese, 12 Sep 2006
+ Add myself as maintainer for MPC8641HPCN.
-* Fix alignment problem in "mtdparts" command
+commit 2f15776ccc6dc32377d8ba9652b8f58059c27c6d
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Mon Aug 28 14:25:31 2006 +0800
-* Add documentation on the latest build environment extensions to
- the README file.
+ Fixed an OF-tree off-by-one bug when adding a new property name.
+ This bug will cause the kernel booting to pause a long time.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
-* Remove dead code (i2o and dma) from cpu/mpc824x/drivers/ directory.
+commit 5567806b67d0ae83493aa8823ad3b6c914f581d7
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Aug 25 14:38:34 2006 -0400
-* Fix LOG_DIR directory creation error.
- Add support for automatic creation of BUILD_DIR directory.
+ Change ramdiskaddr and dtbaddr
+ Remove PEX fluff commands.
+
+ Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Fix build problem cpu/ppc4xx/ndfc.c
- Patch by Stefan Roese, 07 Sep 2006
+commit b2b78421d9db49c21a821af8a19c21c1f7dfb29e
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Aug 23 13:32:45 2006 -0500
-* Fix build problem with CPCI440
- Patch by Stefan Roese, 07 Sep 2006
+ * Another small fix for booting with disable_of
+
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Change Yellowstone to use CFI write buffer
- Patch by Stefan Roese, 07 Sep 2006
+commit 4a7cc0f21918e6ecf07ed57075d67df2c4a1299c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Aug 23 11:04:43 2006 -0500
-* Add support for AMCC Sequoia PPC440EPx eval board
- - Add support for PPC440EPx & PPC440GRx
- - Add support for PPC440EP(x)/GR(x) NAND controller
- in cpu/ppc4xx directory
- - Add NAND boot functionality for Sequoia board,
- please see doc/README.nand-boot-ppc440 for details
- - This Sequoia NAND image doesn't support environment
- in NAND for now. This will be added in a short while.
- Patch by Stefan Roese, 07 Sep 2006
+ Cleanup and lindent new AHCI driver.
-* Fix mkimage -l bug with multifile images on 64bit platforms
- Patch by David Updegraff, 06 Sep 2006
+commit dabf9ef8c10b4dead5ef2106ef742b1c06b542de
+Author: Jin Zhengxiong <jason@bus.ap.freescale.net>
+Date: Wed Aug 23 19:15:12 2006 +0800
-* Fix build problems on sorcery board.
+ Add AHCI define and sata support for MPC8641HPCN board.
+
+ Signed-off-by:Jason Jin<jason.jin@freescale.com>
-* Fix coldfire build problems.
- Patch by Marian Balakowicz, 01 Sep 2006
+commit 4782ac80b02f0d01afd309e2200dd3c7037f2ba4
+Author: Jin Zhengxiong <jason@bus.ap.freescale.net>
+Date: Wed Aug 23 19:10:44 2006 +0800
-* Add support for a saving build objects in a separate directory.
- Modifications are based on the Linux kernel approach and support
- two use cases:
- 1) Add O= to the make command line 'make O=/tmp/build all'
- 2) Set environement variable BUILD_DIR to point to the desired location
- 'export BUILD_DIR=/tmp/build'
- 'make'
- The second approach can also be used with a MAKEALL script
- 'export BUILD_DIR=/tmp/build'
- './MAKEALL'
- Command line 'O=' setting overrides the BUILD_DIR environent variable.
- When none of the above methods is used the local build is performed
- and the object files are placed in the source directory.
+ Add AHCI support to u-boot
+
+ Add AHCI support in u-boot, enable the sata disk controllers which
+ following the AHCI protocol.
+
+ Signed-off-by:Jason Jin<jason.jin@freescale.com>
-* Remove the board/netstar/crcit binary from git repository.
+commit d8ea2acf5f137cae99417df4f573d036ee384668
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Wed Aug 23 17:54:32 2006 +0800
-* Fix tools/updater build error.
+ Add dtb boot-up parameter to default boot commands.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
-* Fix tools/easylogo build error.
+commit b93775c2036b99baa390ea425c4771895bbc63c4
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 18:26:08 2006 -0500
-* Fixed problems on PRS200 board caused by adding splash screen on MCC200
+ Cleanup even more poorly introduced whitespace.
-* Extended README entry on coding style
+commit ae6241685cbcf0c79a3636530d2ceab1fb291a94
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 18:07:00 2006 -0500
-* Added another example showing simple interrupt interception.
+ Cleanup more poorly introduced whitespace.
-* Added simple_strtoul(), getenv() and setenv() to the exported functions.
- Also bumped up ABI version to reflect this change.
+commit 2c33e8a1c535b3ae91cf0b284480600bf3f57c57
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 17:54:05 2006 -0500
-* Added interrupt handling capabilities for mpc5xxx processors.
- Also added Linux like BUG() macros.
+ Cleanup poorly introduced whitespace.
-* Coding Style cleanup.
- Patch by Stefano Babic, 31 Aug 2006
+commit 80e955c7dd98f4b4fd23c2113caf75ed2b77b5b3
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 12:25:27 2006 -0500
-* Add splashscreen support for MCC200 board.
+ General indent and whitespace cleanups.
-* Make the serial driver framework work with CONFIG_SERIAL_MULTI
- enabled
+commit ffff3ae56f5842ca3679e4ce7922b819a87aad9f
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 12:06:18 2006 -0500
-* PCIe endpoint support for AMCC Yucca 440SPe board
- Patch by Tirumala R Marri, 26 Aug 2006
+ General indent and whitespace cleanups.
-* Improve DIMM detection for AMCC Yucca 440SPe board
- Improved the memory DIMM detection for the Yucca 440SPe board for
- the case where a memory DIMM is falsely detected as present.
- This issue is seen on some AMCC Yucca 440SPe validation boards if
- only one 512MB memory DIMM is installed, i.e. DIMM slot 0 is
- populated and DIMM slot 1 is empty. In this case, U-Boot does
- not correctly detect that there is only one DIMM memory module
- installed and will falsely detect two DIMM memory modules are
- present and therefore U-Boot will not calculate the correct amount
- of total memory and u-boot will not booting up.
- Patch by Adam Graham, 24 Aug 2006
+commit 41a0e8b304d3ff55fe27a230507aac79684016ac
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 10:42:21 2006 -0500
-* Fix typo.
+ Cleanup compiler warnings.
-* Code cleanup
+commit 5de62c47a8628b3da4d73f7c07027f32a3342d40
+Author: Matthew McClintock <msm@freescale.com>
+Date: Tue Aug 22 09:31:59 2006 -0500
-* Update for MCC200 / PRS200 boards:
- - auto-adjust console device for Linux.
- - fix typos.
+ Fix disable_of booting
+
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Add a fix for a buggy USB device on the FO300 board.
+commit 87a449c8ac396420cb24260f717ea9e6faa82047
+Author: Matthew McClintock <msm@freescale.com>
+Date: Tue Aug 22 09:23:55 2006 -0500
-* Updates for MCC200 / PRS200 boards:
- - support for configurations with SDRAM or DDR memory,
- - support for highboot and lowboot
- - adjusting environment definitions
+ Support for FDT in uImage format, error when using FDT from flash
+
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Add support for WTK FO300 board (TQM5200 based).
+commit 75c299c38369d01addd5e054b8a16217b70f4a86
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:12:55 2006 -0400
-* Fix TQM834x hang.
+ Unlock cache before kernel starts up for MPC86xx
-* Update for SC520 board.
- Patch by David Updegraff, 02 Dec 2005
+commit 67256678f00c09b0a7f19e862e5c1847553d31bc
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:13:15 2006 -0400
-* Fixed common.h spelling error.
- Patch by Cory Tusar, 30 Nov 2005
+ Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR
-* Fix typo.
- Patch by Andreas Engel, 28 Nov 2005
+commit 1c8f6d8fb028f156094d05f2d14298e6479364ac
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:12:55 2006 -0400
-* Fix fatload command on FAT32 formatted partitions.
- Patch by Joachim Jaeger, 18 Nov 2005
+ Unlock cache before kernel starts up for MPC86xx
-* Fix drivers/dm9000.c when configured in 32 bit mode.
- Patch by Eric Benard, 17 Nov 2005
+commit 0d9ccc55edf9a7f3c5b2b6263580a6ea8d702a04
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:13:15 2006 -0400
-* Cleanup debug code for yucca board.
+ Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR
-* MCC200: restrict addressable flash space to 32 MB
+commit 86c8e17f25e972a7e272950a0735fad84e082b88
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Aug 16 13:59:47 2006 -0500
-* Add debug console on COM12 for MCC200 board
+ * Fix disable_of booting
+
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Fix control-c handing in CONFIG_CMDLINE_EDITING
- Properly pass break code back from readline.
- Patch by Roger Blofeld, 31 Jul 2006
+commit 25c751e9adc86e22fe3b5b47cf2806379b575db7
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Aug 16 10:54:09 2006 -0500
-* Add commandline history support to all AMCC eval boards
- Patch by Stefan Roese, 07 Aug 2006
+ * Support for FDT in uImage format, error when using FDT from flash
+
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Add Macronix MXLV320T flash support for AMCC Bamboo
- Patch by Stefan Roese, 07 Aug 2006
+commit fecf1c7e4de1b2779edc18742b91c22bdc32b68b
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Mon Aug 14 15:33:38 2006 -0500
-* Change "mii info" to not print an error upon missing PHY at address
- Patch by Stefan Roese, 07 Aug 2006
+ Fix BAT0 to actually be cacheable, non-guarded as documented.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Fix PCI-Express on PPC440SPe rev. A.
+commit 40bc83559db5745681909fd7382ae509567e116d
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Aug 9 15:32:16 2006 -0500
-* Fix preboot message on TQM85xx after switching to hush parser.
+ Removed MPC8641HPCN DTS source file from build.
+ It is no longer linked into U-Boot; its sources are
+ now located in the kernel tree.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Adapt TQM85xx ramdisk address to Linux kernel memory map
+commit 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:47:03 2006 -0500
-* Add initial support for PCI-Express on PPC440SPe (Yucca board).
+ * Switched default PCI speed for 8540 ADS back to 33MHz
+
+ * Added comments and a printf to warn that PCI-X won't
+ work at 33MHz
+ Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Fix compiler warning for TRAB board.
- Patch by Martin Krause, 07 Aug 2006
+commit b6c5e1373b6ea0bb37a18e4aeecec00613d1cd39
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:35 2006 -0500
-* Prevent USB commands from working when USB is stopped.
+ * Fixed a bug where 8555 PCI code used the old variable and function names Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Add rudimentary handling of alternate settings of USB interfaces.
- This is in order to fix issues with some USB sticks timing out
- during initialization. Some code readability improvements.
+commit bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:13 2006 -0500
-* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
- AMCC suggested to set the PMU bit to 0 for best performace on
- the PPC440 DDR controller.
- Please see doc/README.440-DDR-performance for details.
- Patch by Stefan Roese, 28 Jul 2006
+ * Added VIA configuration table
+
+ * Added support for PCI2 on CDS
+ Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
- Please see doc/README.bamboo for details.
- Patch by Stefan Roese, 27 Jul 2006
+commit c88f9fe66b64247e5b6a38410ba315ca25596d16
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:41 2006 -0500
-* Fix CONFIG_CMDLINE_EDITING implementation
- Patch by Stefan Roese, 27 Jul 2006
+ * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Fix preboot message on TQM5200 after switching to hush parser.
+commit 97074ed9655309b64231bc2cee69fe85399f8055
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:17 2006 -0500
-* MCC200: set default configuration to low_boot DDR,
- and support for configurable options high_boot and/or SDRAM.
+ * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Add support for 256 MB SDRAM on CPU87
- Patch by Josef Wagner, 25 Nov 2005
+commit f0e6f57f71b3c4fdd13028eb03c3f3e91926dda2
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:49 2006 -0500
-* Add configuration for cam5200 board (based on TQM5200S).
+ * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* More code cleanup
+commit a4e11558b810ef2cddffdf7b9d86bc1130441960
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:23 2006 -0500
-* Disabled kvme080 board in MAKEALL because of build problems.
+ * Made sure the code which disables prefetch for PCI devices sets the size of the prefetch region to 0 Patch by Andy Fleming on 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Code cleanup
+commit 0e16387db1d4aacd5bf35cb6d7c1942765c0347b
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:36 2006 -0500
+
+ * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 855e6fb073f9d04fe4a7f06c107ecbac6344ddd4
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:00 2006 -0500
+
+ * Removed the oftree.dts for stxxtx in light of the changes to the flat device tree handling code Patch by Matthew McClintock 26-June-2006
+
+commit 5498d90312aad9f6bdbf047986027c35b03cd163
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:42:24 2006 -0500
+
+ * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006
+
+commit 0267768eddc5ca7bc1865bc40c866829ac5efbfe
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:41:37 2006 -0500
+
+ * Modify bootm command to support booting with flat device trees Patch by Matthew McClintock 26-June-2006
+
+commit 8fc8bd2cc479b6cd188fdede4010e0e052970b8a
+Author: John Traill <john.traill@freescale.com>
+Date: Wed Aug 9 14:33:50 2006 +0100
+
+ Add Rapidio support for the MPC8641HPCN
+
+ Signed-off-by: John Traill <john.traill@freescale.com>
+
+commit 91a414c7d1fb0eac912592cd995b30c9f23045c9
+Author: John Traill <john.traill@freescale.com>
+Date: Tue Aug 8 11:32:43 2006 +0100
+
+ Fix caslat calculation
+
+ Signed-off-by: John Traill <john.traill@freescale.com>
+
+commit 709d3073e74153278e7904a70819bbef7df50e1a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Aug 3 16:17:56 2006 -0500
+
+ Convert to mac-address in ethernet nodes.
+
+commit 71748af833ca1017edf1415be376366ff2937d17
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Jul 28 12:41:35 2006 -0400
+
+ Correct the irq value of DUART2
+
+commit 9cb3e8816ae4d854e7dc22128c3eea3d70bb982c
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Jul 28 12:41:41 2006 -0400
+
+ Change the space size of PEX IO in README
+
+commit 239db37c94f7a92941c4465feceb867c609241c5
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Jul 28 12:41:18 2006 -0400
+
+ Move get_board_sys_clk to board directory
+
+commit 492900b985439fbce1a118afde1e35def870db03
+Author: John Traill <john.traill@freescale.com>
+Date: Fri Jul 28 09:03:54 2006 +0100
+
+ Fix 8641HPCN pollution
+
+commit 515ab8a62e8574e2babc6e8dcc43544ad221c5b2
+Author: John Traill <john.traill@freescale.com>
+Date: Fri Jul 28 08:16:06 2006 +0100
+
+ Fix 8641HPCN timebase
+
+commit c86360b830f1eecd7a72208575dde4f57879faea
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Fri Jul 28 00:01:34 2006 +0800
+
+ Fixed OF device tree of mpc86xxhpcn board.
+
+ The changes works in with kernel irq mapping rework.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+
+commit bea3f28d285942bf3f7ab339ce85178ded544225
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Wed Jul 12 10:48:05 2006 -0400
+
+ Add support for reading and writing mac addresses to or from ID EEPROM.
+
+ Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
+ With attached patch, we can use command "mac/mac read/mac save/"
+ to read and write EEPROM under u-boot prompt.
+
+ U-boot will calculate the checksum of EEPROM while bootup,
+ if it is right, then u-boot will check whether the mac address
+ of eTSEC0/1/2/3 is availalbe (non-zero).
+
+ If there is mac address availabe in EEPROM, u-boot will use it,
+ otherewise, u-boot will use the mac address defined in
+ MPC8641HPCN.h. This matches the requirement to set unique mac address
+ for each TSEC port.
+
+ Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
+ Signed-off-by: York Sun <yorksun@freescale.com>
+
+commit fcb28e763415e0e4e66b0f45842d1557ae198e5e
+Author: Jin Zhengxiong <Jason.Jin@freescale.com>
+Date: Thu Jul 13 10:35:10 2006 -0500
+
+ Fixed initrd issue by define big RAM
+
+ Signed-off-by:Jason Jin <Jason.jin@freescale.com>
+
+commit e6cd2a1785d74ec3d30a86f1cb360be8de478151
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Fri Jul 7 10:01:45 2006 -0500
+
+ We made a u-boot patch to fix the hang up issue
+ when booting filesystem from ramdisk.
+
+ Signed-off-by:Jason Jin <Jason.jin@freescale.com>
+
+commit 38433ccc5850ee70549af0b2bc5b920355ef5388
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:47:03 2006 -0500
+
+ * Switched default PCI speed for 8540 ADS back to 33MHz
+ * Added comments and a printf to warn that PCI-X won't
+ work at 33MHz
+ Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit e4c2a0eb0c3e3ffbf824800184ee42bdc99d5b19
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:35 2006 -0500
+
+ * Fixed a bug where 8555 PCI code used the old variable and
+ function names
+ Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit cbfc7ce756b88eb26e5537bc7b625c445c6dcfac
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:13 2006 -0500
+
+ * Added VIA configuration table
+ * Added support for PCI2 on CDS
+ Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:41 2006 -0500
+
+ * Fixed PCI memory definitions
+ Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 087454609e47295443af793a282cddcd91a5f49c
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:17 2006 -0500
+
+ * Added support for initializing second PCI bus on 85xx
+ Patch by Andy Fleming 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit b636aaeb6fd516a442fb611bbeeddf3077a687fb
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:49 2006 -0500
+
+ * Added PCI-X #defines for PCI-X initialization
+ Patch by Andy Fleming on 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 20abbc6fffa115690107cc942c7abf84bdc03a1b
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:23 2006 -0500
+
+ * Made sure the code which disables prefetch for PCI devices
+ sets the size of the prefetch region to 0
+ Patch by Andy Fleming on 17-Mar-2006
+
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 40d5fa35d02df22580593bf0039ab173367e8ef0
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:36 2006 -0500
+
+ * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards
+ Patch by Jon Loeliger 17-Jan-2006
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit be7e8b0cb5a0c49dc180075b96df296a893bf146
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:00 2006 -0500
+
+ * Removed the oftree.dts for stxxtx in light of the changes
+ to the flat device tree handling code
+ Patch by Matthew McClintock 26-June-2006
+
+commit 1b380ec225665e73959677f3893dc658c5925e05
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:42:24 2006 -0500
+
+ * Patch to modify ft_build.c to update flat device trees in place
+ Patch by Matthew McClintock 26-June-2006
+
+commit 98a9c4d468a942a09ebe8979bec508017f3e4462
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:41:37 2006 -0500
+
+ * Modify bootm command to support booting with flat device trees
+ Patch by Matthew McClintock 26-June-2006
+
+commit da012ab661fd4ab169dd7b9b32201a4df62cf34a
+Author: Jin Zhengxiong <Jason.Jin@freescale.com>
+Date: Wed Jun 28 08:43:56 2006 -0500
+
+ Change Id to symbolic name for RTL8139
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit bc09cf3c2bfb8d54c659cbb332f79d0950982fd0
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:12:10 2006 +0800
+
+ Fix RTL8139 in big endian
+
+ signed-off-by: Jason Jin <Jason.Jin@freescale.com>
+ signed-off-by: Wei Zhang <wei.zhang@freescale.com>
+
+commit fcfb9a57947fc203b99fe81ab0578f7286261f9f
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:12:23 2006 +0800
+
+ Fix Tsec bug when no link
+
+ When tftp a non-exist file from the tftp server, u-boot will check
+ the link of all eth port. The original file will return wrong link
+ state on the no link ports.
+
+ signed-off-by: Jason Jin <Jason.Jin@freescale.com>
+
+commit bd22c2b97514fbfb0e03bd9c72b3445e4dbd57e2
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:12:02 2006 +0800
+
+ Fix bug for io_bar size during pci scan
+
+ During the pci scan process, Some devices return bar_reponse with the
+ highest bytes 0, such as the pci bridge in uli1575 return bar_response
+ with 0xffffff, So the bar_size should be manually set under 64K.
+
+ Signed-off-by: Jason Jin <jason.jin@freescale.com>
+
+commit fa7db9c377bc2353a17bf1d381d65a6c418728f0
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:11:54 2006 +0800
+
+ Enable PCIE1 for MPC8641HPCN board
+
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 684623ce92c5fd32e7db2d6e016945a67c5ffaba
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Jun 22 08:51:46 2006 -0500
+
+ Fix bug in 8641hpcn reset command with no args.
+
+ Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 8be429a5ddbf0ebe2d94174ba58fcfc7a24285dc
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Tue Jun 20 17:47:15 2006 +0800
+
+ Reworked IRQ mapping in OF-tree.
+
+commit 0e4c2a17ca34001ed36d259f13cb88ada4611a8c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Jun 15 21:33:37 2006 -0500
+
+ Do not enable address translation on secondary CPUs.
+ Do not set up BATs on secondary CPUs. Let Linux do the nasty.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 8ecc971618f56029ad99d3516f8b297a6ed58971
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed Jun 7 10:53:55 2006 -0500
+
+ Fix a get_board_sys_clk() use-before-def warning.
+
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
+
+commit d9bf4858fca5aa4d651b283270f77da72ebadfd5
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed Jun 7 10:52:49 2006 -0500
+
+ Allow DTC path to be passed in.
+
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
+
+commit c83ae9ea6d93abbe751bf8a3396236a084e56f87
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Jun 6 16:54:29 2006 -0400
+
+ Modify the IRQ of DUART2
+
+commit c934f655f9aeca70a5c5f88b465d9e9d57a8d22e
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 13:55:35 2006 -0500
+
+ Review cleanups.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit cb5965fb95b77a49f4e6af95248e0c849f4af03e
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 12:44:44 2006 -0500
+
+ White space cleanup.
+ Some 80-column cleanups.
+ Convert printf() to puts() where possible.
+ Use #include "spd_sdram.h" as needed.
+ Enhanced reset command usage message a bit.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 3d5c5be547445dd3bd2eb7368d80df03ea437970
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 11:39:34 2006 -0500
+
+ Removed unneeded local_bus_init() from 8641HPCN board.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 4d3d729c16c392d2982d3266b659d333c927697d
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 11:24:28 2006 -0500
+
+ Moved mpc8641hpcn_board_reset() out of cpu/ into board/.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit b2a941de060350ad15878d8219825f4950e9bb8e
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 10:07:28 2006 -0500
+
+ Remove dead debug code.
+
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
+
+commit 126aa70f10ba3d20e0a6f4d32328250513b77770
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue May 30 17:47:00 2006 -0500
+
+ Move mpc86xx PIXIS code to board directory
+
+ First cut at moving the PIXIS platform code out of
+ the 86xx cpu directory and into board/mpc8641hpcn
+ where it belongs.
+
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Update NetStar board
- Patch by Ladislav Michl, 03 Nov 2005
+commit 38cee12dcfcc257371c901c7e13e58ecab0a35d8
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue May 30 09:10:32 2006 -0500
-* Make code better readable.
- Patch by Ladislav Michl, 14 Sep 2005
+ Improve "reset" command's interaction with watchdog.
+
+ "reset altbank" will reset another bank WITHOUT watch dog timer enabled
+ "reset altbank wd" will reset another bank WITH watch dog enabled
+ "diswd" will disable watch dog after u-boot boots up successfully
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 70205e5a6ddc8528b11db9eb4d3fa0209d9fce2a
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue May 30 08:51:19 2006 -0500
+
+ Fix two SDRAM setup bugs.
+
+ Fix ECC setup bug.
+ Enable 1T/2T based on number of DIMMs present.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit d11fec5015334deb2010e36ce00bb118cc5429a5
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Fri May 26 10:24:48 2006 -0500
+
+ Add first draft of the MPC8641HPCN doc/README.
+
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
+
+commit ed45d6c930b5939718a87ee12e25cf9a05978d4a
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Fri May 26 10:13:04 2006 -0500
+
+ Added pci@8000 block.
+ Updated ethernet interrupt mappings (moved up 48).
+ Cleaned up a few comments.
+
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
+
+commit 3033ebb20fd7c372c7bca3c9955a4692bb2240b7
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Fri May 26 10:01:16 2006 -0500
+
+ Allow args on reset command.
+
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
+
+commit 14e37081ff3cac7ebe6e93836523429853b6b292
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:28:39 2006 -0500
+
+ Change arbitration to round-robin for SMP linux.
+
+commit 9a655876e5995be80f49054e2509500e871e4d3a
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:26:34 2006 -0500
+
+ Enable dual DDR controllers and interleaving.
+
+commit 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:22:44 2006 -0500
+
+ Update 86xx address map and LAWBARs.
-* Enable initrd ATAG for xm250 board.
- Patch by Josef Wagner, 05 Sep 2005
+commit cccce5d0581bb0ba4602799a4b5112e58d1579cb
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:14:15 2006 -0500
-* Add readline cmdline-editing extension
- Patch by JinHua Luo, 01 Sep 2005
+ Remove L2 Cache invalidate polling.
+
+commit f35ec68fb066cec0e36294bfe07dec2d4e8ad3a8
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 12:33:09 2006 -0500
+
+ Enable 2nd CPU and I2C.
-* Add support for friendly-arm SBC-2410X board
- Patch by JinHua Luo, 01 Sep 2005
+commit bf690dcb512d34c4fceec0eb1e5c0e88a9db5d54
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Mon May 15 07:26:56 2006 -0500
-* Fix multi-part image support on i386 platform.
- Patch by David Updegraff, 19 Aug 2005
+ Update interrupt mapping.
+
+commit 6cfea33477b04b63ed47386ed1629529484c33ba
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed May 10 09:38:06 2006 -0500
+
+ Remove unneeded INIT_RAM_LOCK cache twiddling.
+ Correctly tracks r29 as global data pointer now.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit d4dd317b58c126a2a7e73f4764ecc1a7c97f876c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed May 10 09:33:07 2006 -0500
-* Add support for KVME080 board
- Patch by Sangmoon Kim, 18 Aug 2005
+ Remove unnecessary flash.c file.
-* Fix MIPS LE build problem
- Patch by Matej Kupljen, 10 Aug 2005
+commit 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue May 9 08:23:49 2006 -0500
-* Check argument count in "mii" command.
- Problem pointed out by Andrew Dyer, 13 Jun 2005
+ Get MPC8641HPCN flash images working.
+
+ Enable the CFI driver.
+ Remove bogus LAWBAR7 cruft.
+ Use correct TEXT_BASE, Fixup load script.
+ Enable SPD EEPROM during DDR setup.
+ Use generic RFC 1918 IP addresses by default.
-* Cleanup TQM5200 board configurations:
- - make highboot configurations use environment at high end, too,
- to avoid flash fragmentation
- - always use redundand environment
- - don't enable video code for modules without graphics controller
- - provide useful (though different) mtdparts settings
- - get rid of CONFIG_CS_AUTOCONF which was always set anyway
+commit 5c9efb36a6b5431423f52888a0e3b4b515fe7eca
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Apr 27 10:15:16 2006 -0500
-* Extend mkconfig tool to print more useful target name
+ Cleanup whitespaces and style issues.
+ Removed //-style comments.
+ Use 80-column lines.
+ Remove trailing whitespace.
+ Remove dead code and debug cruft.
-* Add support for high-boot on TQM5200 and TQM5200S boards.
- Hint: the CPLD on the TQM5200 must be programmed with a software
- version supporting the high boot option! The new TQM5200S is
- already supporting this option. On the TQM5200 this option will be
- supported in configurations with MPC5200 rev B processors.
- To actually "high boot", set jumper X30 on the STK52xx.
- Patch by Martin Krause, 12 Jul 2006
+commit a2320a6bf8113a09544c42d160d10ac69d049a03
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Apr 27 08:22:39 2006 -0500
-* Add support for new TQM5200 revisions
- - Support for TQM5200S (short version without graphic controller)
- - Support for modules with 'N' type S29GL128N Spansion flashes
- (requires changes to flash layout)
- - Support for MPC5200B cpu (mostly support for second SDRAM bank)
- Patch by Martin Krause, 07 Jul 2006
+ Revert bad PCI prefetch limit change.
-* Fix support for PS/2 keyboard on TQM85xx boards
- The PS/2 keyobard driver for the TQM85xx modules only supports the
- internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
- include a DUART, the TQM8560 modules can't be used with the PS/2
- keyboard controller on the STK85xx board.
- The PS/2 keyboard driver should work with the modules TQM8540,
- TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
- Make sure the PS/2 controller on the STK85xx is programmed. Jumper
- settings: X66 1-2, 9-10; X61 2-3
- Patch by Martin Krause, 21 Jun 2006
+commit debb7354d1ea4f694154818df5e5b523f5c1cc1d
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Apr 26 17:58:56 2006 -0500
-* Adjust RTC century handling on STK52xx board to match Linux driver.
- Patch by Martin Krause, 12 Jun 2006
-
-* Adjust filenames for USB update images on TRAB board.
- During an automatic update via USB stick, U-Boot searches for
- images with the name "firmware.img" and "kernel.img". This names
- are now changed to "firmw_01.img" and "kernl_01.img". This is done,
- to prevent updates of new boards (with the new macronics "c" step
- flashes) with old, incompatible firmware or kernel versions.
- Patch by Martin Krause, 21 Jun 2006
-
-* Bugfix in VFD routine on TRAB board.
- Make sure upper lext pixel can be set to blue, too
- (so far only red was possible).
- Patch by Martin Krause, 15 Feb 2006
-
-* Enable buffered flash writes for TB5200 board.
-
-* Fix some bugs in TRAB board flash driver.
- - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
- - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
- - remove "Unlock Bypass" mode, because macronix flashes do not support
- this mode officially
- - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
- for Intel compatible flashes, not for AMD compatible.
- Patch by Martin Krause, 15 Feb 2006
-
-* Add additional error messages to flash driver on TRAB board
- (for erase errors and timeout errors)
- Patch by Martin Krause, 14 Feb 2006
-
-* Add support for TB5200 board
- The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
- integrated in a little aluminium case.
- Patch by Martin Krause, 8 Jun 2006
-
-* Enable buffered flash writes for TQM5200 board.
-
-* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
-
-* Add support for TQM885D board.
- Patch by Martin Krause, 20 Mar 2006
-
-* Fix FEC initialisation: All MII configuration is done via FEC1
- registers, but MII_SPEED was configured according to FEC used. So
- if only FEC2 was used, this caused the real MII_SPEED register in
- FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages.
- Fix: always configure MII_SPEED on FEC1 only.
- Patch by Markus Klotzbuecher, 12 Jul 2006
-
-* Add support for SPC1920 board.
- Patch by Markus Klotzbuecher, 12 Jul 2006
-
-* MCC200 board: support console on any one of the Quad UART ports.
-
-* Fix error in flash protection calculation on MCC200 board.
-
-* Major PCMCIA Cleanup to make code better readable and maintainable.
- Notes:
- - Board-dependend code for RPXLITE and RPXCLASSIC-based boards
- placed to the drivers/rpx_pmcia.c file to avoid duplication.
- Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
- - drivers/i82365.c has been split into two parts located at
- board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
- the only boards using CONFIG_82365).
- - Changes were tested for clean build and *very* *few* boards.
-
-* Fix timer problems on AMCC yucca board.
- Set Timer Clock Select to use CPU clock as a timer input source.
-
-* Bring yucca config more in line with other AMCC boards.
-
-* Add AMCC bamboo board to MAKEALL build script.
-
-* Fix AMCC bamboo eval board compilation errors.
-
-* Add system memory to the PCI region list for AMCC PPC44x CPUs.
- Enabled it for Yucca board.
-
-* Cleanup config file and bootup output for Yucca board.
-
-* Fix CONFIG_440_GX define usage.
-
-* Remove autogenerated bmp_logo.h file.
-
-* Add support for AMCC 440SPe CPU based eval board (Yucca).
-
-* Call serial_initialize() before first debug() is used.
-
-* Cleanup trab board for GCC-4.x
-
-* VoiceBlue update: use new MTD flash partitioning methods, use more
- reasonable TEXT_BASE, update default environment and enable keyed
- autoboot.
- Patch by Ladislav Michl, 16. Aug 2005
-
-* Add forgotten changes for the PLEB 2 Board.
- Patch by David Snowdon, 13. Aug 2005
-
-* Add support for wrPPMC7xx/74xx boards
- Patch by Richard Danter, 12 Aug 2005
-
-* Add support for gth2 board
- Patch by Thomas Lange, Aug 11 2005
-
-* Add support for CONFIG_SERIAL_MULTI on MPC5xxx
- Patch by Martin Krause, 8 Jun 2006
-
- This patch supports two serial consoles on boards with
- a MPC5xxx CPU. The console can be switched at runtime
- by setting stdin, stdout and stderr to the desired serial
- interface (serial0 or serial1). The PSCs to be used as
- console port are definded by CONFIG_PSC_CONSOLE
- and CONFIG_PSC_CONSOLE2.
- See README.serial_multi for details.
-
-* Bugfix in I2C initialisation on S3C2400.
- If the bus is blocked because of a previously interrupted
- transfer, up to eleven clocks are generated on the I2CSCL
- line to complete the transfer and to free the bus.
- With this fix pin I2CSCL (PG6) is really configured as GPIO
- so the clock pulses are really generated.
- Patch by Martin Krause, 04 Apr 2006
-
-* Fix DDR6 errata on TQM834x boards
- Patch by Thomas Waehner, 07 Mar 2006
-
-* Remove obsolete flash driver board/tqm5200/flash.c
- Patch by Martin Krause, 11 Jan 2006
-
-* Update configuration for CMC-PU2 board
- Patch by Martin Krause, 17 Nov 2005
-
-* Add support for PS/2 keyboard on TQM85xx board
- Patch by Martin Krause, 07 Nov 2005
-
- Tested on a STK85XX baseboard. Make sure the PS/2 controller
- has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
-
-* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
- In tsc2000_read_channel() the delay after setting the multiplexer
- to a temperature channel is increased from 1,5 ms to 10 ms. This
- is to allow the multiplexer inputs to stabilize after huge steps
- of the input signal level.
- Patch by Martin Krause, 08 Nov 2005
-
-* Adjust TQM5200 make targets
- Make the automatic CS configuration the default.
- The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
- and CONFIG_TQM5200_AC are removed.
- "TQM5200_config" is now the default for STK52XX.200 base boards.
- On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
- Patch by Martin Krause, 07 Nov 2005
-
-* Fix setting of environment variable "ver" on trab board
- The environment variable "ver" is now set before
- do_auto_update() is called, so that "ver" can be used
- in USB update scripts.
- Patch by Martin Krause, 27 Oct 2005
-
-* Fix wrong usage of udelay() in led_blink() on trab board
- Patch by Martin Krause, 27 Oct 2005
-
-* Fix udelay bug in vfd.c for trab board
- Patch by Martin Krause, 27 Oct 2005
-
-* Disable JFFS2 support for trab board
- Patch by Martin Krause, 27 Oct 2005
-
-* Change mtdparts definition on trab board to match current flash map
- Patch by Martin Krause, 27 Oct 2005
-
-* Fix memory init problems on MCC200 board
-
-* Fix IxEthDB.h to compile again
- Patch by Stefan Roese, 14 Jun 2006
-
-* Minor cleanup for PCS440EP board
- Patch by Stefan Roese, 13 Jun 2006
-
-* Add MCF5282 support (without preloader)
- relocate ichache_State to ram
- u-boot can run from internal flash
- Add EB+MCF-EV123 board support.
- Add m68k Boards to MAKEALL
- Patch from Jens Scharsig, 08 Aug 2005
-
-* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
- Patch by Scott McNutt, 08 Jun 2006
-
-* Nios II - Add EPCS Controller bootrom work-around
- -When booting from an epcs controller, the epcs bootrom may leave the
- slave select in an asserted state causing soft reset hang. This
- patch ensures slave select is negated at reset.
- Patch by Scott McNutt, 08 Jun 2006
-
-* Update PK1C20 board
- -Update base addresses for standard configuration
- -Eliminate use of CACHE_BYPASS in board code
- Patch by Scott McNutt, 08 Jun 2006
-
-* Nios II - Fix I/O Macros and mini-app stubs
- -Fix asm/io.h macros
- -Eliminate use of CACHE_BYPASS in cpu code
- -Eliminate assembler warnings
- -Fix mini-app stubs and force no small data
- Patch by Scott McNutt, 08 Jun 2006
-
-* Fix U-Boot environment sector protection on MCC200 board
-
-* Minor cleanup for PCS440EP board
-
-* Update PCS440EP port to fit into one flash device (incl. environment)
- Patch by Stefan Roese, 06 Jun 2006
-
-* Add support for PCS440EP board
- Patch by Stefan Roese, 02 Jun 2006
-
-* Fix examples/Makefile; some build targets were lost
-
-* Fix watchdog handling in CFI flash driver
- Just use udelay() when waiting for status changes which will
- implicitely trigger the watchdog.
-
-* Fix PCI to memory window size problems on PM82x boards
- We use the "automatic" mode that was used for the MPC8266ADS and
- MPC8272 boards. Eventually this should be used on all boards?]
- Patch by Wolfgang Grandegger, 17 Jan 2006
-
-* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
- Patch by Stefan Roese, 29 May 2006
-
-* Update Intel IXP4xx support
- - Add IXP4xx NPE ethernet MAC support
- - Add support for Intel IXDPG425 board
- - Add support for Prodrive PDNB3 board
- - Add IRQ support
- Patch by Stefan Roese, 23 May 2006
-
-* Fix problem in PVR detection for 440GR
- Patch by Stefan Roese, 18 May 2006
-
-* Fix gcc 3.4.x AFLAGS setting for m68k platform.
-
-* Enable autoboot for M5271EVB board.
-
-* Changed default ramdisk addr in yosemite/yellowstone ports
- Patch by Stefan Roese, 15 May 2006
-
-* Fix PCMCIA support on virtlab2
-
-* Add support for VirtLab2 board
- (needed because of differences in the PCMCIA hardware).
-
-* Minor cleanup.
-
-* Update yosemite configuration to enable flash write buffer support
- Patch by Stefan Roese, 10 May 2006
-
-* Fix compile warnings in common/xyzModem.c
- Patch by Stefan Roese, 10 May 2006
-
-* Add support for AMCC 440EP Rev C and 440GR Rev B
- Patch by John Otken, 08 May 2006
-
-* OMAP 5912/OSK: update EMIFS CS1 timings:
- Problems have been seen in the linux kernel's smc91x network driver
- due to improper bus timings. The latest 2.6 OMAP kernels currently
- have a workaround, but this fix belongs in u-boot.
- Patch by Kevin Hilman, 13 Oct 2005
-
-* Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports
- Patch by Hiroki Kaminaga, 11 Mar 2006
-
-* Update omap5912osk board support
- - Fix OMAP support that omap5912osk compiles in current source tree
- - Update with code from "http://omap.spectrumdigital.com/osk5912"
- to fix problems with DDR initialization
- - Fix timer setup
- - Use CFI flash driver and support complete 32MB of onboard flash
- - Add "print_cpuinfo()" and "checkboard()" functions to display
- CPU (with frequency) and Board infos
- Patch by Stefan Roese, 10 May 2006
-
-* Fix watchdog issues for ColdFire boards.
-
-* Add M5271EVB board support.
-
-* Make R5200 specific low level initialization board conditional.
-
-* Update CPU target identification strings for ColdFire family.
-
-* Update register definitions for MCF5271.
-
-* Fix serial console support for MCF5271.
-
-* Fixes for gcc 3.4 based m68k toolchain,
- based on patch by Jate Sujjavanich.
-
-* Fix lowboot support on MCC200 board
-
-* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:
- - Removed MPC8349ADS port
- - Added PCI support to MPC8349ADS
- - reworked memory map to allow mapping of all regions with BATs
- Patch by Kumar Gala, 20 Apr 2006
-
-* Coding Style cleanup
-
-* Write RTC seconds first to maintain settings integrity per
- Maxim/Dallas DS1306 data sheet.
- Patch by Alan J. Luse, 02 May 2006
-
-* Scheduled for removal: strnicmp() which is unused
-
-* Update for Intel Monahans boards:
- - support for magic key detection and handling on delta board
- - NAND support for zylonite board + some minor cleanup
-
-* Declare load_serial_ymodem() when using CFG_CMD_LOADB.
- Patch by Jon Loeliger, 01 May 2006
-
-* Fixed handling of bad checksums with "mkimage -l"
-
-* Added support for BC3450 board
- Patch by Stefan Strobl, 21 Oct 2005
-
-* Update for NC650 board:
- - Support rev1 and rev2 hardware
- - adapt to new NAND layer
- - add CP850 configuration based on NC650
-
-* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
- is configured; othrwise DMA accesses aren't cache coherent which
- causes for example USB to fail.
-
-* Some code cleanup
-
-* Fix dbau1x00 boards broken by dbau1550 patch
- PLL:s were not set for boards other than 1550.
- Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
- Default boot is now bootp for cards other than 1550.
- Patch by Thomas Lange, 10 Aug 2005
-
-* Fixes common/cmd_flash.c:
- - fix some compiler/parser error, if using m68k tool chain
- - optical fix for protect on/off all messages, if using more
- then one bank
- Patch by Jens Scharsig, 28 Jul 2005
-
-* Fix Quad UART mapping on MCC200 board due to new HW revision
-
-* Fix JFFS2 support for legacy NAND driver.
-
-* Remove dependencies between DoC code and old legacy NAND driver.
-
-* Fix PM828_PCI target, for which PCI was *not* configured in.
-
-* Fix Lite5200B support: initialize SDelay register
- See Freescale's AN3221 "MPC5200B SDRAM Initialization and
- Configuration", 3.3.1 SDelay--MBAR + 0x0190
-
-* Changes/fixes for drivers/cfi_flash.c:
-
- - Add Intel legacy lock/unlock support to common CFI driver
-
- On some Intel flash's (e.g. Intel J3) legacy unlocking is
- supported, meaning that unlocking of one sector will unlock
- all sectors of this bank. Using this feature, unlocking
- of all sectors upon startup (via env var "unlock=yes") will
- get much faster.
-
- - Fixed problem with multiple reads of envronment variable
- "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
-
- - Removed unwanted linefeeds from "protect" command when
- CFG_FLASH_PROTECTION is enabled.
-
- - Changed p3p400 board to use CFG_FLASH_PROTECTION
-
- Patch by Stefan Roese, 01 Apr 2006
-
-* Changes/fixes for drivers/cfi_flash.c:
- - Correctly handle the cases where CFG_HZ != 1000 (several
- XScale-based boards)
- - Fix the timeout calculation of buffered writes (off by a
- factor of 1000)
- Patch by Anders Larsen, 31 Mar 2006
-
-* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
-
- 405 SDRAM: - The SDRAM parameters can now be defined in the board
- config file and the 405 SDRAM controller values will
- be calculated upon bootup (see PPChameleonEVB).
- When those settings are not defined in the board
- config file, the register setup will be as it is now,
- so this implementation should not break any current
- design using this code.
-
- Thanks to Andrea Marson from DAVE for this patch.
-
- 440 DDR: - Added function sdram_tr1_set to auto calculate the
- TR1 value for the DDR.
- - Added ECC support (see p3p440).
-
- Patch by Stefan Roese, 17 Mar 2006
-
-* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
- Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
-
-* Add support for ymodem protocol download
- Patch by Stefano Babic, 29 Mar 2006
-
-* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
- Merge from Markus Klotzbücher's repo, 01 Apr 2006
-
-* GCC-4.x fixes: clean up global data pointer initialization for all
- boards
-
-* Update for Delta board:
- - redundant NAND environment
- - misc Monahans cleanups (remove dead code etc.)
- - DA9030 Initialization; some minimal changes to PXA I2C driver to
- make it work with the Monahans.
- - Make Monahans clock frequency configurable using
- CFG_MONAHANS_RUN_MODE_OSC_RATIO and
- CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
- Merge from Markus Klotzbücher's repo, 25 Mar 2006
-
-* Enable Quad UART om MCC200 board.
-
-* Cleanup MCC200 board configuration; omit non-existent stuff.
-
-* Add support for MPC859/866 Rev. A.0
-
-* Add command for handling DDR ECC registers on MPC8349EE MDS board.
-
-* Fix DDR ECC bit definitions for MPC83xx.
-
-* Add initial support for MPC8349E MDS board.
-
-* Add support for ECC DDR initialization on MPC83xx.
-
-* Add DMA support for MPC83xx.
-
-* Add sync in do_reset() routine for MPC83xx after RPR register
- was written to. It is need on some targets when BAT translation
- is enabled.
-
-* Add bit definitions for MPC83xx DDR controller registers.
-
-* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
-
-* Correct shift offsets in icache_status and dcache_status for MPC83xx.
-
-* Add support for DS1374 RTC chip.
-
-* Add support for Lite5200B board.
- Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
-
-* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
- timer and cpu_reset code from cpu/$(CPU) into the new
- cpu/$(CPU)/$(SOC) directories
- Patch by Andreas Engel, 13 Mar 2006
-
-* Change max size of uncompressed uImage's to 8MByte and add
- CFG_BOOTM_LEN to adjust this setting.
-
- As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
- uImages was restricted to 4MBytes. This default size is now
- increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
- in the board config file.
-
- Patch by Stefan Roese, 13 Mar 2006
-
-* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
- Patch by Stefan Roese, 13 Mar 2006
-
-* cpu/ppc4xx/start.S : exceptions are enabled after relocation
- Patch by Cedric Vincent, 06 Jul 2005
-
-* au1x00_eth.c: check malloc return value and abort if it failed
- Patch by Andrew Dyer, 26 Jul 2005
-
-* Change the sequence of events in soft_i2c.c:send_ack() to keep from
- incorrectly generating start/stop conditions on the bus.
- Patch by Andrew Dyer, 26 Jul 2005
-
-* Fix bug in [id]cache_status commands for MPC85xx processors;
- should look at LSB of L1CSRn registers to determine if L1 cache is
- enabled, not the MSB.
- Patch by Murray Jensen, 19 Jul 2005
-
-* Fix array overflow with fw_setenv on uninitialised environment
- Patch by Murray Jensen, 15 Jul 2005
-
-* Add support for EmbeddedPlanet EP88x boards
- Patch by Yuli Barcohen, 13 Jul 2005
-
-* Remove board specific configuration includes from the common xilinx
- ethernet and iic adapter code.
- Patch by Michael Libeskind, 12 Jul 2005
-
-* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
- Patch by Murray Jensen, 08 Jul 2005
-
-* Add (some) definitions for the MPC85xx local bus controller
- Patch by Murray Jensen, 08 Jul 2005
-
-* Add CPM2 I/O pin functions for MPC85xx processors
- Patch by Murray Jensen, 08 Jul 2005
-
-* Fix compile problem
-
-* Added PCI support for MPC8349ADS board
- Patch by Kumar Gala 11 Jan 2006
-
-* Enable address translation on MPC83xx
- Patch by Kumar Gala, 10 Feb 2006
-
-* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
- Patch by Kumar Gala, 25 Jan 2006
-
-* Fixed defines for MPC83xx SICRL register to match current specs
- Patch by Kumar Gala, 23 Jan 2006
-
-* Only disable the MPC83xx watchdog if its enabled out of reset.
- If its disabled out of reset SW can later enable it if so desired
- Patch by Kumar Gala, 11 Jan 2006
-
-* Allow config of GPIO direction & data registers at boot on 83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Enable time handling on 83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Make System IO Config Registers board configurable on MPC83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Fixed PCI indirect config ops to handle multiple PCI controllers
- We need to adjust the bus number we are trying to access based
- on which PCI controller its on
- Patch by Kumar Gala, 12 Jan 2006
-
-* Report back PCI bus when doing table based device config
- Patch by Kumar Gala, 11 Jan 2006
-
-* Added support for PCI prefetchable region and BARs
- If a host controller sets up a region as prefetchable and
- a device's BAR denotes it as prefetchable, allocate the
- BAR into the prefetch region.
-
- If a BAR is prefetchable and no prefetchable region has
- been setup by the controller we fall back to allocating
- the BAR into the normally memory region.
- Patch by Kumar Gala, 11 Jan 2006
-
-* Add helper function for generic flat device tree fixups for mpc83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Add support for passing initrd information via flat device tree
- Patch by Kumar Gala, 11 Jan 2006
-
-* Added OF_STDOUT_PATH and OF_SOC
-
- OF_STDOUT_PATH specifies the path to the device the kernel can use
- for console output
-
- OF_SOC specifies the proper name of the SOC node if one exists.
- Patch by Kumar Gala, 11 Jan 2006
-
-* Allow board code to fixup the flat device tree before booting a kernel
- Patch by Kumar Gala, 11 Jan 2006
-
-* Added CONFIG_ options for bd_t and env in flat dev tree
-
- CONFIG_OF_HAS_BD_T will put a copy of the bd_t
- into the resulting flat device tree.
-
- CONFIG_OF_HAS_UBOOT_ENV will copy the environment
- variables from u-boot into the flat device tree
-
- Patch by Kumar Gala, 11 Jan 2006
-
-* Add support for the DHCP vendor optional bootfile (#67).
- Ignores the vendor TFTP server name option (#66).
- Patch by Murray Jensen, 30 Jun 2005
-
-* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
- Patch by Andy Fleming, 14 Jun 2005
-
-* Fix bad register definitions for LTX971 PHY on MPC85xx boards.
- Patch by Gerhard Jaeger, 21 Jun 2005
-
-* Add netconsole and some more commands to RPXlite_DW board
- Patch by Sam Song, 19 Jun 2005
-
-* Fix bad declaration on pci_cfgfunc_nothing
- Patch by Sam Song, 19 Jun 2005
-
-* Adjust "echo" as a default command
- Patch by Sam Song, 19 Jun 2005
-
-* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC
- Patch by KokHow Teh, 16 Jun 2005
-
-* Add crc of data to jffs2 (in jffs2_1pass_build_lists()).
- Patch by Rick Bronson, 15 Jun 2005
-
-* Coding Style cleanup
-
-* Avoid dereferencing NULL in find_cmd() if no valid commands were found
- Patch by Andrew Dyer, 13 Jun 2005
-
-* Add ADI Blackfin support
- - add support for Analog Devices Blackfin BF533 CPU
- - add support for the ADI BF533 Stamp uClinux board
- - add support for the ADI BF533 EZKit board
- Patches by Richard Klingler, 11 Jun 2005
-
-* Add loads of ntohl() in image header handling
- Patch by Steven Scholz, 10 Jun 2005
-
-* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
- variable to set clock
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* RPXlite configuration fixes
- - Use correct flash sector size
- - Use correct memory test end address
- - Add support for bzip2 compression
- - Various small fixes
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* Memory configuration changes for ZPC.1900 board
- - Fix SDRAM timing on both local bus and 60x bus
- - Add support for second flash bank (SIMM)
- - Change boot flash base
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* Add support for Adder boards with 16MB SDRAM;
- add support for second FEC on Adder87x board.
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* Fix conditional for including ks8695eth driver
- Patch by Greg Ungerer, 04 Jun 2005
-
-* Fix Makefile: include config.mk only after CROSS_COMPILE is defined
- Patch by Friedrich Lobenstock, 02 Jun 2005
-
-* Fix comment in common/soft_i2c.c
- Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005
-
-* Cleanup compiler warnings.
- Patch by Greg Ungerer, 21 May 2005
-
-* Word alignment fixes for word aligned NS16550 UART
- Patch by Jean-Paul Saman, 01 Mar 2005
-
- Fixes bug with UART that only supports word aligned access: removed
- "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some
- (broken!) versions of GCC generate byte accesses when encountering
- the packed attribute regardless if the struct is already correctly
- aligned for a platform. Peripherals that can only handle word
- aligned access won't work properly when accessed with byte access.
- The struct NS16550 is already word aligned for REG_SIZE = 4, so
- there is no need to packed the struct in that case.
-
-* Fix behaviour if gatewayip is not set
- Patch by Robin Gilks, 23 Dec 2004
-
-* Fix cleanup for netstart board.
- Remove build results from repository
-
-* Some code cleanup for GCC 4.x
-
-* Fixes to support environment in NAND flash;
- enable NAND flash based environment for delta board.
-
-* Add support for Intel Monahans CPU on Zylonite and Delta boards
- (This is Work in Progress!)
-
-* Add support for TQM8260-AI boards.
-
-* Minor code cleanup
-
-* Merge the new NAND code (testing-NAND brach); see doc/README.nand
- Rewrite of NAND code based on what is in 2.6.12 Linux kernel
- Patch by Ladislav Michl, 29 Jun 2005
-
-* Add lowboot target to mcc200 board
- Patch by Stefan Roese, 4 Mar 2006
-
-* Fix problem with flash_get_size() from CFI driver update
- Patch by Stefan Roese, 1 Mar 2006
-
-* Make CFG_NO_FLASH work on ARM systems
- Patch by Markus Klotzbuecher, 27 Feb 2006
-
-* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
- use hush shell.
-
-* Convert mcc200 to use common CFI flash driver
- Patch by Stefan Roese, 28 Feb 2006
-
-* Add env-variable "unlock" to handle initial state of sectors
- (locked/unlocked).
-
- Only the U-Boot image and it's environment is protected,
- all other sectors are unprotected (unlocked) if flash
- hardware protection is used (CFG_FLASH_PROTECTION) and
- the environment variable "unlock" is set to "yes".
-
- Patch by Stefan Roese, 28 Feb 2006
-
-* Update drivers/cfi_flash.c:
- - find_sector() called in both versions of flash_write_cfiword()
- Patch by Peter Pearse, 27th Feb 2006
-
-* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
- Patch by Jose Maria Lopez, 16 Jan 2006
-
-* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
- Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
-
-* Changes/fixes for drivers/cfi_flash.c:
- We *should* check if there are any error bits if the previous call
- returned ERR_OK (Otherwise we will have output an error message in
- flash_status_check() already.) The original code would only check for
- error bits if flash_status_check() returns ERR_TIMEOUT.
- Patch by Marcus Hall, 23 Aug 2005
-
-* Changes/fixes for drivers/cfi_flash.c:
- - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
- - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
- Patch by Sangmoon Kim, 19 Aug 2005
-
-* Fixes for drivers/cfi_flash.c:
- - Fix wrong timeout value usage in flash_status_check()
- - Round write_tout up when converting to msec in flash_get_size()
- - Remove clearing flash status at the end of flash_write_cfibuffer()
- which sets Intel 28F640J3 flash back to command mode on CSB472
- Patch by Tolunay Orkun, 02 July 2005
-
-* Add basic support for the SMMACO4 Board from PanDaCom.
- Patch by Heiko Schocher, 20 Feb 2006
-
-* Add GIT version information (commid ID) to untagged U-Boot versions
-
- As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
- of all unreleased (untagged) U-Boot images will be automatically
- extended upon compiletime with a part of the GIT commit ID and
- possibly with "dirty" if uncommited changes are detected.
-
- Here an example for the resulting version:
- "U-Boot 1.1.4-g3457ac18-dirty"
-
- The version is now maintained in the toplevel Makefile and the
- version headers are autogenerated.
-
- Patch by Stefan Roese, 9 Feb 2006
-
-* Update default environment for INKA4x00 board.
-
-* Convert CPCI750 to use common CFI flash driver
- Patch by Reinhard Arlt, 8 Feb 2006
-
-* Various changes to esd HH405 board specific files
- Patch by Matthias Fuchs, 07 Feb 2006
-
-* Cleanup U-Boot boot messages on ARM.
-
- To match the U-Boot user interface on ARM platforms to the U-Boot
- standard (as on PPC platforms), some messages with debug character
- are removed from the default U-Boot build.
- Enable DEBUG for lib_arm/board.c to enable debug messages.
- New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
- Patch by Stefan Roese, 24 Jan 2006
-
-* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
- Patch by Stefan Roese, 18 Jan 2006
-
-* Add VGA support (CT69000) to CPCI750 board.
- Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
- Patch by Reinhard Arlt, 30 Dec 2005
-
-* PMC405 and CPCI405: Moved configuration of pci resources
- into config file.
- PMC405 and CPCI2DP: Added firmware download and booting via pci.
- Patch by Matthias Fuchs, 20 Dec 2005
-
-* Add ColdFire targets to MAKEALL script
- Patch by Zachary Landau, 26 Jan 2006
-
-* Add support for r5200 board
- Patch by Zachary Landau, 26 Jan 2006
-
-* Add support for Freescale M5271 processor
- Patch by Zachary Landau, 26 Jan 2006
-
-* Fix 28F256J3A support on PM520 board
- (without bank-switching only 32 MB can be accessed)
-
-* Fix mkimage bug with multifile images created on 64 bit systems.
-
-* Add support for 28F256J3A flash (=> 64 MB) on PM520 board
-
-* Fix compiler problem with at91rm9200dk board.
- Patch by Eugen Bigz, 19 Dec 2005
-
-======================================================================
-Changes for U-Boot 1.1.4:
-======================================================================
-
-* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
- - Changed GPIO setup to enable another address line in order to
- address 64M of FLASH.
- - Added function sdram_tr1_set to auto calculate the tr1 value for
- the DDR.
- Patch by Steven Blakeslee, 12 Dec 2005
-
-* MPC5200: Set PCI retry counter to 0 = infinite retry;
- The default of 255 is too short for slow devices.
- Patch by Martin Nykodym, 12 Dec 2005
-
-* Change port configuration for O2DNT (CODEC1 on PSC1).
-
-* Fix register for PCI async mode on PPC440EP
- Patch by Youngchul Bang, 08 Dec 2005
-
-* Fix U-Boot linking problems (add .eh_frame segment to linker script)
- This segment may be required by some libgcc.a functions
- (like _udivdi3).
-
-* Fix DPRAM offset/size for MPC8541/8555.
- Simplify TQM85xx Makefile handling.
-
-* Fix data overflow (typo?) in rtc/ds1302.c
-
-* Fix U-Boot compilation for MIPS boards using ELDK 4.0
-
-* Add support for TQM8541/8555 boards, TQM85xx support reworked:
- - Support for TQM8541/8555 boards added.
- - Complete rework of TQM8540/8560 support.
- - Common TQM85xx code now supports all current TQM85xx platforms
- (TQM8540/8541/8555/8560).
- - DDR SDRAM size detection added.
- - CAS latency default values can be overwritten by setting "serial#"
- to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
- If problems are detected with this non default CAS latency,
- the default values will be used instead.
- - Flash size detection added.
- - Moved FCC ethernet driver initialization behind TSEC driver init
- -> TSEC is first device.
- Patch by Stefan Roese, 30 Nov 2005
-
-* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
- Patch by John Otken, 23 Nov 2005
-
-* Changed PPC44x startup message (cpu info, speed...) to common style:
- On PPC44x platforms, the startup message generated in "cpu.c" only
- comprised the ppc type and revision but not additional information
- like speed etc. Those speed infos where printed in the board specific
- code. This new implementation now prints all CPU infos in the common
- cpu specific code. No board specific code is needed anymore and
- therefore removed from all current 44x implementations.
- Patch by Stefan Roese, 27 Nov 2005
-
-* Adjust TQM834x PHY addresses for latest hardware revision.
-
-* Increase malloc arena on TQM5200 board to 256 kB.
- With 64 kb uniform flash sector size the old value of 128 kB was
- too small.
-
-* Fix miiphy global data initialization (problem on 4xx boards when
- no ethaddr is assigned). Initialization moved from
- miiphy_register() to eth_initialize().
-
- Based on initial patch for 4xx platform by Matthias Fuchs.
-
-* Remove unnnecessary #include <linux/types.h> from include/asm-*/u-boot.h
-
-* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code.
- The COPYING file was extended to make clear that these files can be
- used in non-GPL code, too.
- Also, a corresponding note was placed in the headers of the affected files.
-
-* Add support for Prodrive P3P440 board:
- - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
- - CFG_FLASH_QUIET_TEST added to use the common CFI driver
- for bank autodetection
- Patch by Stefan Roese, 22 Nov 2005
-
-* Change all '$(...)' variable references into '${...}'
- which makes the environment compatible with the hush shell.
- WARNING: Support for the old '$(...)' syntax will be
- discontinued in a later version.
-
-* Minor changes to init flags in TQM834x PCI.
-
-* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM)
- Patch by Stefan Roese, 15 Nov 2005
-
-* New PPC 405EP board added: CMS700
- Added CONFIG_NET_MULTI for VOM405 board.
- Added reset_phy() for VOM405 board.
- Patch by Matthias Fuchs, 09 Nov 2005
-
-* Updated PCI mapping for esd CPCI2DP board.
- Add support for error LED.
- Patch by Matthias Fuchs, 07 Nov 2005
-
-* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
- Patch by Stefan Roese, 07 Nov 2005
-
-* Correct PPC Timebase register definitions (SPRN_TBRL...)
- Patch by Stefan Roese, 07 Nov 2005
-
-* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
- Patch by Stefan Roese, 05 Nov 2005
-
-* Additional fix for external IRQ config on Yellowstone & Yosemite
- Patch by Stefan Roese, 03 Nov 2005
-
-* Add support for Ocotea pass 3 with 440GX Rev. F
- Patch by Stefan Roese, 01 Nov 2005
-
-* Fix external IRQ configuration on Yellowstone & Yosemite
- Patch by Stefan Roese, 28 Oct 2005
-
-* Add support for multiple PHYs.
- Tested on the following boards:
- cmcpu2 (at91rm9200/ether.c)
- PPChameleon (ppc4xx/4xx_enet.c)
- yukon (mpc8220/fec.c)
- uc100 (mpc8xx/fec.c)
- tqm834x (mpc834x/tsec.c) with EEPRO100
- lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
- Main changes include:
- common/miiphyutil.c
- - miiphy_register routine was added to allow multiple PHYs to be registered
- - miiphy_read and miiphy_write are now defined in this file, and
- require additional argument (char *devname)
- - other miiphy_* routines also require additional device name argument
- ../lib_i386/board.c
- ../lib_ppc/board.c
- Calling reset_phy() was moved to be executed *after* eth_initialize().
- This is necessary as now some of the implementations of reset_phy()
- may need to use miiphy_reset() which is not allowed before eth_initialize()
- as eth_initialize registers all required miiphy_* routines.
- Tested on IP860 and PHY initializes properly after this change.
-
-* Correct includes for flat tree builder.
-
-* Fix conflicting types (flash_write()) in trab auto_update.c.
-
-* Add PCI support for the TQM834x board.
-
-* Add missing 4xx board to MAKEALL
- Patch by Stefan Roese, 20 Oct 2005
-
-* Fix conflicting types (flash_write()) in esd auto_update.c
- Patch by Stefan Roese, 20 Oct 2005
-
-* Fix problem with sleep in NetConsole (use get_timer())
- Patch by Stefan Roese, 20 Oct 2005
-
-* Add NetConsole Support for AMCC eval boards
- Patch by Stefan Roese, 20 Oct 2005
-
-* Fix NetConsole support on 4xx (only print eth link on 1st transfer)
- Patch by Stefan Roese, 18 Oct 2005
-
-* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo.
- Fix identation on ext2ls help entry.
- Patch by Stefan Roese, 14 Oct 2005
-
-* Add support for TQM834x boards.
- Cleanup.
-
-* Cleanup for GCC-4.x
-
-* Add documentation for Open Firmware Flat Tree and usage.
- Patch by Pantelis Antoniou, 13 Oct 2005
-
-* Add missing files for Pantelis Antoniou's patch
- Patch by Pantelis Antoniou, 04 Sep 2005
-
-* Fix problem in ppc4xx eth-driver without ethaddr (only without
- CONFIG_NET_MULTI set)
- Patch by Stefan Roese, 10 Oct 2005
-
-* Fix gzip bmp support (test if malloc fails, warning when truncated).
- Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board.
- Patch by Stefan Roese, 07 Oct 2005
-
-* Add support for OF flat tree for the STXtc board.
- Patch by Pantelis Antoniou, 04 Sep 2005
-
-* Support passing of OF flat trees to the kernel.
- Patch by Pantelis Antoniou, 04 Sep 2005
-
-* Cleanup
-
-* Add support for NetSilicon NS7520 processor.
- Patch by Art Shipkowski, 12 May 2005
-
-* Add support for AP1000 board.
- Patch by James MacAulay, 07 Oct 2005
-
-* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200
- Patch by Anders Larsen, 07 Oct 2005
-
- The Atmel errata #11 states that the transfer buffer descriptor
- table must be aligned on a 16-word boundary. As it turned out, this
- is insufficient - it seems the table must be aligned on a boundary
- at least as large as the table itself (in Linux this is not an
- issue - the table is aligned on a PAGE_SIZE (4096) boundary).
-
-* Fixed compilation for ARM when using a (standard) hard-FP toolchain
- Patch by Anders Larsen, 07 Oct 2005
-
-* Cleanup warnings for cpu/arm720t & cpu/arm1136 files.
- sed the linker scripts, rather than pre-process them.
- Patch by Peter Pearse, 07 Oct 2005
-
-* Update make target for ARM supported boards.
- Use lowlevel_init() instead of platformsetup() [rename].
- Patch by Peter Pearse, 06 Oct 2005
-
-* Fix booting from serial dataflash on AT91RM9200
- Patch by Peter Menzebach, 29 Aug 2005
-
-* Add JFFS2 support for TRAB board
- Patch by Martin Krause, 25 Aug 2005
-
-* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI
- Patch by Marcus Hall, 24 Aug 2005
-
-* Fix the machine-id of the Cogent csb637 board
- Patch by Anders Larsen, 05 Oct 2005
-
-* Complete support for the KwikByte KB920x boards
- Patch by Anders Larsen, 05 Oct 2005
-
-* Set the AT91RM9200 clock to asynchronous mode
- Patch by Anders Larsen, 03 May 2005
-
-* Set the AT91RM9200 clock to synchronous mode
- Patch by Anders Larsen, 29 Apr 2005
-
-* Add support for Cogent csb637
- Patch by Anders Larsen, 29 Apr 2005
-
-* Fix dm9161.c initialization
- Patch by Anders Larsen, 29 Apr 2005
-
-* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005
- (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5)
-
-* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200
- Patch by Anders Larsen, 29 Apr 2005
-
-* Fix device partition intialization for SystemACE disks.
- Patch by Stephen Williams, 28 Apr 2005
-
-* Added support for KwikByte KB920x boards (based on AT91RM9200)
- Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
-
-* Add support for S29GL064M-R3 flash chip on xsengine board
- Patch by Kurt Stremerch, 18 Apr 2005
-
-* E500 update: repoint IVPR to RAM when code is relocated
- Patch by Kylo Ginsberg, 13 Apr 2005
-
-* Fix loop end test in lib_generic/string.c:strswab()
- Patch by Andrew Dyer, October 10, 2005
- Signed-off-by: Andrew Dyer <amdyer@gmail.com>
-
-* Cleanup
-
-* Update ARM Integrator boards:
- Correct addessing errors in platform files.
- Split off common core module data from Integrator header files to
- include/armcoremodule.h.
- Patch by Peter Pearse, 04 Oct 2005
-
-* Make sure only supported compiler options are used
- Import "cc-option" shell function from kernel and
- use it to get the correct ARM GCC options for individual CPUs
- Patch by Peter Pearse, 30 Jun 2005
-
-* Fix 440GR to print correct cpu revision
- Patch by Stefan Roese, 04 Oct 2005
-
-* Change board message on AMCC Yosemite & Yellowstone to common style
- Patch by Stefan Roese, 03 Oct 2005
-
-* Fix compiler warning
-
-* Fix FEC PHY addresses for TQM85xx boards
-
-* Fix uninitialized variable problem in hush shell
- Patch by Lars Rostock, 26 Sep 2005
-
-* Undo change of f6e20fc6ca... to include/configs/trab.h
- (Must have been an accident?)
-
-* Add support for AT91RM9200 OHCI Controller.
- Patch by Eric Benard, 07 Apr 2005
-
-* Update ARM mach-types.h
- Patch by Eric Benard, 07 Apr 2005
-
-* Add support for MP2USB board.
- Patch by Eric Benard, 07 Apr 2005
-
-* Add board support for armadillo HT1070
- Patch by Rowel Atienza, 06 Apr 2005
-
-* Second Ethernet address enabled for MPC885ADS and MPC8272ADS.
- Patch by Vitaly Bordug, 30 Mar 2005
-
-* Add iopset command on mpc8xx
- Patch by Daniel Eisenhut, 25 Mar 2005
-
-* Add support for MII in eepro100 driver.
- Patch by Gleb Natapov, 21 Mar 2005
-
-* Fixes to the Lubbock (PXA 25x) support:
- - Resolve the FIXME with respect to saving the u-boot environment.
- - Make the default load address land in real memory.
- - Fix lan91c96 SMC_{in,out}{b,w,l}() macros
- Patch by David Brownell, 10 Mar 2005
-
-* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board
- Patch by Marc Leeman, 04 Mar 2005
-
-* OMAP242x H4 board update
- - fix for ES2 differences.
- - switch to using the cfi_flash driver.
- - fix SRAM build address.
- - fix for GP device operation.
- - unlock SRAM for GP devices.
- - display more device information.
- - fix potential deadlock in omap24xx_i2c driver.
- - fix DLL load values to match dpllout*1 operation.
- - fix 2nd chip select init for combo DDR device.
- - add support for CFI Intel 28F256L18 on H4 board.
- Patch by Richard Woodruff, 03 Mar 2005
-
-* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h
- Patch by Steven Scholz, 02 Mar 2005
-
-* Fix typo in eth.c
- Patch by Ara Avanesyan, 24 Feb 2005
-
-* Remove unneeded #include <malloc.h>
- Patch by Ladislav Michl, 22 Feb 2005
-
-* Add cramfs support for m68k
- Patch by Zachary Landau, 21 Feb 2005
-
-* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs
- Patch by Jeff Angielski, 21 Feb 2005
-
-* Fix au1x00_serial baud rate calculation:
- remove hardcoded cpu clock divisor and use register instead;
- round up instead of truncate
- Patch by Andrew Dyer, 15 Feb 2005
-
-* Add Xilinx Spartan3 family FPGA support
- Patch by Kurt Stremerch, 14 Feb 2005
-
-* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET
- Patch by Zachary Landau, 11 Feb 2005
-
-* Fix VOH405 Support
- Patch by Matthias Fuchs, 25 Sep 2005
-
-* Added support for PCI bridge on MPC8272ADS
- Patch by Vitaly Bordug, Feb 09 2005
-
-* Update multicore CM9XX support for Integrator AP to allow booting from flash
- Patch by Jean-Paul Saman, 8 Feb 2005
-
-* Fix strswab() to reliably find end of string
- Patch by Andrew Dyer, 08 Feb 2005
-
-* Fix typos in include/ppc440.h
- Patch by Andrew E Mileski, 04 Feb 2005
-
-* Add Vibren (was Accelent) PXA255 IDP Support
- Patch by Cliff Brake, 04 Feb 2005
-
-* Fix tools/bmp_logo.c using incorrect offset to pixel data
- Patch by Andrew Dyer, 31 Jan 2005
-
-* Add ARM946E cpu and core module targets; remap memory to 0x00000000
- Patch by Peter Pearse, 2 Feb 2005
-
-* Fix error handling in tools/env/fw_env.c
- Patch by Ara Avanesyan, 01 Feb 2005
-
-* Fix MGT5100 PSC baudrate calculation
- Patch by Sebastian Schau, 27 Jan 2005
-
-* OMAP242x fix for GP device booting
- - Add SRAM unlock for GP devices.
- - Change DDR DLL unlock value to allow DPLLout*1 operation.
- Patches by Richard Woodruff, 21 Jan 2005:
-
-* Add support for AMD's Pb1x00 eval board;
- add MII routines to the au1x00 ethernet driver;
- add USB ohci driver (work in progress)
- Patch by Thomas Sailer, 20 Jan 2005
-
-* Update omap5912osk board
- Use drivers/cfi_flash.c instead of private flash driver;
- Remove hardcoded personalized settings from omap5912osk.h;
- Fix spacing with (RO) marks in 'flinfo' output.
- Patch by Michael Bendzick, 14 Jan 2005
-
-* Fix warnings for PCI code on ixp
- Patch by Joe <lgxue@yahoo.com>, 13 Jan 2005
-
-* virtex2 fix for bogus download error messages
- The virtex2 FPGA download code watches for init going active during
- a download of config data as an error condition. init also goes
- active after a configuration is finished in concert with the done
- signal. So far, the code does not check for done active until all
- of the configuration data is sent. If configuration data has a few
- extra pad bytes at the end, this would cause an error message even
- though the download had suceeded.
- NOTE: virtex2 slave serial and spartan2 versions may still have the
- same problem.
- Patch by Andrew Dyer, 12 Jan 2005
-
-* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian
- Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode"
- message when probing for nonexistent flash in little endian mode.
- As a side effect more efficient and smaller code is generated,
- which is always a Good Thing (TM).
- Patch by Ladislav Michl, 24 Sep 2005
-
-* Update for TFTP using a fixed UDP port
- Use the approved environment variable names. Added "tftpdstp" to
- allow ports other than 69 per Tolunay Orkun's recommendation.
- Patch by Jerry Van Baren, 12 Jan 2005
-
-* Allow to force TFTP to use a fixed UDP port
- (Add a configuration option CONFIG_TFTP_PORT and optional env
- variable tftpport)
- Patch by Jerry Van Baren, 10 Jan 2005
-
-* Fix ethernet timeouts on dbau1550 and other au1x00 systems
- Patch by Leif Lindholm, 29 Dec 2004
-
-* Cleanup: fix broken builds
-
-* Fix PHY address argument passing with mii info command
- Patch by Andrew Dyer, 28 Dec 2004
-
-* Cleanup (PPC4xx is AMCC now)
-
-* esd CPCI2DP board added
- Patch by Matthias Fuchs, 22 Sep 2005
-
-* esd PMC405 board updated
- Patch by Matthias Fuchs, 22 Sep 2005
-
-* Add SM501 support to HH405 board.
- Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP).
- Add support for eeprom write-enable (CFG_EEPROM_WREN).
- Patch by Stefan Roese, 22 Sep 2005
-
-* Fix autonegotiation in tsec ethernet driver
- Patch by Stefan Roese, 21 Sep 2005
-
-* Fix bug in auto_update (trab board)
- Patch by Martin Krause, 16 Sep 2005
-
-* Fix computation of framebuffer palette for 8bpp LCD bitmaps
- Patch by Francesco Mandracci, 16 Sep 2005
-
-* Update configuration for INKA4x0 board
-
-* Update configuration for PM854 board
- Based on patch by R. Loeffl, 20 Jul 2005
-
-* Add PCI support to TQM8540 and TQM8560 boards
- Patch by Stefan Roese, 15 Sep 2005
-
-* Update AMCC Yosemite to get a consistent setup for all AMCC eval
- boards (baudrate, environment...). Flash driver fixed.
- Patch by Stefan Roese, 15 Sep 2005
-
-* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd
- ethernet port on ebony.
- Patch by Stefan Roese, 7 Sep 2005
-
-* Added support for mtddevnum and mtddevname variables (mtdparts command)
-
-* Change default console baud rate for stxxtc board
-
-* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
- Patch by Stefan Roese, 31 Aug 2005
-
-* Fix default command set (don't include CFG_CMD_DISPLAY command)
- Patch by Pantelis Antoniou, 02 Sep 2005
-
-* Cleanup
-
-* Enable SM712 driver support for HMI1001 board.
-
-* Fix problems with ld version 2.16 (dot outside sections problem)
- Pointed out by Gerhard Jaeger, 31 Aug 2005;
- cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
-
-* Prepare U-Boot for gcc-4.x: fix global data pointer initialization
-
-* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux
-
-* Add keyboard and dot matrix display support for HMI1001 board.
-
-* Prepare U-Boot for gcc-4.x
-
-* Fixed Bamboo port to enable running without DDR-DIMM
- (Bamboo has also 64MB onboard DDR)
- Patch by Stefan Roese, 24 Aug 2005
-
-* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
- now handling all 4xx cpu's
- Patch by Stefan Roese, 16 Aug 2005
-
-* Fix make dependencies for at91rm9200 and ks8695 cpus
- Patch by Steven Scholz, 23 Aug 2005
-
-* Add JFFS2 support for TQM5200 board
-
-* Add esd cpci5200 and pf5200 boards
- Patch by Reinhard Arlt, 22 Aug 2005
-
-* Fix sysclock for TQM8540 and TQM8560 boards
- Patch by Martin Krause, 25 Jul 2005
-
-* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2
- Patch by Martin Krause, 08 Jun 2005
-
-* Add new board specific commands for TQM5200/STK52XX
- - Sound commands (beep, wav, sound)
- - Test commands (led, can, backlight, rs232)
- Patch by Martin Krause, 02 May 2005
-
-* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
- because of a bug in the AT91RM9200 CPU PLL
- Patch by Martin Krause, 22 Apr 2005
-
-* Add automatic HW detection for another CMC_PU2 variant
- Patch by Martin Krause, 20 Apr 2005
-
-* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration
- Patch by Martin Krause, 19 Apr 2005
-
-* Fix initialization problem on TQM5200 without SM501
- Patch by Martin Krause, 08 Apr 2005
-
-* Add RTC support for STK52XX.200
- Patch by Martin Krause, 07 Apr 2005
-
-* Add support for IFM o2dnt board
-
-* Enable PCI on hmi1001 board
-
-* Fix return values of the jffs2 commands ls/fsload/fsinfo,
- so we can use them to, e.g., check the existence of a file with
- "if ls foo; then this; else that; fi" in the hush shell
- Patch by Andreas Engel, 16 August 2005
-
-* Coding style cleanup
-
-* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
- Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
-
-* Check return value of malloc in 440gx_enet.c
- Patch by Travis B. Sawyer, 18 Jul 2005
-
-* Add Sandburst Metrobox and Sandburst Karef board support packages.
- Second serial port on 440GX now defined as a system device.
- Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
- Patch by Travis B. Sawyer, 12 Jul 2005
-
-======================================================================
-Changes for U-Boot 1.1.3:
-======================================================================
-
-* Minor code cleanup
-
-* Add forgotten new fils from latest VoiceBlue update
-
-* Make bootretry feature work with hush shell.
- Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too.
- Patch by Andreas Engel, 19 Jul 2005
-
-* Update Hymod Board Database PHP code in "tools" directory
- Patch by Murray Jensen, 01 Jul 2005
-
-* Make "tr" command use POSIX compliant; export HOSTOS make variable
- Patch by Murray Jensen, 30 Jun 2005
-
-* Fix Murray Jensen's mail address.
- Patch by Murray Jensen, 30 Jun 2005
-
-* Preserve PHY_BMCR during a soft reset.
- Patch by Carl Riechers, 24 Jun 2005
-
-* VoiceBlue update: eeprom tool can also store firmware version now.
- eeprom.bin is runable by jumping at load address.
- Patch by Ladislav Michl, 23 May 2005
-
-* Move the AT91RM9200DK to the ARM Systems list.
- Patch by Anders Larsen, 26 Apr 2005
-
-* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3
- Patch by Anders Larsen, 26 Apr 2005
-
-* measure_gclk() is needed when DEBUG is enabled
- Patch by Bryan O'Donoghue, 25 Apr 2005
-
-* Add UPD-Checksum code, fix problem in net.c (return instead of break)
- Patch by Reinhard Arlt, 12 Aug 2005
-
-* esd PCI405 board updated
- Patch by Matthias Fuchs, 28 Jul 2005
-
-* esd WUH405 and DU405 board updated
- Patch by Matthias Fuchs, 27 Jul 2005
-
-* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I)
- Patch by Matthias Fuchs, 4 May 2005
-
-* Update AMCC Yosemite to get a consistent setup for all AMCC eval
- boards (baudrate, environment...). Flash driver fixed.
- Patch by Stefan Roese, 11 Aug 2005
-
-* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port
- Patch by Stefan Roese, 11 Aug 2005
-
-* Add NAND FLASH support for AMCC Bamboo 440EP eval board
- Patch by Stefan Roese, 11 Aug 2005
-
-* Add configuration for IFM AEV FIFO board.
- Minor coding style cleanup.
-
-* Add configuration for IFM SPI eval board
-
-* Fix CompactFlash problem on HMI1001 board
-
-* Make new "mtdparts" code build with older compilers
- Patch by Andrea Scian, 09 Aug 2005
-
-* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to
- CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design
- with the 405 defines and the linux kernel defines.
- Patch by Stefan Roese, 08 Aug 2005
-
-* Fix compiler warnings with older GCC versions
-
-* Add common (with Linux) MTD partition scheme and "mtdparts" command
-
- Old, obsolete and duplicated code was cleaned up and replace by the
- new partitioning method. There are two possible approaches now:
-
- The first one is to define a single, static partition:
-
- #undef CONFIG_JFFS2_CMDLINE
- #define CONFIG_JFFS2_DEV "nor0"
- #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */
- #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */
- #define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
- The second method uses the mtdparts command line option and dynamic
- partitioning:
-
- /* mtdparts command line support */
- #define CONFIG_JFFS2_CMDLINE
- #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
- #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
-
- Command line of course produces bigger images, and may be inappropriate
- for some targets, so by default it's off.
-
-* Fix build problems for PM856 Board
-
-* Fix sign extension bug in 'fpga loadb' command;
- make 'fpga loadb' always print the file header info
- Patch by Andrew Dyer, 11 Jan 2005
-
-* Fix errors that occur when accessing SystemACE CF
- Patch by Jeff Angielski, 09 Jan 2005
-
-* Document switching between U-Boot and PlanetCore on RPXlite
- by Sam Song, 24 Dec 2004
-
-* Fix PowerQUICC II mask detection.
- Patch by Eugene Surovegin, 20 Dec 2004
-
-* Add support for Altera NIOS DK1C20 board
- Patch by Shlomo Kut, 13 Dec 2004
-
-* Add support for ep8248 board
- Patch by Yuli Barcohen, 12 Dec 2004
-
- Minor code cleanup.
-
-* Fix baudrate setting for KGDB on MPC8260
- Patch by HoJin, 11 Dec 2004
-
-* Fix 'mii help' text formatting
- Patch by Cory Tusar, 10 Dec 2004
-
-* Fix return code of NFS command
- Patch by Hiroshi Ito, 11 Dec 2004
-
-* Fix typo
-
-* Fix compiler warnings in cpu/ppc4xx/usbdev.c
- Patch by Steven Blakeslee, 04 Aug 2005
-
-* Add support for AMCC Bamboo PPC440EP eval board
- Patch by Stefan Roese, 04 Aug 2005
-
-* Patch by Jon Loeliger
- Fix style issues primarily in 85xx and 83xx boards.
- - C++ comments
- - Trailing white space
- - Indentation not by TAB
- - Excessive amount of empty lines
- - Trailing empty lines
-
-* Patch by Ron Alder, 11 Jul 2005
- Add Xianghua Xiao and Lunsheng Wang's support for the
- GDA MPC8540 EVAL board.
-
-* Patch by Eran Liberty
- Add support for the Freescale MPC8349ADS board.
-
-* Patch by Jon Loeliger, 25 Jul 2005
- Move the TSEC driver out of cpu/mpc85xx as it will be shared
- by the upcoming mpc83xx family as well.
-
-* Patch by Jon Loeliger, 05 May 2005
- Implemented support for MPC8548CDS board.
- Added DDR II support based on SPD values for MPC85xx boards.
- This roll-up patch also includes bugfies for the previously
- published patches:
- DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
-
-* Patch by Jon Loeliger, 10 Feb 2005
- Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
-
-* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
- For MPC85xxCDS:
- Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
- for faster flash parts.
- Add documentation for BR/OR for FLASH.
-
-* Patch by Jon Loeliger 08 Feb 2005
- Determine L2 Cache size dynamically on 85XX boards.
-
-* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
- - Convert the CPM2 based functionality to use new CONFIG_CPM2
- option rather than a myriad of CONFIG_MPC8560-like variants.
- Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
- Eliminates the CONFIG_MPC8560 option entirely. Distributes the
- new CONFIG_CPM2 option to each 8260 board.
-
-* Add support for MicroSys PM856 board
- Patch by Josef Wagner, 03 Aug 2005
-
-* Minor fixes to PM854 board
- Patch by Josef Wagner, 03 Aug 2005
-
-* Adjust configuration of XENIAX board
- (chip select and GPIO required for USB operation)
-
-* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
- routed to the Watchdog handler
- Patch by Eugene Surovegin, 18 Jun 2005
-
-* (re)enabled scsi commands do_scsi() and do_scsiboot()
- Patch by Denis Peter, 06 Dec 2004
-
-* Fix endianess problem in TFTP / NFS default filenames
- Patch by Hiroshi Ito, 06 Dec 2004
-
-* Ignore broadcast status bit in received frames in 8260 FCC ethernet
- loopback test code
- Patch by Murray Jensen, 18 Jul 2005
-
-* Fix typo in mkconfig script (used == instead of =)
- Patch by Murray Jensen, 18 Jul 2005
-
-* Cleanup build problems on 64 bit build hosts
-
-* Update MAINTAINERS file
-
-* Patch by Stefan Roese, 01 Aug 2005:
- - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
- (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
- for details.
- - Sycamore (PPC405GPr) eval board added (Walnut port is extended
- to run on both 405GP and 405GPr eval boards).
-
-* Patch by Steven Blakeslee, 27 Jul 2005:
- - Add support for AMCC PPC440EP/GR.
- - Add support for AMCC Yosemite PPC440EP eval board.
- - Add support for AMCC Yellowstone PPC440GR eval board.
-
-* Minor fixes for PPChameleon Board:
- - fix alignment of NAND size
- - make code do what the comment says
-
-* Implement h/w sector protection status synchronization at boot.
- The code is provided for, and was tested on, the Yukon/Alaska
- and PM520 boards only.
-
- A bug in flash_real_protect() for the Yukon board was fixed by
- adding a function that tells if two banks are on one flash chip.
-
-* Fix sysmon POST problem: check I2C error codes
- This fixes a problem of displaying bogus voltages when the voltages
- are so low that the I2C devices start failing while the rest of the
- system keeps running.
-
-* Patch by Cedric Vincent, 6 Jul 2005:
- Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c"
-
-* Patch by Jon Loeliger, 20 Jul 2005:
- Add missing PCI IO port definitions.
-
-* Add CompactFlash support for HMI1001 board.
-
-* Adjust printed board ID for LWMON board.
-
-* Fix low-level OHCI transfers for ARM920t and MPC5xxx
-
-* Add new argument format for flash commands to allow for usage like
- "erase $(addr) +$(filesize)", i. e. a size argument can be used and
- U-Boot will automaticially find the end of the corresponding sector.
-
-* Patch by Stefan Roese, 5 Jul 2005:
- Update uc100 board PHY setup
-
-* Patch by Stefan Roese, 1 Jul 2005:
- Fix PHY address for CATcenter board (now correct!)
-
-* Patch by Stefan Roese, 30 Jun 2005:
- Fix PHY addresses for PPChameleon and CATcenter boards
- Change MAINTAINER for most esd boards
-
-* Patch by Detlev Zundel, 30 Jun 2005:
- Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
-
-* Fix baudrate calculation problem on MPC5200 systems
-
-* Add EEPROM and RTC support for HMI1001 board
-
-* Patch by Detlev Zundel, 20 Jun 2005:
- Fix initialization of low active GPIO pins on inka4x0 board
-
-* Enable redundant environment, disable HW flash protection of
- HMI1001 board
-
-* Patch by Travis Sawyer, 10 Jun 2005:
- Initialize allocated dev and private hw structures
- after their respective allocation in 440gx_enet.c
-
-* Patch by Steven Scholz, 10 Jun 2005:
- Fix byteorder problems with second argument of "bootm" with
- standalone images;
-
-* Add support for HMI1001 board
-
-* Disable "date" and "sntp" commands on TQM866M
-
-* Fix watchdog reset problems on LWMON board
-
-* Patch by Juergen Selent, 17 May 2005:
- Add support for Funkwerk VoVPN gateway module.
-
-* Cleanup debug code for MPC8220 FEC driver
-
-* Extend burst mode RAM test program to take a loop count
- (0 = infinite)
-
-* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
- those boards that use it.
-
-* Patches by Greg Ungerer, 19 May 2005:
- - add support for the KS8695P (ARM 922 based) CPU
- - add support for the OpenGear CM4008, CM4116 and CM4148 boards
-
-* Patch by Steven Scholz, 19 May 2005:
- Add support for CONFIG_SERIAL_TAG on ARM boards
-
-* Add PCI support for Sorcery board.
- Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
-
-* Fix compile problems caused by new burst mode SDRAM test;
- make port pins to trigger logic analyzer configurable
-
-* Fix timer handling on MPC85xx systems
-
-* Fix debug code in omap5912osk flash driver
-
-* Add support for MPC8247 based "IDS8247" board.
-
-* Add support for 2 x TSEC interfaces on the TQM8540 board.
-
-* On LWMON we must use the watchdog to reset the board as the CPU
- genereated HRESET pulse is too short to reset the external
- circuitry.
-
-* Add test tool to exercise SDRAM accesses in burst mode
- (as standalone program, MPC8xx/PowerPC only)
-
-* Increase CFG_MONITOR_LEN for Rattler board to match actual code
- size.
-
-* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
- March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
- added to support LZO and LZARI compression modes (undefined by
- default).
-
-* Fix problem with symbolic links in JFFS2 code.
-
-* Use linker ASSERT statement to prevent undetected overlapping of
- sections on PPChameleon board; other boards might use this, too.
-
-* Patch by Stefan Roese, 03 May 2005:
- Update for P3G4
- Fix problems in cmd_universe.c
-
-* Patch by Matthias Fuchs, 03 May 2005:
- Added missing variable declaration in cmd_nand.c
- Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
-
-* Fix INKA4x0: use CS1 as gpio_wkup_6 output
-
-* Fix bug in the SDRAM initialization code for canmb, IceCube and
- PM520 boards.
- Fix PHY address for canmb board.
-
-* Cleanup serial console baudrate calculation on AT91RM9200;
- get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
-
-* Patch by Matthias Fuchs, 18 Apr 2005:
- Make PCI target address spaces on PMC405 and CPCI405 boards
- configurable via environment variables
-
-* Auto-size RAM on canmb board.
-
-* Add support for canmb board
-
-* Patch by Stefan Roese, 13 Apr 2005:
- Update for esd apc405
-
-* Fixes for TQM8560 board:
- - fix clock rates
- - remove debug messages
- - fix flash sector protection
-
-* Patch by Steven Scholz, 07 Apr 2005:
- Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
-
-* Patches by Steven Scholz, 07 Apr 2005:
- Fix compiler warning in altera.c
- Fix warning in cpu/arm920t/at91rm9200/i2c.c
-
-* Patch by Ladislav Michl, 06 Apr 2005:
- Fix voiceblue configuration.
-
-* Patch by Stefan Roese, 06 Apr 2005:
- Updates for OCOTEA board:
- - Changed U-Boot size from 512kByte to 256kByte
- - Fixed flash driver to support boot from soldered user flash
- - Added README for switch from PIBS firmware to U-Boot
-
-* Patch by Travis Sawyer, 05 Apr 2005:
- - Change timer frequency for ppc 440 from 10 ms to 1 ms.
- Problem found by Andrew Wozniak.
-
-* Patch by Steven Scholz, 06 Apr 2005:
- - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
- - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
-
-* Patches by Robert Whaley, 29 Nov 2004:
- - update the pxa-regs.h file for PXA27x chips
- - add PXA27x based ADSVIX board
- - add support for MMC on PXA27x processors
-
-* Patch by Andrew E. Mileski, 28 Nov 2004:
- Fix PPC4xx SPD SDRAM detection bug
-
-* Patch by Hiroshi Ito, 26 Nov 2004:
- Fix logic of "test -z" and "test -n" commands
-
-* Patch by Ladislav Michl, 05 Apr 2005:
- Add support for VoiceBlue board.
-
-* Patch by Ladislav Michl, 05 Apr 2005:
- Fix netboot_common() prototypes.
-
-* Patch by Steven Scholz, 05 Apr 2005:
- Use i.MX watchdog timer for reset_cpu()
-
-* Patch by Steven Scholz, 05 Apr 2005:
- Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
- subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
- (now in interupts.c)
-
-* Add support for MPC8220 based "sorcery" board.
-
-* Add support for TQM8560 board.
-
-* Add FEC support for TQM8540 board.
- Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
-
-* Patch by Martin Krause, 04 Apr 2005:
- Update default configuration for CMC_PU2 board.
-
-* Patch by Steven Scholz, 04 Apr 2005:
- - remove all references to CONFIG_INIT_CRITICAL for ARM based boards
- - introduce two new configuration options instead:
- CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
-
-* Patch by Steven Scholz, 04 Apr 2005:
- Make sure that MDIO clock does not exceed 2.5 MHz on AT91
-
-* Fix timer code for ARM systems: make sure that udelay() does not
- reset timers so it's save to use udelay() in timeout code.
-
-* Patch by Mathias Küster, 23 Nov 2004:
- add udelay support for the mcf5282 cpu
-
-* Patch by Tolunay Orkun, 16 November 2004:
- fix incorrect onboard Xilinx CPLD base address
-
-* Patch by Jerry Van Baren, 08 Nov 2004:
- - Add low-boot option for MPC8260ADS board (if lowboot is selected,
- the jumper for the HRCW source should select flash. If lowboot is
- not selected, the jumper for the HRCW source should select the
- BCSR.
- - change default load base address to 0x00400000
-
-* Patch by Yuli Barcohen, 08 Nov 2004:
- Add support for Analogue & Micro Rattler boards.
- Tested on Rattler8248.
-
-* Patch by Andre Renaud, 08 Nov 2004:
- Fix watchdog support in common/lcd.c
-
-* Patch by Marc Leeman, 05 Nov 2003:
- Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
- bug only affects the XPC8245 processors
-
-* Patches by Josef Wagner, 29 Oct 2004:
- - Add support for MicroSys CPU87 board
- - Add support for MicroSys PM854 board
-
-* Patch by Jian Zhang, 02 Nov 2004:
- Add 16-bit NAND support
-
-* Patch by Scott McNutt, 01 Nov 2004:
- Add missing NIOS/NIOS2 support for "iminfo" command
-
-* Patch by Detlev Zundel, 29 Oct 2004:
- Add missing NIOS/NIOS2 support for "mkimage" tool.
-
-* Patch by David Adair, 27 Oct 2004:
- Add missing 440GX SDRAM Controller reset
-
-* Patch by Steven Scholz, 25 Oct 2004:
- Declare reset_cpu() in include/common.h instead locally
-
-* Patch by Yusdi Santoso, 22 Oct 2004:
- - Add support for HIDDEN_DRAGON board
- - fix endianess problem in driver/rtl1839.c
-
-* Patch by Allen Curtis, 21 Oct 2004:
- support multiple serial ports
-
-* Patch by Richard Klingler, 03 Apr 2005:
- Add call to eth_halt() in net/net.c when called functions fail
- after eth_init() has been called.
-
-* Patch by Sam Song, 3 April 2005:
- - Update README.Netconsole
- - Update README
-
-* Prepare for SoC rework of ARM code:
- - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL
- - rename memsetup into lowlevel_init (function name and source files)
- Patch by Steven Scholz, 03 Apr 2005:
- - create SoC specific directories include/asm-arm/arch-imx and
- include/asm-arm/arch-s3c24x0
-
-* Fix problems with SNTP support;
- enable SNTP support in some boards.
-
-* Patches by Martin Krause, 01 Apr 2005:
- - Fix flash erase timeout on CMC_PU2
- - Add automatic HW detection for CMC_PU2 and CMC_BASIC
-
-* Patch by Steven Scholz, 13 March 2005:
- fix cache enabling for AT91RM9200
-
-* Patch by Masami Komiya, 30 Mar 2005:
- add SNTP support and expand time server and time offset fields of
- DHCP support. See doc/README.SNTP
-
-* Patch by Steven Scholz, 13 Dec 2004:
- Fix bug in at91rm920 ethernet driver
-
-* Patch by Steven Scholz, 13 Dec 2004:
- Remove duplicated code by merging memsetup.S files for
- at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
-
-* Patch by Detlev Zundel, 31 Mar 2005:
- Cleanup duplicate definition of overwrite_console()
-
-* Update TQM5200 configuration;
- prepare for Rev. 200 starter kit boards
-
-* Patch by Scott McNutt, 21 Oct 2004:
- Add support for Nios-II EPCS Controller core.
-
-* Patch by Scott McNutt, 20 Oct 2004:
- Nios-II cleanups:
- - Add sysid command (Nios-II only).
- - Locate default exception trampoline at proper offset.
- - Implement I/O routines (readb, writeb, etc)
- - Implement do_bootm_linux
-
-* Patches by Martin Krause, 22 Mar 2005:
- - use TQM5200_auto as MAKEALL target for TQM5200 systems
- - add support for SM501 graphics controller
- - add support for graphic console on TQM5200
- - add support for TQM5200 Rev 200
- - cleanup, fix typo in include/configs/TQM5200.h
-
-* Patch by Manfred Baral, 17 Mar 2005:
- Fix typo
-
-* Fix RTC configuration for PPChameleon board
-
-* Cleanup, fix typo in include/configs/TQM5200.h
-
-* Patch by Stefan Roese, 16 Mar 2005:
- Update for esd auto_update and hh405 board
-
-* Adapt for U-Boot image size (new features enabled) on TQM5200
-
-* Update code for TQM8540 board (and 85xx in general):
- - Change the name of the Ethernet driver: MOTO ENET -> ENET
- - Reformat boot messages
- - Enable redundant environment
- - Replace the -O2 optimization flag with -mno-string
-
-* Patch by David Brownell, 10 Mar 2005:
- Restore copyright statements in OHCI drivers.
-
-* Add support for TQM8540 board
-
-* Patch by Detlev Zundel, 14 Mar 2005:
- NC650: changed NAND flash addressing to using UPMB
-
-* Patch by Stefan Roese, 14 Mar 2005:
- Update for esd voh405 fpga image
-
-* INKA4x0: Allow initialization of LCD backlight dimming from
- "brightness" environment variable.
-
-* Add port initialization for digital I/O on INKA4x0
-
-* Patch by Stefan Roese, 01 Mar 2005:
- Update for esd boards dp405 and hub405
-
-* Fix get_partition_info() parameter error in all other calls
- (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c).
-
-* Enable USB and IDE support for INKA4x0 board
-
-* Patch by Andrew Dyer, 28 Feb 2005:
- fix ext2load passing an incorrect pointer to get_partition_info()
- resulting in load failure for devices other than 0
-
-* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board
-
-* Cleanup USB and partition defines
-
-* Add support for ext2 filesystems and image timestamps to TQM5200 board
-
-* Add reset code for Coral-P on INKA4x0 board
-
-* Patch by Martin Krause, 28 Jun 2004:
- Update for TRAB board.
-
-* Fix some missing "volatile"s in MPC5xxx FEC driver
-
-* Fix cirrus voltage detection (for CPC45)
-
-* Fix byteorder problem in usbboot and scsiboot commands.
-
-* Patch by Cajus Hahn, 04 Feb 2005:
- - don't insist on leading '/' for filename in ext2load
- - set default partition to useful value (1) in ext2load
-
-* Patch by Andrew Dyer, 08 Jan 2005:
- fix wrong return codes in ext2 code
-
-* Removed '--no-warn-mismatch' option from Makefile. This option
- makes 'ld' to overlook binary objects compatibility.
-
-* Moved $(PLATFORM_LIBS) from the library group (--start-group ...
- --end-group) outside of the group. This will make 'ld' to do
- _multiple_ search in the library group when resolving symbol
- references and do only a _single_ seach in libgcc.a after the group
- search.
-
-* Fix stability problems on CPC45 board again.
-
-* Make image detection for diskboot / usbboot / scsiboot more robust
- (also check header checksum)
-
-* Update CPC45 board configuration.
-
-* Add USB and PCI support for INKA4x0 board
-
-* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO).
-
-* Code cleanup
-
-* Patch by Robin Getz, 13 Oct 2004:
- Add standalone application to change SMC91C111 MAC addresses,
- see examples/README.smc91111_eeprom
-
-* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
- Fix Flash support for ARM Integrator CP.
-
-* Patch by Richard Woodruff, 10 Jan 2005:
- Update support for OMAP2420 (ARM11) and H4 board:
- o clean up and add new types to H4 memory probe code.
- o fix to work with internal boot.
- o added PRCM config III operation.
- o fix marginal flash timings.
- o add revison ATAG usage.
- o enable voltage scaling at power chip.
- o fix compile error for i2c.
-
-* Fix network problem (error when receiving multiple ARP packets)
-
-* Patch by Daniel Poirot, 12 Oct 2004:
- Add support for Wind River sbc405 board
-
-* Patch by Rainer Brestan, 12 Oct 2004:
- Make examples/Makefile more robust
-
-* Patch by Sam Song, 11 October 2004:
- - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board
- - Adjust CPU:BUS frequency ratio 1:1 when core frequency
- less than 50MHz
-
-* Patch by Sam Song, 10 Oct 2004:
- Fix a parameter error in run_command() in main.c
-
-* Patch by Richard Woodruff, 01 Oct 2004:
- add support for the TI OMAP2420 processor and its H4 reference
- board
-
-* Patch by Christian Pellegrin, 24 Sep 2004:
- Added support for NE2000 compatible (DP8390, DP83902) NICs.
-
-* Patch by Leif Lindholm, 23 Sep 2004:
- add support for the AMD db1550 board
-
-* Patch by Travis Sawyer, 15 Sep 2004:
- Add CONFIG_SERIAL_MULTI support for ppc4xx,
- update README.serial_multi
-
-* Patches by David Snowdon, 07 Sep 2004:
- - add u-boot.hex target in the top level Makefile
- - add support for the UNSW/NICTA PLEB 2 board (pleb2)
- - use -mtune=xscale and -march=armv5 options for PXA
-
-* Patch by Florian Schlote, 08 Sep 2004:
- Add support for SenTec-COBRA5272-board (ColdFire).
-
-* Patch by Gleb Natapov, 07 Sep 2004:
- mpc824x: set PCI latency timer to a sane value
- (is 0 after reset).
-
-* Patch by Kurt Stremerch, 03 Sep 2004:
- Add bitstream configuration option for fpga command (Xilinx only).
-
-* Patch by Kurt Stremerch, 03 Sep 2004:
- Add Xilinx Spartan2E family FPGA support
-
-* Patch by Jeff Angielski, 02 Sep 2004:
- Add Added support for H2 revision of the EP8260 board.
- Fixed formatting for some of the EP8260 related source files.
-
-* Patch by Jon Loeliger, 02 Sep 2004:
- Reset monitor size back to 256 so environment can be written
- to flash on MPC85xx ADS and CDS releases.
-
-* Patch by Paolo Broggini, 02 Sep 2004:
- Make BSS clearing on ARM systems more robust
-
-* Patch by Yue Hu and Joe, 01 Sep 2004:
- - add PCI support for ixp425;
- - add EEPRO100 suppor tfor ixdp425 board.
-
-* Fix problem with protected sector detection in driver/cfi_flash.c
-
-======================================================================
-Changes for U-Boot 1.1.2:
-======================================================================
-
-* Code cleanup, mostly for GCC-3.3.x
-
-* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
- pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
- additional ethernet addresses.
-
-* Cleanup drivers/i82365.c - avoid duplication of code
-
-* Fix bogus "cannot span across banks" flash error message
-
-* Code cleanup
-
-* Add support for CompactFlash for the CPC45 Board.
-
-* Fix problems with CMC_PU2 flash driver.
-
-* Cleanup:
- - avoid trigraph warning in fs/ext2/ext2fs.c
- - rename UC100 -> uc100
-
-* Add support for UC100 board
-
-* Patch by Stefan Roese, 16 Dez 2004:
- - ext2fs support added
- - Tundra universe support added
- - ColdFire MCF5249 support added (no preloader needed!)
- - MCF5249 board TASREG added
- - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405,
- VOM405, WUH405
- - some esd boards updated
- - memory commands "mdc" and "mwc" added for cyclic read/write
- (CONFIG_MX_CYCLIC, see README for further description)
-
-* Add support for INKA4X0 board
-
-* Patch by Steven Scholz, 12 Dec 2004:
- Fix typo in AT91 memory setup.
-
-* Patch by Martin Krause, 27 Oct 2004:
- - add support for "STK52xx" board (including PS/2 multiplexer)
- - add hardware detection for TQM5200
-
-* Clean up CMC PU2 flash driver
-
-* Update MAINTAINERS file
-
-* Fix bug in MPC823 LCD driver
-
-* Fix udelay() on AT91RM9200 for delays < 1 ms.
-
-* Enable long help on CMC PU2 board;
- fix reset issue;
- increase CPU speed from 179 to 207 MHz.
-
-* Fix smc91111 ethernet driver for Xaeniax board (need to handle
- unaligned tail part specially).
-
-* Update for AT91RM9200DK and CMC_PU2 boards:
- - Enable booting directly from flash
- - fix CMC_PU2 flash driver
-
-* Fix mkimage usage message
-
-* Map SRAM on NC650 board
-
-* Work around for Ethernet problems on Xaeniax board
-
-* Patch by TsiChung Liew, 23 Sep 2004:
- - add support for MPC8220 CPU
- - Add support for Alaska and Yukon boards
-
-* Fix configuration for ERIC board (needs more room)
-
-* Adjust MIPS compiler options at run-time depending on tools version
- ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new,
- "-mcpu=4kc" for old tools)
-
-* Add passing of the command line and memory size information to the
- kernel on xaeniax board.
-
-* Enable NAND flash support for NC650 board.
-
-* Patch by Thomas Lange 07 Oct 2004:
- Updated README for DBAu1x00 boards to match current status
-
-* Patch by Philippe Robin, 28 Sept 2004:
- Fix Flash support for Versatile.
-
-* Patch by Roger Blofeld, 16 Sep 2004:
- Fix timeout for DHCP command retry
-
-* Patch by Pantelis Antoniou, 14 Sep 2004:
- Fix early serial hang when CONFIG_SERIAL_MULTI is defined.
-
-* Patch by Pantelis Antoniou, 14 Sep 2004:
- Kick watchdog when bz-decompressing
-
-* Fix CFG_HZ problems on AT91RM9200 systems
- [Remember: CFG_HZ should be 1000 on ALL systems!]
-
-* Patch by Gridish Shlomi, 30 Aug 2004:
- - Add support to revA version of PQ27 and PQ27E.
- - Reverted MPC8260ADS baudrate back to original 115200
-
-* Patch by Hojin, 17 Sep 2004:
- Fix typo in cfi_flash.c
-
-* Patch by Mark Jonas, 09 September 2004:
- mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong
- error message
-
-* Patch by Mark Jonas, 31 August 2004:
- Added option CFG_XLB_PIPELINING to enable XLB pipelining. This
- improves FTP performance for MPC5200 systems. Enabled for IceCube
- by default.
-
-* Patch by Michael Bendzick, 30 Aug 2004:
- - Improve platform.S code for omap1510inn that detects whether code
- is running from SDRAM or not. Patch allows SDRAM to be configured
- if code is running out of SRAM at 0x20000000.
-
-* Patch by Frederick Klatt, 30 Aug 2004:
- Add support for the Wind River SBC8540/SBC8560 boards
-
-* Configure SX1 board to use drivers/cfi_flash.c
-
-* Patches by Michael Bendzick, 30 Aug 2004:
- - Configure omap1510inn board to use drivers/cfi_flash.c
- - Make drivers/cfi_flash.c protect environment and redundant
- environment.
-
-* Patch by Steven Scholz, 23 Jun 2004:
- - Add script (tools/img2brec.sh) to programm U-Boot into
- (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L
-
-* Patches by Scott McNutt, 24 Aug 2004:
- - Add support for Altera Nios-II processors.
- - Add support for Psyent PCI-5441 board.
- - Add support for Psyent PK1C20 board.
-
-* Patches by Jon Loeliger, 24 Aug 2004:
- - Add support for the MPC8541 and MPC8555 CDS boards
- - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
- - Convert MPC85xxADS to use common CFI flash driver
- - Fix PCI window on MPC85xx; remove unneeded PCI initialization
- from board_early_init_f()
- - Provide SW workaround for PCI initialization on 85xx CDS
-
-* Patches by George G. Davis, 24 Aug 2004:
- - Enable ramdisk/initrd tagged param support for omap1610h2_config
- - Remove static network setup defaults from mx1ads_config
- - update ARM boards to use constants from mach-types.h
-
-* Patch by Gary Jennejohn, 04 Oct 2004:
- - fix I2C on at91rm9200
- - add support for Ricoh RS5C372A RTC
-
-* Patch by Gary Jennejohn, 01 Oct 2004:
- - add support for CMC PU2 board
- - add support for I2C on at91rm9200
-
-* Patch by Gary Jennejohn, 28 Sep 2004:
- fix baudrate handling on at91rm9200
-
-* Patch by Yuli Barcohen, 22 Aug 2004:
- - remove ZPC.1900 board-specific flash driver;
- switch the port to generic CFI driver;
- - port clean-up
-
-* Patch by Hinko Kocevar, 21 Aug 2004:
- Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB
-
-* Clean up tools/bmp_logo.c to not add trailing white space
-
-* Patch by Hinko Kocevar, 21 Aug 2004:
- - Group common framebuffer functions in common/lcd.c
- - Group common framebuffer macros and #defines in include/lcd.h
- - Provide calc_fbsize() for video ATAG
-
-* Patch by Sam Song, 21 August 2004:
- - Fix a typo in README
- - Align "(RO)" output for "flinfo" after "protect on"
- - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency
- ratio 1:1 when core frequency less than 50MHz
-
-* Patches by Hinko Kocevar, 21 Aug 2004:
- - fix some "use of label at end of compound statement" warnings
- - Define type of LCD panel on lubbock board if CONFIG_LCD is used
-
-* Patch by Steven Scholz, 16 Aug 2004:
- - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
- - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
- - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
- - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
- into cpu/arm920t/$(SOC)/
-
-* Patches by Sean Chang, 09 Aug 2004:
- - Added support for both 8 and 16 bit mode access to System ACE CF
- through MPU.
- - Fixed missing System ACE CF device during get FAT partition info
- in fat_register_device function.
- - Enabled System ACE CF support on ML300.
-
-* Patch by Sean Chang, 09 Aug 2004:
- Synch defines for saveenv and do_saveenv functions so they get
- compiled under the same statement.
-
-* Patch by Sean Chang, 09 Aug 2004:
- - Added I2C support for ML300.
- - Added support for ML300 to read out its environment information
- stored on the EEPROM.
- - Added support to use board specific parameters as part of
- U-Boot's environment information.
- - Updated MLD files to support configuration for new features
- above.
-
-* Patches by Travis Sawyer, 05 Aug 2004:
- - Remove incorrect bridge settings for eth group 6
- - Add call to setup bridge in ppc_440x_eth_initialize
- - Fix ppc_440x_eth_init to reset the phy only if its the
- first time through, otherwise, just check the phy for the
- autonegotiated speed/duplex. This allows the use of netconsole
- - only print the speed/duplex the first time the phy is reset.
-
-* Patch by Shlomo Kut, 29 Mar 2004:
- Add support for MKS Instruments "Quantum" board
-
-* Fix build problem with Cogent boards;
- avoid using <asm/byteorder.h> when using the host compiler
-
-* Patch by Ganapathi C, 04 Aug 2004:
- Fix NFS timeout issue
-
-* Patch by Yuli Barcohen, 19 Jul 2004:
- - Fix host tools building in Cygwin environment
- - Fix header files search order for host tools
-
-* Patch by Tom Armistead, 19 Jul 2004:
- Fix kgdb.S support for 74xx_75x cpu
-
-* Patch by Jon Loeliger, 15 Jul 2004:
- Fix MPC85xx I2C driver
-
-* Fix problems with CDROM drive as slave device on Lite5200 IDE bus.
-
-* Patch by Stephen Williams, 15 July 2004
- Set the PCI class code for JSE board as part of PCI interface setup
-
-* Patch by Michael Bendzick, 15 Jul 2004:
- Fix problem with writes with odd sizes in drivers/cfi_flash.c when
- CFG_FLASH_USE_BUFFER_WRITE is set
-
-* Patch by Yuli Barcohen, 13 Jul 2004:
- Allow clock setting on MPC866/MPC885 series chips according to
- environment variable `cpuclk'
-
-* Patch by Yuli Barcohen, 20 Apr 2004:
- Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
-
-* Patch by Vincent Dubey, 24 Sep 2004:
- Add support for xaeniax board
-
-* Add comment about non-GPL character of standalone applications to
- COPYING file
-
-* Fix FEC ethernet problem on NSCU board.
-
-* Patch by Gary Jennejohn, 09 Sep 2004:
- allow to use USART1 as console port on at91rm9200dk boards
-
-* Patch by Stefan Roese, 16 Sep 2004:
- Update AR405 board.
-
-* Fix SysClk handling for PPChameleon and CATcenter boards
-
-* Patch by Detlev Zundel, 08 Sep 2004:
- Update etags build target
-
-* Improve NetConsole support: add support for broadcast destination
- address and buffered input.
-
-* Cleanup compiler warnings for GCC 3.3.x and later
-
-* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
-
-* Add support for IDS "NC650" board
-
-* Add automatic update support for LWMON board
-
-* Clear Block Lock-Bits when erasing flash on LWMON board.
-
-* Fix return code of "fatload" command
-
-* Enable MSDOS/VFAT filesystem support for LWMON board
-
-* Patch by Martin Krause, 03 Aug 2004:
- change timing for SM501 graphics controller on TQM5200 module
-
-* Patch by Mark Jonas, 13 July 2004:
- - Total5200 LCD now run in little endian mode. Endianess conversion
- is done in hardware.
- - Removed last reference to "console" environment variable.
-
-* Patches by Lars Munch, 12 Jul 2004:
- - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
- board specific
- - split out the LXT971A PHY from ns_9750_eth.h
- - split the dm9161 phy part out of at91rm9200_ether.c
-
-* Patch by Andreas Engel, 12 Jul 2004:
- Replaced hardcoded PL011 clock frequency with config variable.
- Fixed wrong CONFIG_CMD_DFL doc.
-
-* Patch by Thomas Viehweger, 09 Jun 2004:
- make it possible to remove chpart when there is only one partition
-
-* Add support for console over UDP (compatible to Ingo Molnar's
- netconsole patch under Linux)
-
-* Patch by Jon Loeliger, 16 Jul 2004:
- - support larger DDR memories up to 2G on the PC8540/8560ADS and
- STXGP3 boards
- - Made MPC8540/8560ADS be 33Mhz PCI by default.
- - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
- and CONFIG_L2_INIT_RAM options.
- - Refactor Local Bus initialization out of SDRAM setup.
- - Re-implement new version of LBC11/DDR11 errata workarounds.
- - Moved board specific PCI init parts out of CPU directory.
- - Added TLB entry for PCI-1 IO Memory
- - Updated README.mpc85xxads
-
-* Patch by Sascha Hauer, 28 Jun:
- - add generic support for Motorola i.MX architecture
- - add support for mx1ads, mx1fs2 and scb9328 boards
-
-* Patches by Marc Leeman, 23 Jul 2004:
- - Add define for the PCI/Memory Buffer Configuration Register
- - corrected comments in cpu/mpc824x/cpu_init.c
-
-* Add support for multiple serial interfaces
- (for example to allow modem dial-in / dial-out)
-
-* Patch by Stefan Roese, 15 Jul 2004:
- cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
-
-* Fix NSCU config; add ethernet wakeup code.
-
-* Add link for preloader for Motorola ColdFire to README.m68k
-
-* Patch by Michael Bendzick, 12 Jul 2004:
- fix output formatting in drivers/cfi_flash.c
-
-* Patch by Mark Jonas, 02 Jul 2004:
- Fix lowboot (again) on MPC5xxx
-
-* Patch by Curt Brune, 07 Jul 2004:
- relocate exception vectors on arm720t if needed
-
-* Patch by George G. Davis, 06 Jul 2004:
- - update mach-types.h to latest arm.linux.org.uk master list
- - Set correct OMAP1610 bi_arch_number for build target
-
-* Patch by Curt Brune, 06 Jul 2004:
- evb4510: add support for timer interrupt; cleanup
-
-* Patch by Dan Poirot, 06 Jul 2004:
- Fix sbc8260 environment variables
-
-* Cleanup redundand "console" environment variable
-
-* Patch by Mark Jonas, 05 Jul 2004:
- add support for the Total5100's and Total5200's LCD screen
-
-* Patches by Dan Eisenhut, 01 Jul 2004:
- - README fixes.
- - Move doc2000.h include to prevent compiler warning on some boards
-
-* Patch by Mark Jonas, 01 Jul 2004:
- Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
- MGT5100 and MPC5200 based Freescale platforms.
-
-* Patch by Philippe Robin, 01 Jul 2004:
- Add initialization for Integrator and versatile board files.
-
-* Patch by Hinko Kocevar, 01 Jun 2004:
- Fix VFD FB allocation, add LCD FB allocation on ARM
-
-* Patch by Martin Krause, 30 Jun 2004:
- Add support for TQM5200 board
-
-* Patch by Martin Krause, 29 Jun 2004:
- Add loopw command: infinite write loop on address range
-
-* Patches by Yasushi Shoji, 29 Jun 2004:
- - add empty include/asm-microblaze/processor.h
- - add to CREDITS and MAINTAINERS
- - add gd initialization
- - add MicroBlaze and SUZAKU board to MAKEALL script
- - add reset support for SUZAKU
- - add flush_cache() for MicroBlaze
- - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed
- size flash memory on SUZAKU
-
-* Patch by Prakash Kumar, 27 Jun 2004:
- Add support for the PXA250 based Intrinsyc Cerf board.
-
-* Patch by Yasushi Shoji, 27 Jun 2004:
- fix comment in include/common.h
-
-* Rename SBC8560 into sbc8560 for consistency
-
-* Patch by Daniel Poirot, 24 Jun 2004:
- Add support for Wind River's sbc8240 board
-
-* Patches by Yasushi Shoji, 26 Jun 2004:
- - drivers/serial_xuartlite.c: fix "return 0" in void function
- - add microblaze support to mkimage tool
-
-* Patch by Fred Klatt, 25 Jun 2004:
- Add support for WindRiver's sbc8560 board
-
-* Patch by Nicolas Lacressonniere, 24 Jun 2004
- Small Bugs fixes for "at91rm9200dk" board:
- - Timing modifications for SPI DataFlash access
- - Fix NAND flash detection bug
-
-* Patch by Nicolas Lacressonniere, 24 Jun 2004:
- Add Support for Flash AT49BV6416 for AT91RM9200DK board
-
-* Patch by Jon Loeliger, 17 June 2004:
- Completion of the 8540ADS/8560ADS updates:
- Fix some PCI and Rapid I/O memory maps,
- Initialize both TSEC 1 and 2,
- Initialize SDRAM
- Update MAINTAINER for 85xx boards and README.mpc85xxads
-
-* Patch by Yuli Barcohen, 16 Jun 2004:
- Remove obsolete AdderII port which was superseded by unified
- AdderII/Adder87x port
-
-* Patch by Ladislav Michl, 16 Jun 2004:
- Fix gcc-3.3.3 warnings for smc91111.c
-
-* Patch by Stefan Roese, 02 Jul 2004:
- - Fix bug in 405 ethernet driver; allocated data not cleared!
- - Fix problem in 405 i2c driver; don't try to print without console!
-
-* Patch by Paul Ruhland, 11 Jun 2004:
- Remove debug code from 'board/lpd7a40x/flash.c'
-
-* Patch by Andrea Marson, 11 Jun 2004:
- Update for PPChameleon board:
- - support for SysClk @ 25MHz
- - support for Silicon Motion SM712 VGA controller
- - some clean ups
-
-* Patches by Richard Woodruff, 10 Jun 2004:
- - fix problems with examples/stubs.c for GCC >= 3.4
- - fix problems with gd initialization
-
-* Patch by Curt Brune, 17 May 2004:
- - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
- - Add support for ESPD-Inc. EVB4510 Board
-
-* Patch by Marc Leeman, 11 May 2004:
- Fix for MPC8245 - reading PPC Memory from another device with the
- PPC as PCI target device corrupts data due to interenal hardware
- buffering.
-
-* Fix "cls" command when used with splash screen
-
-* Increase NFS download timeout (now 1 min - 10 sec is to short for a
- slow download of a big image)
-
-* Add "cls" function to MPC823 LCD driver so we can reinitialize the
- display even after showing a bitmap
-
-* Patch by Josef Wagner, 04 Jun 2004:
- - DDR Ram support for PM520 (MPC5200)
- - support for different flash types (PM520)
- - USB / IDE / CF-Card / DiskOnChip support for PM520
- - 8 bit boot rom support for PM520/CE520
- - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- - I2C and RTC support for CPC45
- - support of new flash type (28F160C3T) for CPC45
-
-* Fix flash parameters passed to Linux for PPChameleon board
-
-* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
-
-* Patch by Paul Ruhland, 10 Jun 2004:
- fix support for Logic SDK-LH7A404 board and clean up the
- LH7A404 register macros.
-
-* Patch by Matthew McClintock, 10 Jun 2004:
- Modify code to select correct serial clock on Sandpoint8245
-
-* Patch by Robert Schwebel, 10 Jun 2004:
- Add support for Intel K3 strata flash.
-
-* Patch by Thomas Brand, 10 Jun 2004:
- Fix "loads" command on DK1S10 board
-
-* Patch by Yuli Barcohen, 09 Jun 2004:
- Add support for 8MB flash SIMM and JFFS2 file system on
- Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
-
-* Patch by Yuli Barcohen, 09 Jun 2004:
- Add support for Analogue&Micro Adder87x and the older AdderII board.
-
-* Patch by Ming-Len Wu, 09 Jun 2004:
- Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
-
-* Patch by Sam Song, 09 Jun 2004:
- - Add support for RPXlite_DW board
- - Update FLASH driver for 4*AM29DL323DB90VI
- - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
-
-* Patch by Mark Jonas, 08 June 2004:
- - Make MPC5200 boards evaluate the SVR to print processor name and
- version in checkcpu() (cpu/mpc5xxx/cpu.c).
-
-* Patch by Kai-Uwe Bloem, 06 May 2004:
- Fix endianess problem in cramfs code
-
-* Patch by Tom Armistead, 04 Jun 2004:
- Add support for MAX6900 RTC
-
-* Patches by Ladislav Michl, 03 Jun 2004:
- - fix cfi_flash.c on LE systems
- - let 'make mrproper' delete u-boot.img as well
- - turn printf into debug in cfi_flash.c
-
-* Patch by Kurt Stremerch, 28 May 2004:
- Add support for Exys XSEngine board
-
-* Patch by Martin Krause, 27 May 2004:
- Fix a MPC5xxx I2C timing issue in i2c_probe().
-
-* Patch by Leif Lindholm, 27 May 2004:
- Fix board_init_f() for dbau1x00 board.
-
-* Patch by Imre Deak, 26 May 2004:
- On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
- Set flash base accordingly, and decide whether to do or skip board
- specific setup steps.
-
-* Patch by Josef Baumgartner, 26 May 2004:
- Add missing define in include/asm-m68k/global_data.h
-
-* Patch by Josef Baumgartner, 25 May 2004:
- Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
-
-* Patch by Paul Ruhland, 24 May 2004:
- fix SDRAM initialization for LPD7A400 board.
-
-* Patch by Jian Zhang, 20 May 2004:
- add support for environment in NAND flash
-
-* Patch by Yuli Barcohen, 20 May 2004:
- Add support for Interphase iSPAN boards.
-
-* Patches by Paul Ruhland, 17 May 2004:
- - Add I/O functions to the smc91111 ethernet driver to support the
- Logic LPD7A40x boards.
- - Add support for the Logic Zoom LH7A40x based SDK board(s),
- specifically the LPD7A400.
-
-* Patches by Robert Schwebel, 15 May 2004:
- - call MAC address reading code also for SMSC91C111;
- - make SMSC91C111 timeout configurable, remove duplicate code
- - fix get_timer() for PXA
- - update doc/README.JFFS2
- - use "bootfile" env variable also for jffs2
-
-* Patch by Tolunay Orkun, 14 May 2004:
- Add support for Cogent CSB472 board (8MB Flash Rev)
-
-* Patch by Thomas Viehweger, 14 May 2004:
- - flash.h: more flash types added
- - immap_8260.h: some bits added (useful for RMII)
- - cmd_coninfo.c: typo corrected, printf -> puts
- - reduced size by replacing spaces with tab
-
-* Patch by Robert Schwebel, 13 May 2004:
- Add 'imgextract' command: extract one part of a multi file image.
-
-* Patches by Jon Loeliger, 11 May 2004:
- Dynamically handle REV1 and REV2 MPC85xx parts.
- (Jon Loeliger, 10-May-2004).
- New consistent memory map and Local Access Window across MPC85xx line.
- New CCSRBAR at 0xE000_0000 now.
- Add RAPID I/O memory map.
- New memory map in README.MPC85xxads
- (Kumar Gala, 10-May-2004)
- Better board and CPU identification on MPC85xx boards at boot.
- (Jon Loeliger, 10-May-2004)
- SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
- Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
- (Jim Robertson, 10-May-2004)
- Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
- Supports multiple PHYs.
- (Andy Fleming, 10-May-2004)
- Some README.MPC85xxads updates.
- (Kumar Gala, 10-May-2004)
- Copyright updates for "Freescale"
- (Andy Fleming, 10-May-2004)
-
-* Patch by Stephen Williams, 11 May 2004:
- Add flash support for ST M29W040B
- Reduce JSE specific flash.c to remove dead code.
-
-* Patch by Markus Pietrek, 04 May 2004:
- Fix clear_bss code for ARM systems (all except s3c44b0 which
- doesn't clear BSS at all?)
-
-* Fix "ping" problem on INC-IP board. Strange problem:
- Sometimes the store word instruction hangs while writing to one of
- the Switch registers, but only if the next instruction is 16-byte
- aligned. Moving the instruction into a separate function somehow
- makes the problem go away.
-
-* Patch by Rishi Bhattacharya, 08 May 2004:
- Add support for TI OMAP5912 OSK Board
-
-* Patch by Sam Song May, 07 May 2004:
- Fix typo of UPM table for rmu board
-
-* Patch by Pantelis Antoniou, 05 May 2004:
- - Intracom board update.
- - Add Codec POST.
-
-* Add support for the second Ethernet interface for the 'PPChameleon'
- board.
-
-* Patch by Dave Peverley, 30 Apr 2004:
- Add support for OMAP730 Perseus2 Development board
-
-* Patch by Alan J. Luse, 29 Apr 2004:
- Fix flash chip-select (OR0) option register setting on FADS boards.
-
-* Patch by Alan J. Luse, 29 Apr 2004:
- Report MII network speed and duplex setting properly when
- auto-negotiate is not enabled.
-
-* Patch by Jarrett Redd, 29 Apr 2004:
- Fix hang on reset on Ocotea board due to flash in wrong mode.
-
-* Patch by Dave Peverley, 29 Apr 2004:
- add MAC address detection to smc91111 driver
-
-* Patch by David Müller, 28 Apr 2004:
- fix typo in lib_arm/board.c
-
-* Patch by Tolunay Orkun, 20 Apr 2004:
- - README update: add CONFIG_CSB272 and csb272_config
- - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
- i2cfast environment variable
-
-* Patch by Yuli Barcohen, 19 Apr 2004:
- - Rename DUET_ADS to MPC885ADS
- - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
- - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
- - Clean up FADS family port to use the new defines
-
-* Fix PCI support on CPC45 board
-
-* Patch by Scott McNutt, 25 Apr 2004:
- Add Nios GDB/JTAG Console support:
- - Add stubs to support gdb via JTAG.
- - Add support for console over JTAG.
- - Minor cleanup.
-
-* Add support for CATcenter board (based on PPChameleon ME module)
-
-* Patch by Klaus Heydeck, 12 May 2004:
- Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
- load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
- various changes to KUP4 board specific files
-
-* Fix minor network problem on MPC5200: need some delay between
- resetting the PHY and sending the first packet. Implemented in a
- "natural" way by invoking the PHY reset and initialization code
- only once after power on vs. each time the interface is brought up.
-
-* Add some limited support for low-speed devices to SL811 USB controller
- (at least "usb reset" now passes successfully and "usb info" displays
- correct information)
-
-* Change init sequence for multiple network interfaces: initialize
- on-chip interfaces before external cards.
-
-* Fix memory leak in the NAND-specific JFFS2 code
-
-* Fix SL811 USB controller when attached to a USB hub
-
-* Fix config option spelling in PM520 config file
-
-* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
- patches by Pantelis Antoniou, 30 Mar 2004)
-
-* Fix minor NAND JFFS2 related issue
-
-* Fixes for SL811 USB controller:
- - implement workaround for broken memory stick
- - improve error handling
-
-* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
- cope with congested networks.
-
-======================================================================
-Changes for U-Boot 1.1.1:
-======================================================================
-
-* Patch by Travis Sawyer, 23 Apr 2004:
- Fix VSC/CIS 8201 phy descrambler interoperability timing due to
- errata from Vitesse Semiconductor.
-
-* Patch by Philippe Robin, 22 Apr 2004:
- Fix ethernet configuration for "versatile" board
-
-* Patch by Kshitij Gupta, 21 Apr 2004:
- Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
-
-* Patch by Steven Scholz, 24 Feb 2004:
- Fix a bug in AT91RM9200 ethernet driver:
- The MII interface is now initialized before accessing the PHY.
-
-* Patch by John Kerl, 19 Apr 2004:
- Use U-boot's miiphy.h for PHY register names, rather than
- introducing a new header file.
-
-* Update pci_ids.h from linux-2.4.26
-
-* Patch by Masami Komiya, 19 Apr 2004:
- Fix problem cause by VLAN function on little endian architecture
- without VLAN environment
-
-* Clean up the TQM8xx_YYMHz configurations; allow to use the same
- binary image for all clock frequencies. Implement run-time
- optimization of flash access timing based on the actual bus
- frequency.
-
-* Modify KUP4X board configuration to use SL811 driver for USB memory
- sticks (including FAT / VFAT filesystem support)
-
-* Add SL811 Host Controller Interface driver for USB
-
-* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README
-
-* Patch by Pantelis Antoniou, 19 Apr 2004:
- Allow to use shell style syntax (i. e. ${var} ) with standard parser.
- Minor patches for Intracom boards.
-
-* Patch by Christian Pell, 19 Apr 2004:
- cleanup support for CF/IDE on PCMCIA for PXA25X
-
-* Temporarily disabled John Kerl's extended MII command code because
- "miivals.h" is missing
-
-* Patches by Mark Jonas, 13 Apr 2004:
- - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
- - Add sync instructions to IceCube SDRAM init code
- - Move SDRAM chip constants into seperate include files
- - Unify DDR and SDR initialization code
- - Unify all IceCube (Lite5xxx) target names
-
-* Patch by John Kerl, 16 Apr 2004:
- Enable ranges in mii command, e.g. mii read 0-1f 0 or
- mii read 4-7 18-1a. Also add mii dump subcommand for
- pretty-printing standard regs 0-5.
-
-* Patch by Stephen Williams, 16 April 2004:
- fix typo in JSE.h; update MAINTAINERS
-
-* Patch by Matthew S. McClintock, 14 Apr 2004:
- fix initdram function for utx8245 board
-
-* Patch by Markus Pietrek, 14 Apr 2004:
- use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag
-
-* Patch by Reinhard Meyer, 18 Apr 2004:
- provide the IDE Reset Function for EMK 5200 boards
-
-* Patch by Masami Komiya, 12 Apr 2004:
- fix pci_hose_write_config_{byte,word}_via_dword problems
-
-* Patch by Sangmoon Kim, 12 Apr 2004:
- Update max RAM size for debris board
-
-* Patch by Travis Sawyer, 08 Apr 2004:
- Add TLB entry for second DIMM slot on ocotea
-
-* Patch by Masami Komiya, 08 Apr 2004:
- add RTL8169 network driver
-
-* Patch by Dan Malek, 07 Apr 2004:
- - Add support for RPC/STx GP3, Motorola 8560 board
- - Update 85xx TSEC driver so it searches MII for first available PHY
- and uses that one.
- - Add functions to support console MII commands.
-
-* Patch by Tolunay Orkun, 07 Apr 2004:
- Move initialization of bi_iic_fast[]
- from board_init_f() to board_init_r()
-
-* Patch by Yasushi Shoji, 07 Apr 2004:
- Cleanup microblaze port
-
-* Patch by Sangmoon Kim, 07 Apr 2004:
- Add auto SDRAM module detection for Debris board
-
-* Patch by Rune Torgersen, 06 Apr 2004:
- - Fix some PCI problems on the MPC8266ADS board
- - Fix the location of some PCI entries in the immap structure
-
-* Patch by Yasushi Shoji, 07 Apr 2004:
- - add support for microblaze processors
- - add support for AtmarkTechno "suzaku" board
-
-* Configure PPChameleon board to use redundand environment in flash
-
-* Configure PPChameleon board to use JFFS2 NAND support.
-
-* Added support for JFFS2 filesystem (read-only) on top of NAND flash
-
-* Patch by Rune Torgersen, 16 Apr 2004:
- LBA48 fixes
-
-* Patches by Pantelis Antoniou, 16 Apr 2004:
- - add support for a new version of an Intracom board and fix
- various other things on others.
- - add verify support to the crc32 command (define
- CONFIG_CRC32_VERIFY to enable it)
- - fix FEC driver for MPC8xx systems:
- 1. fix compilation problems for boards that use dynamic
- allocation of DPRAM
- 2. shut down FEC after network transfers
- - HUSH parser fixes:
- 1. A new test command was added. This is a simplified version of
- the one in the bourne shell.
- 2. A new exit command was added which terminates the current
- executing script.
- 3. Fixed handing of $? (exit code of last executed command)
- - Fix some compile problems;
- add "once" functionality for the netretry variable
-
-* Patch by George G. Davis, 02 Apr 2004:
- add support for Intel Assabet board
-
-* Patch by Stephen Williams, 01 Apr 2004:
- Add support for Picture Elements JSE board
-
-* Patch by Christian Pell, 01 Apr 2004:
- Add CompactFlash support for PXA systems.
-
-* Patches by Pantelis Antoniou, 30 Mar 2004:
- - add auto-complete support to the U-Boot CLI
- - add support for NETTA and NETPHONE boards; fix NETVIA board
- - add support for the Epson 156x series of graphical displays
- (These displays are serial and not suitable for using a normal
- framebuffer console on them)
- - add infrastructure needed in order to POST any DSPs in a board
- - improve and fix various things in the MPC8xx FEC driver:
- 1. The new 87x and 88x series of processors have two FECs,
- and the new driver supports them both.
- 2. Another change in the 87x/88x series is support for
- the RMII (Reduced MII) interface. However numerous
- changes are needed to make it work since the PHYs
- are connected to the same lines. That means that
- you have to address them correctly over the MII
- interface.
- 3. We now correctly match the MII/RMII interface
- configuration to what the PHY reports.
- - Fix problem when readingthe MII status register. Due to the
- internal design of many PHYs you have to read the register
- twice. The problem is more apparent in 10Mbit mode.
- - add new mode ".jffs2s" for reading from a NAND device: it just
- skips over bad blocks.
- - add networking support for VLANs (802.1q), and CDP (Cisco
- Discovery Protocol)
- - some minor patches / cleanup
-
-* Patch by Yuli Barcohen, 28 Mar 2004:
- - Add support for MPC8272 family including MPC8247/8248/8271/8272
- - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
- - Change configuration method for MPC8260ADS family
-
-* add startup code to clear the BSS of standalone applications
-
-* Fix if / elif handling bug in HUSH shell
-
-======================================================================
-Changes for U-Boot 1.1.0:
-======================================================================
-
-* Patch by Mark Jonas: Remove config.tmp files only when
- unconfiguring the board
-
-* Adapt RMU board for bigger flash memory
-
-* Patch by Klaus Heydeck, 13 Mar 2003:
- Add support for KUP4X Board
-
-* Patch by Pavel Bartusek, 21 Mar 2004
- Add Reiserfs support
-
-* Patch by Hinko Kocevar, 20 Mar 2004
- - Add auto-release for SMSC LAN91c111 driver
- - Add save/restore of PTR and PNR regs as suggested in datasheet
-
-* Patch by Stephen Williams, 19 March 2004
- Increase speed of sector reads from SystemACE,
- shorten poll timeout and remove a useless reset
-
-* Patch by Tolunay Orkun, 19 Mar 2004:
- Make GigE PHY 1000Mbps Speed/Duplex detection conditional
- (CONFIG_PHY_GIGE)
-
-* Patch by Brad Kemp, 18 Mar 2004:
- prevent machine checks during a PCI scan
-
-* Patch by Pierre Aubert, 18 Mar 2004:
- Fix string cleaning in IDE identification
-
-* Patch by Pierre Aubert, 18 Mar 2004:
- - Unify video mode handling for Chips & Technologies 69000 Video
- chip and Silicon Motion SMI 712/710/810 Video chip
- - Add selection of the video output (CRT or LCD) via 'videoout'
- environment variable for the Silicon Motion
- - README update
-
-* Patch by Pierre Aubert, 18 Mar 2004:
- include/common.h typo fix
-
-* Patches by Tolunay Orkun, 17 Mar 2004:
- - Add support for bd->bi_iic_fast[] initialization via environment
- variable "i2cfast" (CONFIG_I2CFAST)
- - Add "i2cfast" u-boot environment variable support for csb272
-
-* Patch by Carl Riechers, 17 Mar 2004:
- Ignore '\0' characters in console input for use with telnet and
- telco pads.
-
-* Patch by Leon Kukovec, 17 Mar 2004:
- typo fix for strswab prototype #ifdef
-
-* Patches by Thomas Viehweger, 16 Mar 2004:
- - show PCI clock frequency on MPC8260 systems
- - add FCC_PSMR_RMII flag for HiP7 processors
- - in do_jffs2_fsload(), take load address from load_addr if not set
- explicit, update load_addr otherwise
- - replaced printf by putc/puts when no formatting is needed
- (smaller code size, faster execution)
-
-* Patch by Phillippe Robin, 16 Mar 2004:
- avoid dereferencing NULL pointer in lib_arm/armlinux.c
-
-* Patch by Stephen Williams, 15 Mar 2004:
- Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation
-
-* Patch by Tolunay Orkun, 15 Mar 2004:
- Initialize bi_opbfreq to real OPB frequency via get_OPB_freq()
-
-* Patch by Travis Sawyer, 15 Mar 2004:
- Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port
-
-* Add start-up delay to make sure power has stabilized before
- attempting to switch on USB on SX1 board.
-
-* Patch by Josef Wagner, 18 Mar 2004:
- - Add support for MicroSys XM250 board (PXA255)
- - Add support for MicroSys PM828 board (MPC8280)
- - Add support for 32 MB Flash on PM825/826
- - new SDRAM refresh rate for PM825/PM826
- - added support for MicroSys PM520 (MPC5200)
- - replaced Query by Identify command in CPU86/flash.c
- to support 28F160F3B
-
-* Fix wrap around problem with udelay() on ARM920T
-
-* Add support for Macronix flash on TRAB board
-
-* Patch by Pierre Aubert, 15 Mar 2004:
- Fix buffer overflow in IDE identification
-
-* Fix power-off of LCD for out-of-band temperatures on LWMON board
-
-* Remove redundand #define in IceCube.h
-
-* Patch by Steven Scholz, 27 Feb 2004:
- - Adding get_ticks() and get_tbclk() for AT91RM9200
- - Many white space fixes in cpu/at91rm9200/interrupts.c
-
-* Patches by Steven Scholz, 20 Feb 2004:
- some cleanup in AT91RM9200 related code
-
-* Patches by Travis Sawyer, 12 Mar 2004:
- - Fix Gigabit Ethernet support for 440GX
- - Add Gigabit Ethernet Support to MII PHY utilities
-
-* Patch by Brad Kemp, 12 Mar 2004:
- Fixes for drivers/cfi_flash.c:
- - Better support for x8/x16 implementations
- - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
- - Added defines for AMD command and address constants
-
-* Patch by Leon Kukovec, 12 Mar 2004:
- Fix get_dentfromdir() to correctly handle deleted dentries
-
-* Patch by George G. Davis, 11 Mar 2004:
- Remove hard coded network settings in TI OMAP1610 H2
- default board config
-
-* Patch by George G. Davis, 11 Mar 2004:
- add support for ADS GraphicsClient+ board.
-
-* Patch by Pierre Aubert, 11 Mar 2004:
- - add bitmap command and splash screen support in cfb console
- - add [optional] origin in the bitmap display command
-
-* Patch by Travis Sawyer, 11 Mar 2004:
- Fix ocotea board early init interrupt setup.
-
-* Patch by Thomas Viehweger, 11 Mar 2004:
- Remove redundand code; add PCI-specific bits to include/mpc8260.h
-
-* Patch by Stephan Linz, 09 Mar 2004
- - Add support for the SSV ADNP/ESC1 (Nios Softcore)
-
-* Patch by George G. Davis, 9 Mar 2004:
- fix recent build failure for SA1100 target
-
-* Patch by Travis Sawyer, 09 Mar 2004:
- Support native interrupt mode for the IBM440GX.
- Previously it was running in 440GP compatibility mode.
-
-* Patch by Philippe Robin, 09 Mar 2004:
- Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
- Platform support.
-
-* Patch by Masami Komiya, 08 Mar 2004:
- Don't overwrite server IP address or boot file name
- when the boot server does not return values
-
-* Patch by Tolunay Orkun, 5 Mar 2004:
- Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
-
-* Patch by Tolunay Orkun, 5 Mar 2004:
- Fix early board initialization for Cogent CSB272 board
-
-* Patch by Ed Okerson, 3 Mar 2004:
- fix CFI flash writes for little endian systems
-
-* Patch by Reinhard Meyer, 01 Mar 2004:
- generalize USB and IDE support for MPC5200 with according
- changes to IceCube.h and TOP5200.h
- add Am29LV256 256 MBit FLASH support for TOP5200 boards
- add info about USB and IDE to README
-
-* Patch by Yuli Barcohen, 4 Mar 2004:
- Fix problems with GCC 3.3.x which changed handling of global
- variables explicitly initialized to zero (now in .bss instead of
- .data as before).
-
-* Patch by Leon Kukovec, 02 Mar 2004:
- add strswab() to fix IDE LBA capacity, firmware and model numbers
- on little endian machines
-
-* Patch by Masami Komiya, 02 Mar 2004:
- - Remove get_ticks() from NFS code
- - Add verification of RPC transaction ID
-
-* Patch by Pierre Aubert, 02 Mar 2004:
- cleanup for IDE and USB drivers for MPC5200
-
-* Patch by Travis Sawyer, 01 Mar 2004:
- Ocotea:
- - Add IBM PPC440GX Ref Platform support (Ocotea)
- Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
- Adapted to U-Boot and 440GX port
- 440gx_enet.c:
- - Add gracious handling of all Ethernet Pin Selections for 440GX
- - Add RGMII selection for Cicada CIS8201 Gigabit PHY
- ppc440.h:
- - Add needed bit definitions
- - Fix formatting
-
-* Patch by Carl Riechers, 1 Mar 2004:
- Add PPC440GX prbdv0 divider to fix memory clock calculation.
-
-* Patch by Stephan Linz, 27 Feb 2004
- - avoid problems for targets without NFS download support
-
-* Patch by Rune Torgersen, 27 Feb 2004:
- - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
- - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
- - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)
-
-* Patch by Masami Komiya, 27 Feb 2004:
- Fix rarpboot: add autoload by NFS
-
-* Patch by Dan Eisenhut, 26 Feb 2004:
- fix flash_write return value in saveenv
-
-* Patch by Stephan Linz, 11 Dec 2003
- expand config.mk to avoid trigraph warnings on NIOS
-
-* Rename "BMS2003" board into "HMI10"
-
-* SX1 patches: use "serial#" for USB serial #; use redundand environment
- storage; auto-set console on USB port (using preboot command)
-
-* Add support for SX1 mobile phone; add support for USB-based console
- (enable with "setenv stdout usbtty; setenv stdin usbtty")
-
-* Fix LOWBOOT configuration for MPC5200 with DDR memory
-
-* Fix SDRAM timings for LITE5200 / IceCube board
-
-* Handle Auti-MDIX / connection status for INCA-IP
-
-* Fix USB problems when attempting to read 0 bytes
-
-* Patch by Travis Sawyer, 26 Feb 2004:
- Fix broken compile for XPEDITE1K target.
-
-* Patch by Stephan Linz, 26 Feb 2004:
- Bug fix for NFS code on NIOS targets
-
-* Patch by Stephen Williams, 26 Feb 2004:
- Break up SystemACE reads of large block counts
-
-* Patch by Pierre Aubert, 26 Feb 2004
- add IDE support for MPC5200
-
-* Patch by Masami Komiya, 26 Feb 2004:
- add autoload via NFS
-
-* Patch by Stephen Williams
- Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
- elsewhere in the source.
-
-* Patch by Steven Scholz, 25 Feb 2004:
- - Timeouts in FPGA code should be based on CFG_HZ
- - Minor cleanup in code for Altera FPGA ACEX1K
-
-* Patch by Steven Scholz, 25 Feb 2004:
- Changed "Directory Hierarchy" section in README
-
-* Patch by Masami Komiya, 25 Feb 2004:
- Reduce copy count in nfs_read_reply() of NFS code
-
-* Patch by Markus Pietrek, 24 Feb 2004:
- NS9750 DevBoard added
-
-* Patch by Pierre Aubert, 24 Feb 2004
- add USB support for MPC5200
-
-* Patch by Steven Scholz, 24 Feb 2004:
- - fix MII commands to use values from last command
-
-* Patch by Torsten Demke, 24 Feb 2004:
- Add support for the eXalion platform (SPSW-8240, F-30, F-300)
-
-* Patch by Rahul Shanbhag, 19 Feb 2004:
- Fixes for for OMAP1610 board:
- - shift some IRQ specific code to platform.S file
- - remove duplicatewatchdog reset code from start.S
-
-* Make Auto-MDIX Support configurable on INCA-IP board
-
-* Fix license for mkimage tool
-
-* Patch by Masami Komiya, 24 Feb 2004:
- Update NetBootFileXferSize in NFS code
-
-* Patch by Scott McNutt, 24 Feb 2004:
- fix packet length in NFS code
-
-* Patch by Masami Komiy, 22 Feb 2004:
- Add support for NFS for file download
-
-* Patch by Andrea Scian, 17 Feb 2004:
- Add support for S3C44B0 processor and DAVE B2 board
-
-* Patch by Steven Scholz, 20 Feb 2004:
- - Add support for MII commands on AT91RM9200 boards
- - some cleanup in AT91RM9200 ethernet code
-
-* Patch by Peter Ryser, 20 Feb 2004:
- Add support for the Xilinx ML300 platform
-
-* Patch by Stephan Linz, 17 Feb 2004:
- Fix watchdog support for NIOS
-
-* Patch by Josh Fryman, 16 Feb 2004:
- Fix byte-swapping for cfi_flash.c for different bus widths
-
-* Patch by Jon Diekema, 14 Jeb 2004:
- Remove duplicate "FPGA Support" notes from the README file
-
-* Patches by Reinhard Meyer, 14 Feb 2004:
- - update board/emk tree; use common flash driver
- - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
- [adapted for other PPC CPUs -- wd]
- - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c
-
-* Patch by Jon Diekema, 13 Feb 2004:
- Call show_boot_progress() whenever POST "FAILED" is printed.
-
-* Patch by Nishant Kamat, 13 Feb 2004:
- Add support for TI OMAP1610 H2 Board
- Fixes for cpu/arm926ejs/interrupt.c
- (based on Richard Woodruff's patch for arm925, 16 Oct 03)
- Fix for a timer bug in OMAP1610 Innovator
- Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2
-
-* Patches by Stephan Linz, 12 Feb 2004:
- - add support for NIOS timer with variable period preload counter value
- - prepare POST framework support for NIOS targets
-
-* Patch by Denis Peter, 11 Feb 2004:
- add POST support for the MIP405 board
-
-* Patch by Laurent Mohin, 10 Feb 2004:
- Fix buffer overflow in common/usb.c
-
-* Patch by Tolunay Orkun, 10 Feb 2004:
- Add support for Cogent CSB272 board
-
-* Patch by Thomas Elste, 10 Feb 2004:
- Add support for NET+50 CPU and ModNET50 board
-
-* Patch by Sam Song, 10 Feb 2004:
- Fix typos in cfi_flash.c
-
-* Patch by Leon Kukovec, 10 Feb 2004
- Fixed long dir entry slot id calculation in get_vfatname
-
-* Patch by Robin Gilks, 10 Feb 2004:
- add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==,
- !=, <>, <, >, <=, >=)
-
-* Fix problem with side effects in macros in include/usb.h
-
-* Patch by David Benson, 13 Nov 2003:
- bug 841358 - fix TFTP download size limit
-
-* Fixing bug 850768:
- improper flush_cache() in load_serial()
-
-* Fixing bug 834943:
- MPC8540 - missing volatile declarations
-
-* Patch by Stephen Williams, 09 Feb 2004:
- Add support for Xilinx SystemACE chip:
- - New files common/cmd_ace.c and include/systemace.h
- - Hook systemace support into cmd_fat and the partition manager
-
-* Patch by Travis Sawyer, 09 Feb 2004:
- Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
-
-* Patch by Travis Sawyer, 09 Feb 2004:
- o 440GX:
- - Fix PCI Indirect access for type 1 config cycles with ppc440.
- - Add phymode for 440 enet
- - fix pci pre init
- o XPedite1K:
- - Change board_pre_init to board_early_init_f
- - Add user flash to bus controller setup
- - Fix pci pre init
- - Fix is_pci_host to check GPIO for monarch bit
- - Force xpedite1k to pci conventional mode (via #define option)
-
-* Patch by Brad Kemp, 4 Feb 2004:
- - handle the machine check that is generated during the PCI scans
- on 82xx processors.
- - define the registers used in the IMMR by the PCI subsystem.
-
-* Patch by Pierre Aubert, 03 Feb 2004:
- cpu/mpc5xxx/start.S: copy MBAR into SPR311
-
-* Patch by Jeff Angielski, 03 Feb 2004:
- Fix copy & paste error in cpu/mpc8260/pci.c
-
-* Patch by Reinhard Meyer, 24 Jan 2004:
- Fix typo in cpu/mpc5xxx/pci_mpc5200.c
-
-* Add Auto-MDIX support for INCA-IP
-
-* Some code cleanup
-
-* Patch by Josef Baumgartner, 10 Feb 2004:
- Fixes for ColdFire port
-
-* Patch by Brad Kemp, 11 Feb 2004:
- Fix CFI flash driver problems
-
-* Make sure to use a bus clock divider of 2 only when running TQM8xxM
- modules at CPU clock frequencies above 66 MHz.
-
-* Optimize flash programming speed for LWMON (by another 100% :-)
-
-* Patch by Jian Zhang, 3 Feb 2004:
- - Changed the incorrect FAT12BUFSIZE
- - data_begin in fsdata can be negative. Changed it to be short.
-
-* Patches by Stephan Linz, 30 Jan 2004:
- 1: - board/altera/common/flash.c:flash_erase():
- o allow interrupts befor get_timer() call
- o check-up each erased sector and avoid unexpected timeouts
- - board/altera/dk1c20/dk1s10.c:board_early_init_f():
- o enclose sevenseg_set() in cpp condition
- - remove the ASMI configuration for DK1S10_standard_32 (never present)
- - fix some typed in mistakes in the NIOS documentation
- 2: - split DK1C20 configuration into several header files:
- o two new files for each NIOS CPU description
- o U-Boot related part is remaining in DK1C20.h
- 3: - split DK1S10 configuration into several header files:
- o two new files for each NIOS CPU description
- o U-Boot related part is remaining in DK1S10.h
- 4: - Add support for the Microtronix Linux Development Kit
- NIOS CPU configuration at the Altera Nios Development Kit,
- Stratix Edition (DK-1S10)
- 5: - Add documentation for the Altera Nios Development Kit,
- Stratix Edition (DK-1S10)
- 6: - Add support for the Nios Serial Peripharel Interface (SPI)
- (master only)
- 7: - Add support for the common U-Boot SPI framework at
- RTC driver DS1306
-
-* Patch by Rahul Shanbhag, 28 Jan 2004:
- Fix flash protection/locking handling for OMAP1610 innovator board.
-
-* Patch by Rolf Peukert, 28 Jan 2004:
- fix flash write problems on CSB226 board (write with 32 bit bus width)
-
-* Patches by Mark Jonas, 16 Jan 2004:
- - fix rounding error when calculating baudrates for MPC5200 PSCs
- - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
- time which is not supported
-
-* Patch by Yuli Barcohen, 26 Jan 2004:
- Allow bzip2 compression for small memory footprint boards
-
-* Patch by Brad Kemp, 21 Jan 2004:
- Add support for CFI flash driver for both the Intel and the AMD
- command sets.
-
-* Patch by Travis Sawyer, 20 Jan 2004:
- Fix pci bridge auto enumeration of sibling p2p bridges.
-
-* Patch by Tolunay Orkun, 12 Jan 2004:
- Add some delays as needed for Intel LXT971A PHY support
-
-* Patches by Stephan Linz, 09 Jan 2004:
- - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
- - make DK1C20 board configuration related to ASMI conform to
- documentation
-
-* Patch by Anders Larsen, 09 Jan 2004:
-
- ARM memory layout fixes: the abort-stack is now set up in the
- correct RAM area, and the BSS is zeroed out as it should be.
-
- Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
- of the linker scripts are replaced by '__bss_start' and '_end',
- resp., which is a further step to eliminate unnecessary differences
- between the implementation of the CPU architectures.
-
-* Patch by liang a lei, 9 Jan 2004:
- Fix Intel 28F128J3 ID in include/flash.h
-
-* Patch by Masami Komiya, 09 Jan 2004:
- add support for TB0229 board (NEC VR4131 MIPS processor)
-
-* Patch by Leon Kukovec, 12 Dec 2003:
- changed extern __inline__ into static __inline__ in
- include/linux/byteorder/swab.h
-
-* Patch by Travis Sawyer, 30 Dec 2003:
- Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
- select MDI port based on enabled EMAC device.
- Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
- base PrPMC board.
-
-* Patch by Wolter Kamphuis, 15 Dec 2003:
- made CONFIG_SILENT_CONSOLE usable on all architectures
-
-* Disable date command on TQM866M - there is no RTC on MPC866
-
-* Fix variable CPU clock for MPC859/866 systems for low CPU clocks
-
-* Implement adaptive SDRAM timing configuration based on actual CPU
- clock frequency for INCA-IP; fix problem with board hanging when
- switching from 150MHz to 100MHz
-
-* Add PCMCIA CS support for BMS2003 board
-
-* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
- see doc/README.MPC866 for details;
- implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
- calculate CPU clock frequency from PLL register values.
-
-* Add support for 128 MB RAM on TQM8xxL/M modules
-
-* Fix PS/2 keyboard problem caused by statically initialized variable
- pointing to a location in flash
-
-* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130.
-
-* The PS/2 mux on the BMS2003 board needs 450 ms after power on
- before we can access it; add delay in case we are faster (with no
- CF card inserted)
-
-* Cleanup of some init functions
-
-* Make sure SCC Ethernet is always stopped by the time we boot Linux
- to avoid Linux crashes by early packets coming in.
-
-* Accelerate flash accesses on LWMON board by using buffered writes
-
-* Fix typo in Makefile;
- fix problem with PARTNUM detection
-
-* Patch by Reinhard Meyer, 09 Jan 2004:
- - add RTC support for MPC5200 based boards (requires RTC_XTAL)
-
-* Add support for IDE LED on BMS2003 board
- (exclusive with status LED!)
-
-* Add support for PS/2 keyboard (used with PS/2 multiplexor on
- BMS2003 board)
-
-* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004:
- Add common files for "emk" boards
-
-* Add a common get_ram_size() function and modify the the
- board-specific files to invoke that common implementation.
-
-======================================================================
-Changes for U-Boot 1.0.1:
-======================================================================
-
-* Set default clock for INCA-IP to 150 MHz
-
-* Make BMS2003 use a separate config file to avoid #ifdef mess;
- add I2C support; add support for DS1337 RTC
-
-* Add CompactFlash support for BMS2003 board
-
-* Add support for status LED on BMS2003 board
-
-* Patch by Scott McNutt, 02 Jan 2004:
- Add support for the Nios Active Serial Memory Interface (ASMI)
- on Cyclone devices
-
-* Patch by Andrea Marson, 16 Dec 2003:
- Add support for the PPChameleon ME and HI modules
-
-* Patch by Yuli Barcohen, 22 Dec 2003:
- Add support for Motorola DUET ADS board (MPC87x/88x)
-
-* Patch by Robert Schwebel, 15 Dec 2003:
- add support for cramfs (uses JFFS2 command interface)
-
-* Patches by Stephan Linz, 11 Dec 2003:
- - more documentation for NIOS port
- - new struct nios_pio_t, struct nios_spi_t
- - Reconfiguration for NIOS Development Kit DK1C20:
- o move board related code from board/dk1c20
- to board/altera/dk1c20
- o create a new common source path board/altera/common
- and move generic flash access stuff into it
- o change/expand configuration file DK1C20.h
- - Add support for NIOS Development Kit DK1S10
- - Add status LED support for NIOS systems
- - Add dual 7-segment LED support for Altera NIOS DevKits
-
-* Patch by Ronen Shitrit, 10 Dec 2003:
- Add support for the Marvell DB64360 / DB64460 development boards
-
-* Patch by Detlev Zundel, 10 Dec 2003:
- fix dependency problem in examples/Makefile
-
-* Patch by Denis Peter, 8 Dec 2003
- - add support for the PATI board (MPC555)
- - add SPI support for the MPC5xx
-
-* Patch by Anders Larsen, 08 Dec 2003:
- add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG
- to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target;
- cleanup some redundand #defines
-
-* Patch by André Schwarz, 8 Dec 2003:
- fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
- - TX and RX deskriptors must be quad-word aligned
- - does not work with only one TX deskriptor
- - standard reset method does not work
-
-* Patch by Masami Komiya, 08 Dec 2003:
- add RTL8139 ethernet driver
-
-* Patches by Ed Okerson, 07 Dec 2003:
- - fix ethernet for the AU1x00 processors in little-endian mode.
- - extend memsetup.S for the AU1x00 processors in BE and LE modes
-
-* Minor code cleanup (coding style)
-
-* Patch by Reinhard Meyer, 30 Dec 2003:
- - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
- - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
- - turned debug print of PHY registers into a function (called in two places)
- - added support for EMK MPC5200 based modules
-
-* Fix MPC8xx PLPRCR_MFD_SHIFT typo
-
-* Add support for TQM866M modules
-
-* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
-
-* Fix a few compiler warnings
-
-* Patch by Reinhard Meyer, 28 Dec 2003:
- Add initial support for TOP5200 board
-
-* Make CPU clock on ICA-IP board controllable by a "cpuclk"
- environment variable which can set to "100", "133", or "150". The
- CPU clock will be configured accordingly upon next reboot. Other
- values are ignored. In case of an invalid or undefined "cpuclk"
- value, the compile-time default CPU clock speed will be used.
-
-* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory
- window that is used to access the UART registers by the Linux driver)
-
-* Patch by Reinhard Meyer, 20 Dec 2003:
- Fix clock calculation for the MPC5200 for higher clock frequencies
- (above 2**32 / 10 = 429.5 MHz).
-
-* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration
-
-* Fix IceCube CLKIN configuration (it's 33.000000MHz)
-
-* Add new configuration for IceCube board with DDR memory
-
-* Update TRAB memory configurations
-
-* Add JFFS2 support for INCA-IP board
-
-* Patch by Bill Hargen, 09 Dec 2003:
- - BUBINGA405EP: changed flash driver to protect top sector containing
- first instruction.
- - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM.
- - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access).
- - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1).
- - 405EP: added/fixed support for "reginfo" command.
- - 4xx: removed spurious MII error messages on "mii info" command.
-
-* Patch by Bernhard Kuhn, 28 Nov 2003:
- add support for ColdFire CPU
- add support for Motorola M5272C3 and M5282EVB boards
-
-* Patch by Pierre Aubert, 24 Nov 2003:
- - add a return value for the fpga command
- - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT
- is defined. If ide_preinit fails, ide_init is aborted.
- - fix an endianess problem in fat.h
-
-* Patch by Wolter Kamphuis, 05 Dec 2003:
- Add support for SNMC's QS850/QS823/QS860T boards
-
-* Patch by Yuli Barcohen, 3 Dec 2003:
- "revive" U-Boot support for old Motorola MPC860ADS board
-
-* Patch by Cam(ilo?), 03 Dec 2003:
- make examples build even with broken Montavista objcopy
-
-* Patch by Pavel Bartusek, 27 Nov 2003:
- fix conversion problem with "bootretry" evironment variable
-
-* Patch by Andre Schwarz, 24 Nov 2003:
- add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
-
-* Patch by Pavel Bartusek, 21 Nov 2003:
- set ZMII bridge speed on 440
-
-* Patch by Anders Larsen, 17 Nov 2003:
- Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
-
-* Patches by David Müller, 14 Nov 2003:
- - board/mpl/common/common_util.c
- * implement support for BZIP2 compressed images
- * various cleanups (printf -> puts, ...)
- - board/mpl/common/flash.c
- * report correct errors to upper layers
- * check the erase fail and VPP low bits in status reg
- - board/mpl/vcma9/cmd_vcma9.c
- - board/mpl/vcma9/flash.c
- * various cleanups (printf -> puts, ...)
- - common/cmd_usb.c
- * fix typo in comment
- - cpu/arm920t/usb_ohci.c
- * support for S3C2410 is missing in #if line
- - drivers/cs8900.c
- * reinit some registers in case of error (cable missing, ...)
- - fs/fat/fat.c
- * support for USB/MMC devices is missing in #if line
- - include/configs/MIP405.h
- - include/configs/PIP405.h
- * enable BZIP2 support
- * enlarge malloc space to 1MiB because of BZIP2 support
- - include/configs/VCMA9.h
- * enable BZIP2 support
- * enlarge malloc space to 1MiB because of BZIP2 support
- * enable USB support
- - lib_arm/armlinux.c
- * change calling convention of ARM Linux kernel as
- described on http://www.arm.linux.org.uk/developer/booting.php
-
-* Patch by Thomas Lange, 14 Nov 2003:
- Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to
- support all these AMD boards.
-
-* Patch by Thomas Lange, 14 Nov 2003:
- Workaround for mips au1x00 physical memory accesses (the au1x00
- uses a 36 bit bus internally and cannot access physical memory
- directly. Use the uncached SDRAM address instead of the physical
- one.)
-
-* Patch by Xue Ligong (Joe), 13 Nov 2003:
- add Realtek 8019 ethernet driver
-
-* Patch by Yuli Barcohen, 13 Nov 2003:
- MPC826xADS/PQ2FADS cleanup
-
-* Patch by Anders Larsen, 12 Nov 2003:
- Update README to mark the PORTIO commands non-standard
-
-* Patch by Nicolas Lacressonnière, 12 Nov 2003:
- update for for Atmel AT91RM9200DK development kit:
- - support for environment variables in DataFlash
- - Atmel DataFlash AT45DB1282 support
-
-* Patch by Jeff Carr, 11 Nov 2003:
- add support for new version of 8270 processors
-
-* Patches by George G. Davis, 05 Nov 2003:
- - only pass the ARM linux initrd tag to the kernel when an initrd
- is actually present
- - update omap1510inn configuration file
-
-* Patches by Stephan Linz, 3 Nov 2003:
- - more endianess fixes for LAN91C111 driver
- - CFG_HZ configuration patch for NIOS Cyclone board
-
-* Patch by Stephan Linz, 28 Oct 2003:
- fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c
-
-* Patch by Steven Scholz, 20 Oct 2003:
- - make "mii info <addr>" show infor for PHY at "addr" only
- - Endian fix for miiphy_info()
-
-* Patch by Gleb Natapov, 19 Sep 2003:
- Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c
-
-* Patch by Anders Larsen, 17 Sep 2003:
- Bring ARM memory layout in sync with the documentation:
- stack and malloc-heap are now located _below_ the U-Boot code
-
-* Accelerate booting on TRAB board: read and check autoupdate image
- headers first instead of always reading the whole images.
-
-* Fix type in MPC5XXX code (pointed out by Victor Wren)
-
-* Enabled password check on RMU board
-
-* Fix configuration problem with IceCube in LOWBOOT configuration:
- envrionment got embedded, corrupting the image layout.
-
-* Fix NEC display names (it's 6440 [for 640x480], not 6640).
-
-* Added BMS2003 board
- add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display
-
-* Fix flash driver for TRAB board (must use Unlock Bypass Reset
- command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
- and CPLD
-
-* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
- recent tools
-
-* Add checksum verification to 'imls' command
-
-* Add bd_info fields needed for 4xx Linux I2C driver
-
-* Patch by Martin Krause, 4 Nov. 2003:
- Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)
-
-* Print used network interface when CONFIG_NET_MULTI is set
-
-* Patch by Bernhard Kuhn, 28 Oct 2003:
- Add low boot support for MPC5200
-
-* Fix problem with dual PCMCIA support (NSCU)
-
-* Fix MPC5200 I2C initialization function
-
-======================================================================
-Changes for U-Boot 1.0.0:
-======================================================================
-
-* Fix parameter passing to standalone images with bootm command
-
-* Patch by Kyle Harris, 30 Oct 2003:
- Fix build errors for ixdp425 board
-
-* Patch by David M. Horn, 29 Oct 2003:
- Fixes to build under CYGWIN
-
-* Get IceCube MGT5100 working (again)
-
-* Fix problems in memory test on some boards (which was not
- non-destructive as intended)
-
-* Patch by Gary Jennejohn, 28 Oct 2003:
- Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack
- to prevent stack overflow on ARM systems
-
-* Patch by Stephan Linz, 28 Oct 2003:
- fix init sequence error for NIOS port
-
-* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name
-
-* Add CONFIG_VERSION_VARIABLE to TRAB configuration
-
-* Patch by Xiao Xianghua, 23 Oct 2003:
- small patch for mpc85xx
-
-* Fix small problem in MPC5200 I2C driver
-
-* Fix FCC3 support on ATC board
-
-* Correct header printing for multi-image files in do_bootm()
-
-* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED
-
-* Fix PCI problems on PPChameleon board
-
-* Patch by Steven Scholz, 18 Oct 2003:
- Fix AT91RM9200 ethernet driver
-
-* Patch by Nye Liu, 17 Oct 2003:
- Fix typo in include/mpc8xx.h
-
-* Patch by Richard Woodruff, 16 Oct 03:
- Fixes for cpu/arm925/interrupt.c
- - Initialize timestamp & lastdec vars.
- - fix timestamp overflows.
- - fix lastdec overflow.
- - smarter normalization to allow udelay() below 1ms to work.
-
-* Patch by Scott McNutt, 16 Oct
- add networking support for the Altera Nios Development Kit,
- Cyclone Edition (DK-1C20)
-
-* Patch by Jon Diekema, 14 Oct 2003:
- add hint about doc/README.silent to README file
-
-* Add CompactFlash support for NSCU
-
-* Fix PCI problems on PPChameleonEVB
-
-* TRAB auto-update: Base decision if we have to strip the image
- header on image type as encoded in the header
- (include image type patch by Martin Krause, 17 Oct 2003)
-
-* Patches by Xianghua Xiao, 15 Oct 2003:
-
- - Added Motorola CPU 8540/8560 support (cpu/85xx)
- - Added Motorola MPC8540ADS board support (board/mpc8540ads)
- - Added Motorola MPC8560ADS board support (board/mpc8560ads)
-
-* Fix flash timings on TRAB board
-
-* Make sure HUSH is initialized for running auto-update scripts
-
-* Make 5200 reset command _really_ reset the board, without running
- any other code after it
-
-* Fix errors with flash erase when range spans across banks
- that are mapped in reverse order
-
-* Fix flash mapping and display on P3G4 board
-
-* Patch by Kyle Harris, 15 Jul 2003:
- - add support for Intel IXP425 CPU
- - add support for IXDP425 eval board
-
-* Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent
- for more information
-
-* Patch by Steven Scholz, 10 Oct 2003
- - Add support for Altera FPGA ACEX1K
-
-* Patches by Thomas Lange, 09 Oct 2003:
- - fix cmd_ide.c for non ppc boards (read/write functions did not
- add ATA base address)
- - fix for shannon board
- - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
- - Endian swap ATA identity for all big endian CPUs, not just PPC
- - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
- args to linux
- - add support for dbau1x00 board (MIPS32)
-
-* Patch by Sangmoon Kim, 07 Oct 2003:
- add support for debris board
-
-* Patch by Martin Krause, 09 Oct 2003:
- Fixes for TRAB board
- - /board/trab/rs485.c: correct baudrate
- - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
- udelay(); fix some timing problems with adc controller
- - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
- modify commands: touch and buzzer
-
-* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE
- (quick & dirty workaround for rogue pointer problem in get_vfatname());
- Use direct function calls for auto_update instead of hush commands
-
-* Patch by Scott McNutt, 04 Oct 2003:
- - add support for Altera Nios-32 CPU
- - add support for Nios Cyclone Development Kit (DK-1C20)
-
-* Patch by Steven Scholz, 29 Sep 2003:
- - A second parameter for bootm overwrites the load address for
- "Standalone Application" images.
- - bootm sets environment variable "filesize" to the resulting
- (uncompressed) data length for "Standalone Application" images
- when autostart is set to "no". Now you can do something like
- if bootm $fpgadata $some_free_ram ; then
- fpga load 0 $some_free_ram $filesize
- fi
-
-* Patch by Denis Peter, 25 Sept 2003:
- add support for the MIP405 Rev. C board
-
-* Patch by Yuli Barcohen, 25 Sep 2003:
- add support for Zephyr Engineering ZPC.1900 board
-
-* Patch by Anders Larsen, 23 Sep 2003:
- add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only
- implemented for the x86 architecture)
-
-* Patch by Sangmoon Kim, 23 Sep 2003:
- fix pll_pci_to_mem_multiplier table for MPC8245
-
-* Patch by Anders Larsen, 22 Sep 2003:
- enable timed autoboot on PXA
-
-* Patch by David Müller, 22 Sep 2003:
- - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver
- returns correct libgcc file path
- - "latency" reduction of busy-loop waiting to improve "U-Boot" boot
- time on s3c24x0 systems
-
-* Patch by Jon Diekema, 19 Sep 2003:
- - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet
- link state to the fault LED.
- - In NetLoop, make the Fault LED reflect the link status. The link
- status gets updated on entry, and on timeouts.
-
-* Patch by Anders Larsen, 18 Sep 2003:
- allow mkimage to build and run on Cygwin-hosted systems
-
-* Patch by Frank Müller, 18 Sep 2003:
- use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in
- cpu/mpc8xx/fec.c
-
-* Patch by Pantelis Antoniou, 16 Sep 2003:
- add tool to compute fileds in the PLPRCR register for MPC86x
-
-* Use IH_TYPE_FILESYSTEM for TRAB "disk" images.
-
-* Fix build problems under FreeBSD
-
-* Add generic filesystem image type
-
-* Make fatload set filesize environment variable
-
-* enable basic / medium / high-end configurations for PPChameleonEVB
- board; fix NAND code
-
-* enable TFTP client code to specify to the server the desired
- timeout value (see RFC-2349)
-
-* Improve SDRAM setup for TRAB board
-
-* Suppress all output with splashscreen configured only if "splashimage"
- is set
-
-* Fix problems with I2C support for mpc5200
-
-* Adapt TRAB configuration and auto_update to new memory layout
-
-* Add configuration for wtk board
-
-* Add support for the Sharp LQ065T9DR51U LCD display
-
-* Patch by Rune Torgersen, 17 Sep 2003:
- - Fixes for MPC8266 default config
- - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
-
-* Patches by Jon Diekema, 17 Sep 2003:
- - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
- env_common.c)
- - sbc8260 tweaks
- - adjust "help" output
-
-* Patches by Anders Larsen, 17 Sep 2003:
- - fix spelling errors
- - set GD_FLG_DEVINIT flag only after device function pointers
- are valid
- - Allow CFG_ALT_MEMTEST on systems where address zero isn't
- writeable
- - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
- - trigger watchdog while waiting in serial driver
-
-* Add auto-update code for TRAB board using USB memory sticks,
- support new configuration with more memory
-
-* disable MPC5200 bus pipelining as workaround for bus contention
-
-* Modify XLB arbiter priorities on MPC5200 so all devices use same
- priority; configure critical interrupts to be handled like external
- interrupts
-
-* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
- go back to 66 MHz for stability
-
-* Patches by Jon Diekema, 15 Sep 2003:
- - add description for missing CFG_CMD_* entries in the README file
- - sacsng tweaks
-
-* Patch by Gleb Natapov, 14 Sep 2003:
- enable watchdog support for all MPC824x boards that have a watchdog
-
-* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
- "Non-octet Aligned Frame" errors we see at 100 Mbps
-
-* Patch by Sharad Gupta, 14 Sep 2003:
- fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
-
-* Patch by llandre, 11 Sep 2003:
- update configuration for PPChameleonEVB board
-
-* Patch by David Müller, 13 Sep 2003:
- various changes to VCMA9 board specific files
-
-* Add I2C support for MGT5100 / MPC5200
-
-* Patch by Rune Torgersen, 11 Sep 2003:
- Changed default memory option on MPC8266ADS to NOT be Page Based
- Interleave, since this doesn't work very well with the standard
- 16MB DIMM
-
-* Patch by George G. Davis, 12 Sep 2003:
- fix Makefile settings for sk98 driver
-
-* Patch by Stefan Roese, 12 Sep 2003:
- - new boards added: DP405, HUB405, PLU405, VOH405
- - some esd boards updated
- - cpu/ppc4xx/sdram.c: disable memory controller before setting
- first values
- - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems
-
-* Patch by Martin Krause, 11 Sep 2003:
- add burn-in tests for TRAB board
-
-* Enable instruction cache on MPC5200 board
-
-* Patch by Denis Peter, 11 Sep 2003:
- - fix USB data pointer assignment for bulk only transfer.
- - prevent to display erased directories in FAT filesystem.
-
-* Change output format for NAND flash - make it look like for other
- memory, too
-
-======================================================================
-Changes for U-Boot 0.4.8:
-======================================================================
-
-* Add I2C and RTC support for RMU board
-
-* Patches by Denis Peter, 9 Sep 2003:
- add FAT support for IDE, SCSI and USB
-
-* Patches by Gleb Natapov, 2 Sep 2003:
- - cleanup of POST code for unsupported architectures
- - MPC824x locks way0 of data cache for use as initial RAM;
- this patch unlocks it after relocation to RAM and invalidates
- the locked entries.
-
-* Patch by Gleb Natapov, 30 Aug 2003:
- new I2C driver for mpc107 bridge. Now works from flash.
-
-* Patch by Dave Ellis, 11 Aug 2003:
- - JFFS2: fix typo in common/cmd_jffs2.c
- - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- - JFFS2: remove node version 0 warning
- - JFFS2: accept JFFS2 PADDING nodes
- - SXNI855T: add AM29LV800 support
- - SXNI855T: move environment from EEPROM to flash
- - SXNI855T: boot from JFFS2 in NOR or NAND flash
-
-* Patch by Bill Hargen, 11 Aug 2003:
- fixes for I2C on MPC8240
- - fix i2c_write routine
- - fix iprobe command
- - eliminates use of global variables, plus dead code, cleanup.
-
-* Add support for USB Mass Storage Devices (BBB)
- (tested with USB memory sticks only)
-
-* Avoid flicker on TRAB's VFD
-
-* Add support for SK98xx driver
-
-* Add PCI support for SL8245 board
-
-* Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB)
- or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
- Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
-
-* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz)
- to allow for more accurate baudrate settings
- (error now 0.7% at 115 kbps, instead of 3.5% before)
-
-* Patch by Andreas Mohr, 4 Sep 2003:
- Fix a lot of spelling errors
-
-* Add support for PPChameleon Eval Board
-
-* Add support for P3G4 board
-
-* Fix problem with MGT5100 FEC driver: add "early" MAC address
- initialization
-
-* Patch by Yuli Barcohen, 7 Aug 2003:
- check BCSR to detect if the board is configured in PCI mode
-
-======================================================================
-Changes for U-Boot 0.4.7:
-======================================================================
-
-* Patch by Raghu Krishnaprasad, 7 Aug 2003:
- add support for Adder II MPC852T module
-
-* Patch by George G. Davis, 19 Aug 2003:
- fix TI Innovator/OMAP1510 pin configs
-
-* Patches by Kshitij, 18 Aug 2003
- - add support for arm926ejs cpu core
- - add support for TI OMAP 1610 Innovator Board
-
-* Patch by Yuli Barcohen, 14 Aug 2003:
- add support for bzip2 uncompression
-
-* Add GCC library to examples/Makefile so GCC utility functions will
- be resolved, too
-
-* Add I2C and RTC support for RMU board using software I2C driver
- (because of better response to iprobe command); fix problem with
- "reset" command
-
-* Patch by Matthias Fuchs, 28 Aug 2003:
- Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
- CONFIG_BOOTP_MAKS (see README).
-
-* Fix ICU862 environment problem
-
-* Fix RAM size detection for RMU board
-
-* Implement "reset" for MGT5100/MPC5200 systems
-
-======================================================================
-Changes for U-Boot 0.4.6:
-======================================================================
-
-* Make Ethernet autonegotiation on INCA-IP work for all clock rates;
- allow selection of clock frequency as "make" target
-
-* Implement memory autosizing code for IceCube boards
-
-* Configure network port on INCA-IP for autonegotiation
-
-* Fix overflow problem in network timeout code
-
-* Patch by Richard Woodruff, 8 Aug 2003:
- Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
-
-======================================================================
-Changes for U-Boot 0.4.5:
-======================================================================
-
-* Update for TQM board defaults:
- disable clocks_in_mhz, enable boot count limit
-
-* Removed tools/gdb from "make all" target. Added make target "gdbtools"
- in toplevel directory instead. Removed astest.c from tools/gdb because
- it is no longer relevant.
-
-* Fix PCI support for MPC5200 / IceCube Board
-
-* Map ISP1362 USB OTG controller for NSCU board
-
-* Patch by Brad Parker, 02 Aug 2003:
- fix sc520_cdp problems
-
-* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements)
-
-* Allow erase command to cross flash bank boundaries
-
-* Patch by Scott McNutt, 21 Jul 2003:
- Add support for LynuxWorks Kernel Downloadable Images (KDIs).
- Both LynxOS and BlueCat linux KDIs are supported.
-
-* Patch by Richard Woodruff, 25 Jul 2003:
- use more reliable reset for OMAP/925T
-
-* Patch by Nye Liu, 25 Jul 2003:
- fix typo in mpc8xx.h
-
-* Patch by Richard Woodruff, 24 Jul 2003:
- Fixes for cmd_nand.c:
- - Fixed null dereferece which could result in incorrect ECC values.
- - Added support for devices with no Ready/Busy signal hooked up.
- - Added OMAP1510 read/write protect handling.
- - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock
- for non-JFFS2.
- - Switched default ECC to be JFFS2.
-
-* Allow crc32 to be used at address 0x000
-
-* Provide consistent interface to standalone applications to access
- the 'global_data' structure
- Provide a doc/README.standalone more useful to users/developers.
-
-* Make IceCube MGT5100 FEC driver work
-
-* Implement new mechanism to export U-Boot's functions to standalone
- applications: instead of using (PPC-specific) system calls we now
- use a jump table; please see doc/README.standalone for details
-
-* Patch by Dave Westwood, 24 Jul 2003:
- added support for Unity OS (a proprietary OS)
-
-* Patch by Detlev Zundel, 23 Jul 2003:
- add "imls" command to print flash table of contents
-
-* Fix cold boot detection for log buffer reset
-
-* Return error for invalid length specifiers with "cp.X" etc.
-
-* Fix startup problem on MIPS
-
-* Allow for CONFIG_SPLASH_SCREEN even when no explicit
- bitmap support is configured
-
-* Patch by Bill Hargen, 18 Jul 2003:
- - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c
-
-* Patch by Denis Peter, 18 Jul 2003:
- - fix memory configuration for MIP405T
- - fix printout of baudrate for "loadb <loadaddr> <baudrate>"
-
-* Cleanup of TQM82xx configurations; use "official" board types
- to make selection easier.
-
-* Patch by Martin Krause, 17 Jul 2003:
- add delay to get I2C working with "imm" command and s3c24x0_i2c.c
-
-* Patch by Richard Woodruff, 17 July 03:
- - Fixed bug in OMAP1510 baud rate divisor settings.
-
-* Patch by Nye Liu, 16 July 2003:
- MPC860FADS fixes:
- - add MPC86xADS support (uses MPC86xADS.h)
- - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
- o PLPRCR changes
- o BRG changes (EXTAL/XTAL restricted to 10MHz)
- o don't trust gclk() software measurement by default, depend on
- CONFIG_8xx_GCLK_FREQ
- - add DRAM SIMM not installed detection
- - use more "correct" SDRAM initialization sequence
- - allow different SDRAM sizes (8xxADS has 8M)
- - default DER is 0
- - remove unused MAMR defines from FADS860T.h (all done in fads.c)
- - rename MAMR/MBMR defines to be more consistent. Should eventually
- be merged into MxMR to better reflect the PowerQUICC datasheet.
-
-* Patch by Yuli Barcohen, 16 Jul 2003:
- support new Motorola PQ2FADS-ZU evaluation board which replaced
- MPC8260ADS and MPC8266ADS
-
-======================================================================
-Changes for U-Boot 0.4.4:
-======================================================================
-
-* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)
-
-* Add support for MGT5100 and MPC5200 processors
-
-* Patch by Lutz Dennig, 15 Jul 2003:
- update for R360MPI board
-
-======================================================================
-Changes for U-Boot 0.4.3:
-======================================================================
-
-* Patches by Kshitij, 04 Jul 2003
- - added support for arm925t cpu core
- - added support for TI OMAP 1510 Innovator Board
-
-* Patches by Martin Krause, 14 Jul 2003:
- - add I2C support for s3c2400 systems (trab board)
- - (re-) add "ping" to command table
-
-* Fix handling of "slow" POST routines
-
-* Patches by Yuli Barcohen, 13 Jul 2003:
- - Correct flash and JFFS2 support for MPC8260ADS
- - fix PVR values and clock generation for PowerQUICC II family
- (8270/8275/8280)
-
-* Patch by Bernhard Kuhn, 08 Jul 2003:
- - add support for M68K targets
-
-* Patch by Ken Chou, 3 Jul:
- - Fix PCI config table for A3000
- - Fix iobase for natsemi.c
- (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
-
-* Allow to enable "slow" POST routines by key press on power-on
-* Fix temperature dependend switching of LCD backlight on LWMON
-* Tweak output format for LWMON
-
-* Patch by Stefan Roese, 11 Jul 2003:
- - Fix bug in CONFIG_VERSION_VARIABLE.
- - AR405 config updated.
- - OCRTC/ORSG: bsp command added.
- - ASH405 bsp update.
-
-======================================================================
-Changes for U-Boot 0.4.2:
-======================================================================
-
-* Add support for NSCU board
-
-* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
-
-* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
- mirror bit flash on TQM8xxM modules
-
-* Patch by Kenneth Johansson, 30 Jun 2003:
- get rid of MK_CMD_ENTRY macro; update doc/README.command
-
-* Patch by Seb James, 30 Jun 2003:
- Improve documentation of I2C configuration in README
-
-* Fix problems with previous log buffer "fixes"
-
-* Fix minor help text issues
-
-* "log append" did not append a newline
-
-======================================================================
-Changes for U-Boot 0.4.1:
-======================================================================
-
-* Fix some missing commands, cleanup header files
- (autoscript, bmp, bsp, fat, mmc, nand, portio, ...)
-
-* Rewrite command lookup and help command (fix problems with bubble
- sort when sorting command name list). Minor cleanup here and there.
-
-* Merge from "stable branch", tag LABEL_2003_06_28_1800-stable:
- - Allow to call sysmon function interactively
- - PIC on LWMON board needs delay after power-on
- - Add missing RSR definitions for MPC8xx
- - Improve log buffer handling: guarantee clean reset after power-on
- - Add support for EXBITGEN board (aka "genie")
- - Add support for SL8245 board
-
-* Code cleanup:
- - remove trailing white space, trailing empty lines, C++ comments, etc.
- - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
-
-* Patches by Kenneth Johansson, 25 Jun 2003:
- - major rework of command structure
- (work done mostly by Michal Cendrowski and Joakim Kristiansen)
-
-======================================================================
-Changes for U-Boot 0.4.0:
-======================================================================
-
-* Patches by Robert Schwebel, 26 Jun 2003:
- - csb226 configuration updated
- - credits for logodl port updated
- - innokom configuration updated
- - logodl tree update, still with coding style inconsistencies
- - added OCM for ppc405 warning to README
-
-* Patch by Pantelis Antoniou, 25 Jun 2003:
- update NetVia with V2 board support
-
-* Header file cleanup for ARM
-
-* Patch by Murray Jensen, 24 Jun 2003:
- - make sure to use only U-boot provided header files
- - fix problems with ".rodata.str1.4" section as used by GCC-3.x
-
-* Patch by Stefan Roese, 24 Jun 2003:
- - Update esd ASH405 board files.
- - Update esd DASA_SIM config file.
- - Add ping command to some esd boards.
-
-* Patch by Yuli Barcohen, 23 Jun 2003:
- Update for MPC8260ADS board
-
-* Patch by Murray Jensen, 23 Jun 2003:
- - cleanup of GCC 3.x compiler warnings
-
-* Patch by Rune Torgersen, 4 Jun 2003:
- add large memory support for MPC8266ADS board
-
-* Patch by Richard Woodruff, 19 June 03:
- - Enabled standard u-boot device abstraction for ARM
- - Enabled console device for ARM
- - Initilized bi_baudrate for ARM
-
-* Patch by Bill Hargen, 23 Apr 2003:
- fix byte order for 824x I2C addresses (write op)
-
-* Patch by Murray Jensen, 20 Jun 2003:
- - hymod update
- - cleanup (especially for gcc-3.x compilers)
-
-* Patch by Tom Guilliams, 20 Jun 2003:
- added CONFIG_750FX support for IBM 750FX processors
-
-* Patch by Devin Crumb, 02 Apr 2003:
- Fix clock divider rounding problem in drivers/serial.c
-
-* Patch by Richard Woodruff, 19 June 03:
- - Fixed smc91c111 driver to sync with the u-boot environment
- (driver/smc91c111.c).
- - Added eth_init error return check in NetLoop (net/net.c).
-
-* Patch by Ken Chou, 19 June 2003:
- Added support for A3000 SBC board (Artis Microsystems Inc.)
-
-* Patches by Murray Jensen, 17 Jun 2003:
- - Hymod board database mods: add "who" field and new xilinx chip types
- - provide new "init_cmd_timeout()" function so code external to
- "common/main.c" can use the "reset_cmd_timeout()" function before
- entering the main loop
- - add DTT support for adm1021 (new file dtt/adm1021.c; config
- slightly different. see include/configs/hymod.h for an example
- (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and
- CFG_DTT_ADM1021 defined)
- - add new "eeprom_probe()" function which has similar args and
- behaves in a similar way to "eeprom_read()" etc.
- - add 8260 FCC ethernet loopback code (new "eth_loopback_test()"
- function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST)
- - gdbtools copyright update
- - ensure that set_msr() executes the "sync" and "isync" instructions
- after the "mtmsr" instruction in cpu/mpc8260/interrupts.c
- - 8260 I/O ports fix: Open Drain should be set last when configuring
- - add SIU IRQ defines for 8260
- - allow LDSCRIPT override and OBJCFLAGS initialization: change to
- config.mk to allow board configurations to override the GNU
- linker script, selected via the LDSCRIPT, make variable, and to
- give an initial value to the OBJCFLAGS make variable
- - 8260 i2c enhancement:
- o correctly extends the timeout depending on the size of all
- queued messages for both transmit and receive
- o will not continue with receive if transmit times out
- o ensures that the error callback is done for all queued tx
- and rx messages
- o correctly detects both tx and rx timeouts, only delivers one to
- the callback, and does not overwrite an earlier error
- o logic in i2c_probe now correct
- - add "vprintf()" function so that "panic()" function can be
- technically correct
- - many Hymod board changes
-
-* Patches by Robert Schwebel, 14 Jun 2003:
- - add support for Logotronic DL datalogger board
- - cleanup serial line after kermit binary download
- - add debugX macro (debug level support)
- - update mach-types.h to latest arm.linux.org.uk master list.
-
-* Patches by David Müller, 12 Jun 2003:
- - rewrite of the S3C24X0 register definitions stuff
- - "driver" for the built-in S3C24X0 RTC
-
-* Patches by Yuli Barcohen, 12 Jun 2003:
- - Add MII support and Ethernet PHY initialization for MPC8260ADS board
- - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
- configuration word supplied by FPGA on some MPC8260ADS boards
-
-* Patch by Pantelis Antoniou, 10 Jun 2003:
- Unify status LED interface
-
-* Add support for DS12887 RTC; add RTC support for ATC board
-
-* Patch by Nicolas Lacressonniere, 11 Jun 2003:
- Modifications for Atmel AT91RM9200DK ARM920T based development kit
- - Add Atmel DataFlash support for reading and writing.
- - Add possibility to boot a Linux from DataFlash with BOOTM command.
- - Add Flash detection on Atmel AT91RM9200DK
- (between Atmel AT49BV1614 and AT49BV1614A flashes)
- - Replace old Ethernet PHY layer functions
- - Change link address
-
-* Patch by Frank Smith, 9 Jun 2003:
- use CRIT_EXCEPTION for machine check on 4xx
-
-* Patch by Detlev Zundel, 13 Jun 2003:
- added implementation of the "carinfo" command in cmd_immap.c
-
-* Fix CONFIG_NET_MULTI support in include/net.h
-
-* Patches by Kyle Harris, 13 Mar 2003:
- - Add FAT partition support
- - Add command support for FAT
- - Add command support for MMC
- ----
- - Add Intel PXA support for video
- - Add Intel PXA support for MMC
- ----
- - Enable MMC and FAT for lubbock board
- - Other misc changes for lubbock board
-
-* Patch by Robert Schwebel, April 02, 2003:
- fix for SMSC91111 driver
-
-* Patch by Vladimir Gurevich, 04 Jun 2003:
- make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option
-
-* Patch by Stefan Roese, 05 Jun 2003:
- - PPC4xx: Fix bug for initial stack in data cache as pointed out by
- Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in
- data cache can be used even if the chip select is in use.
- - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count
- (see README for further description).
- - Changed config files of CONFIG_EEPRO100 boards to use the
- CFG_RX_ETH_BUFFER define.
-
-* Add support for RMU board
-
-* Add support for TQM862L at 100/50 MHz
-
-* Patch by Pantelis Antoniou, 02 Jun 2003:
- major reconstruction of networking code;
- add "ping" support (outgoing only!)
-
-* Patch by Denis Peter, 04 June 2003:
- add support for the MIP405T board
-
-* Patches by Udi Finkelstein, 2 June 2003:
- - Added support for custom keyboards, initialized by defining a
- board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
- - Added support for the RBC823 board.
- - cpu/mpc8xx/lcd.c now automatically calculates the
- Horizontal Pixel Count field.
-
-* Fix alignment problem in BOOTP (dhcp_leasetime option)
- [pointed out by Nicolas Lacressonnière, 2 Jun 2003]
-
-* Patch by Mark Rakes, 14 May 2003:
- add support for Intel e1000 gig cards.
-
-* Patch by Nye Liu, 3 Jun 2003:
- fix critical typo in MAMR definition (include/mpc8xx.h)
-
-* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
-
-* Patch by Klaus Heydeck, 2 Jun 2003
- Minor changes for KUP4K configuration
-
-* Patch by Marc Singer, 29 May 2003:
- Fixed rarp boot method for IA32 and other little-endian CPUs.
-
-* Patch by Marc Singer, 28 May 2003:
- Added port I/O commands.
-
-* Patch by Matthew McClintock, 28 May 2003
- - cpu/mpc824x/start.S: fix relocation code when booting from RAM
- - minor patches for utx8245
-
-* Patch by Daniel Engström, 28 May 2003:
- x86 update
-
-* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
- add nand flash support to SXNI855T configuration
- fix/extend nand flash support:
- - fix 'nand erase' command so does not erase bad blocks
- - fix 'nand write' command so does not write to bad blocks
- - fix nand_probe() so handles no flash detected properly
- - add doc/README.nand
- - add .jffs2 and .oob options to nand read/write
- - add 'nand bad' command to list bad blocks
- - add 'clean' option to 'nand erase' to write JFFS2 clean markers
- - make NAND read/write faster
-
-* Patch by Rune Torgersen, 23 May 2003:
- Update for MPC8266ADS board
-
-* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
- instead CFG_MONITOR_LEN is now only used to determine _at_compile_
- _time_ (!) if the environment is embedded within the U-Boot image,
- or in a separate flash sector.
-
-* Cleanup CFG_DER #defines in config files (wd maintained only)
-
-* Fix data abort exception handling for arm920t CPU
-
-* Fix alignment problems with flash driver for TRAB board
-
-* Patch by Donald White, 21 May 2003:
- fix calculation of base address in pci_hose_config_device()
-
-* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always
- execute "cmd2", even if "cmd1" fails. Note that this is different
- to "run var1 var2" where the contents of "var2" will NOT be
- executed when a command in "var1" fails.
-
-* Add zero-copy ramdisk support (requires corresponding kernel support!)
-
-* Patch by Kyle Harris, 20 May 2003:
- In preparation for an ixp port, rename cpu/xscale and arch-xscale
- into cpu/pxa and arch-pxa.
-
-* Patch by Stefan Roese, 23 May 2003:
- - IBM PPC405EP port added.
- - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not
- UART0) is used as default U-Boot console. PPC4xx only!
- - esd ASH405 board added (PPC405EP based).
- - BUBINGA405EP board added (PPC405EP based - IBM Eval Board).
- - esd CPCI405AB board added.
- - esd PMC405 board added.
- - Update of some esd boards.
-
-* Patch by Denis Peter, 19 Mai 2003:
- add support for the MIP405-3 board
-
-* Patch by Dave Ellis, 22 May 2003:
- Fix problem with only partially cleared .bss segment
-
-* Patch by Rune Torgersen, 12 May 2003:
- get PCI to work on a MPC8266ADS board; incorporate change to
- cpu/mpc8260/pci.c to enable overrides of PCI memory parameters
-
-* Patch by Nye Liu, 1 May 2003:
- minor patches for the FADS8xx
-
-* Patch by Thomas Schäfer, 28 Apr 2003:
- Fix SPD handling for 256 ECC DIMM on Walnut
-
-* Add support for arbitrary bitmaps for TRAB's VFD command;
- allow to pass boot bitmap addresses in environment variables;
- allow for zero boot delay
-
-* Patch by Christian Geißinger, 19 May 2002:
- On TRAB: wait until the dummy byte has been completely sent
-
-* Patch by David Updegraff, 22 Apr 2003:
- update for CrayL1 board
-
-* Patch by Pantelis Antoniou, 21 Apr 2003:
- add boot support for ARTOS (a proprietary OS)
-
-* Patch by Steven Scholz, 11 Apr 2003:
- Add support for RTC DS1338
-
-* Patch by Rod Boyce, 24 Jan 2003:
- Fix counting of extended partitions in diskboot command
-
-* Patch by Christophe Lindheimer, 20 May 2003:
- allow the use of CFG_LOADS when CFG_NO_FLASH is set
-
-* Fix SDRAM timing on Purple board
-
-* Add support for CompactFlash on ATC board
- (includes support for Intel 82365 and compatible PC Card controllers,
- and Yenta-compatible PCI-to-CardBus controllers)
-
-* Patch by Mathijs Haarman, 08 May 2003:
- Add lan91c96 driver (tested on Lubbock and custom PXA250 board only)
-
-* Fix problem with usage of "true" (undefined in current versions of bfd.h)
-
-* Add support for Promess ATC board
-
-* Patch by Keith Outwater, 28 Apr 2003:
- - Miscellaneous corrections and additions to GEN860T board specific code.
- - Added GEN860_SC variant to GEN860T.
- - Miscellaneous corrections to GEN860T documentation.
- - Correct duplicate entry in U-Boot CREDITS file.
- - Add GEN860T_SC entry in MAINTAINERS file.
- - Update CREDITS file with GEN860T_SC info.
-
-* Update Smiths Aerospace addresses in MAINTAINERS file
-
-* Fix error handling in hush's version of "run" command
-
-* LWMON extensions:
- - Splashscreen support
- - modem support
- - sysmon support
- - temperature dependend enabling of LCD
-
-* Allow booting from old "PPCBoot" disk partitions
-
-* Add support for TQM8255 Board / MPC8255 CPU
-
-======================================================================
-Changes for U-Boot 0.3.1:
-======================================================================
-
-* Make sure Block Lock Bits get cleared in R360MPI flash driver
-
-* MPC823 LCD driver: Fill color map backwards, to allow for steady
- display when Linux takes over
-
-* Patch by Erwin Rol, 27 Feb 2003:
- Add support for RTEMS (this time for real).
-
-* Add support for "bmp info" and "bmp display" commands to load
- bitmap images; this can be used (for example in a "preboot"
- command) to display a splash screen very quickly after poweron.
-
-* Add support for 133 MHz clock on INCA-IP board
-
-* Patch by Lutz Dennig, 10 Apr 2003:
- Update for R360MPI board
-
-* Add new meaning to "autostart" environment variable:
- If set to "no", a standalone image passed to the
- "bootm" command will be copied to the load address
- (and eventually uncompressed), but NOT be started.
- This can be used to load and uncompress arbitrary
- data.
-
-* Patch by Stefan Roese, 10 Apr 2003:
- Changed DHCP client to use IP address from server option field #54
- from the OFFER packet in the server option field #54 in the REQUEST
- packet. This fixes a problem using a Windows 2000 DHCP server,
- where the DHCP-server is not the TFTP-server.
-
-* Set max brightness for MN11236 displays on TRAB board
-
-* Add support for TQM862L modules
-
-======================================================================
-Changes for U-Boot 0.3.0:
-======================================================================
-
-* Patch by Arun Dharankar, 4 Apr 2003:
- Add IDMA example code (tested on 8260 only)
-
-* Add support for Purple Board (MIPS64 5Kc)
-
-* Add support for MIPS64 5Kc CPUs
-
-* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
-
-* Patch by Denis Peter, 04 Apr 2003:
- - update MIP405-4 board
-
-* Patch by Stefan Roese, 4 Apr 2003:
- - U-Boot version environment variable "ver" added
- (CONFIG_VERSION_VARIABLE).
- - Changed PPC405GPr version from A to B.
- - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.
-
-* Patches by Denis Peter, 03 April 2003:
- - fix PCI IRQs on MPL boards
- - fix two more un-relocated pointer problems
-
-* Fix behaviour of "run" command:
- - print error message iv variable does not exist
- - terminate processing of arguments in case of error
-
-* Patches by Peter Figuli, 10 Mar 2003
- - Add support for BTUART on PXA platform
- - Add support for WEP EP250 (PXA) board
-
-* Fix flash problems on INCA-IP; add tool to allow bruning images to
- flash using a BDI2000
-
-* Implement fix for I2C Edge Conditions problem for all boards that
- use the bit-banging driver (common/soft_i2c.c)
-
-* Patch by Martin Winistoerfer, 23 Mar 2003
- - Add port to MPC555/556 microcontrollers
- - Add support for cmi customer board with
- Intel 28F128J3A, 28F320J3A or 28F640J3A flash.
-
-* Patch by Rick Bronson, 28 Mar 2003:
- - fix common/cmd_nand.c
-
-* Patch by Arun Dharankar, 24 Mar 2003:
- - add threads / scheduler example code
-
-* Add patches by Robert Schwebel, 31 Mar 2003:
- - add ctrl-c support for kermit download
- - align bdinfo output on ARM
- - csb226 board: bring in sync with innokom/memsetup.S
- - csb226 board: fix MDREFR handling
- - misc doc fixes / extensions
- - innokom board: cleanup, MDREFR fix in memsetup.S, config update
- - add BOOT_PROGRESS to armlinux.c
-
-* Add CPU ID, version, and clock speed for INCA-IP
-
-* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
- - fix SRAM and SDRAM memory sizing
- - add status LED support
- - add MAC address for second (SCC1) ethernet port
-
-* Update default environment for TQM8260 board
-
-* Patch by Rick Bronson, 16 Mar 2003:
- - Add NAND flash support for reading, writing, and erasing NAND
- flash (certain forms of which are called SmartMedia).
- - Add support for Atmel AT91RM9200DK ARM920T based development kit.
-
-* Patches by Robert Schwebel, 19 Mar 2003:
- - use arm-linux-gcc as default compiler for ARM
- - fix i2c fixup code
- - fix missing baudrate setting
- - added $loadaddr / CFG_LOAD_ADDR support to loadb
- - moved "ignoring trailing characters" _before_ u-boot wants to
- print out diagnostics messages; removes bogus characters at the
- end of transmission
-
-* Patch by John Zhan, 18 Mar 2003:
- Add support for SinoVee Microsystems SC8xx boards
-
-* Patch by Rolf Offermanns, 21 Mar 2003:
- ported the dnp1110 related changes from the current armboot cvs to
- current u-boot cvs. smc91111 does not work. problem marked in
- smc91111.c, grep for "FIXME".
-
-* Patch by Brian Auld, 25 Mar 2003:
- Add support for STM flash chips on ebony board
-
-* Add PCI support for MPC8250 Boards (PM825 module)
-
-* Patch by Stefan Roese, 25 Mar 2003:
- - PCI405 update.
-
-* Patch by Stefan Roese, 20 Mar 2003:
- - CPCI4052 update (support for revision 3).
- - Set edge conditioning circuitry on PPC405GPr for compatibility
- to existing PPC405GP designs.
- - Clip udiv to 5 bits on PPC405 (serial.c).
-
-* Extend INCAIP board support:
- - add automatic RAM size detection
- - add "bdinfo" command
- - pass flash address and size to Linux kernel
- - switch to 150 MHz clock
-
-* Avoid flicker on the TRAB's VFD by synchronizing the enable with
- the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100
- boards, version 153 for Rev. 200 boards).
-
-* Patch by Vladimir Gurevich, 12 Mar 2003:
- Fix relocation problem of statically initialized string pointers
- in common/cmd_pci.c
-
-* Patch by Kai-Uwe Blöm, 12 Mar 2003:
- Cleanup & bug fixes for JFFS2 code:
- - the memory mangement was broken. It caused havoc on malloc by
- writing beyond the block boundaries.
- - the length calculation for files was wrong, sometimes resulting
- in short file reads.
- - data copying now optionally takes fragment version numbers into
- account, to avoid copying from older data.
- See doc/README.JFFS2 for details.
-
-* Patch by Josef Wagner, 12 Mar 2003:
- - 16/32 MB and 50/80 MHz support with auto-detection for IP860
- - ETH05 and BEDBUG support for CU824
- - added support for MicroSys CPC45
- - new BOOTROM/FLASH0 and DOC base for PM826
-
-* Patch by Robert Schwebel, 12 Mar 2003:
- Fix the chpart command on innokom board
-
-* Name cleanup:
- mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h
- s/PPCBoot/U-Boot/ in some files
- s/pImage/uImage/ in some files
-
-* Patch by Detlev Zundel, 15 Jan 2003:
- Fix '' command line quoting
-
-* Patch by The LEOX team, 19 Jan 2003:
- - add support for the ELPT860 board
- - add support for Dallas ds164x RTC
-
-* Patches by David Müller, 31 Jan 2003:
- - minimal setup for CardBus bridges
- - add EEPROM read/write support in the CS8900 driver
- - add support for the builtin I2C controller in the Samsung s3c24x0 chips
- - add support for MPL's VCMA9 (Samsung s3c2410 based) board
-
-* Patch by Steven Scholz, 04 Feb 2003:
- add support for RTC DS1307
-
-* Patch by Reinhard Meyer, 5 Feb 2003:
- fix PLPRCR/SCCR init sequence on 8xx to allow for
- changes of EBDF by software
-
-* Patch by Vladimir Gurevich, 07 Feb 2003:
- "API-compatibility patch" for 4xx I2C driver
-
-* TRAB fixes / extensions:
- - Restore VFD brightness as saved in environment
- - add support for Fujitsu flashes
- - make sure both buzzers are turned off (drive low level)
-
-* Patches by Robert Schwebel, 06 Mar 2003:
- - fix bug in BOOTP code (must use NetCopyIP)
- - update of CSB226 port
- - clear BSS segment on XScale
- - added support for i2c_init_board() function
- - update to the Innokom plattform
-
-* Extend support for redundand environments for configurations where
- environment size < sector size
-
-* Patch by Rune Torgersen, 13 Feb 2003:
- Add support for Motorola MPC8266ADS board
-
-* Patch by Kyle Harris, 19 Feb 2003:
- patches for the Intel lubbock board:
- memsetup.S - general cleanup (based on Robert's csb226 code)
- flash.c - overhaul, actually works now
- lubbock.c - fix init funcs to return proper value
-
-* Patch by Kenneth Johansson, 26 Feb 2003:
- - Fixed off by one in RFTA calculation.
- - No need to abort when LDF is lower than we can program it's only
- minimum timing so clamp it to what we can do.
- - Takes function pointer to function for reading the spd_nvram. Usefull
- for faking data or hardcode a module without the nvram.
- - fix other user for above change
- - fix some comments.
-
-* Patches by Brian Waite, 26 Feb 2003:
- - fix port for evb64260 board
- - fix PCI for evb64260 board
- - fix PCI scan
-
-* Patch by Reinhard Meyer, 1 Mar 2003:
- Add support for EMK TOP860 Module
-
-* Patch by Yuli Barcohen, 02 Mar 2003:
- Add SPD EEPROM support for MPC8260ADS board
-
-* Patch by Robert Schwebel, 21 Jan 2003:
- - Add support for Innokom board
- - Don't complain if "install" fails
- - README cleanup (remove duplicated lines)
- - Update PXA header files
-
-* Add documentation for existing POST code (doc/README.POST)
-
-* Patch by Laudney Ren, 15 Jan 2003:
- Fix handling of redundand environment in "tools/envcrc.c"
-
-* Patch by Detlev Zundel, 28 Feb 2003:
- Add bedbug support for 824x systems
-
-* Add support for 16 MB flash configuration of TRAB board
-
-* Patch by Erwin Rol, 27 Feb 2003:
- Add support for RTEMS
-
-* Add image information to README
-
-* Patch by Stefan Roese, 18 Feb 2003:
- CPCIISER4 configuration updated.
-
-* Patch by Stefan Roese, 17 Feb 2003:
- Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).
-
-* Patch by Stefan Roese, 13 Feb 2003:
- Add "pcidelay" environment variable (in ms, enabled via
- CONFIG_PCI_BOOTDELAY).
- PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after
- RST# to respond to configuration cycles (33MHz -> 1s).
-
-* Fix dual PCMCIA slot support (when running with just one
- slot populated)
-
-* Add VFD type detection to trab board
-
-* extend drivers/cs8900.c driver to synchronize ethaddr environment
- variable with value in the EEPROM
-
-* Patch by Stefan Roese, 10 Feb 2003:
- Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c)
-
-* Add support for MIPS32 4Kc CPUs
-
-* Add support for INCA-IP Board
-
-======================================================================
-Changes for U-Boot 0.2.2:
-======================================================================
-
-* Add dual ethernet support on PM826
-
-* Add support for LXT971 PHY on PM826
-
-* Patch by Tord Andersson, 16 Jan 2003:
- Fix flash sector count for TQM8xxL
-
-* Fix I2C EEPROM problem on ICU862 board (would only write the first
- 16 bytes out of each 32 byte block)
-
-======================================================================
-Changes for U-Boot 0.2.1:
-======================================================================
-
-* Add support for V37 board
- (patch by Jón Benediktsson, 11 Dec 2002)
-
-* Update baudrate in bd_info when it gets changed
-
-* Add watchdog trigger points while waiting for serial port
- (so far only 8xx -- needed on LWMON with 100ms watchdog)
-
-* Improve command line tool to access the U-Boot's environment
- (figuration of the utility, using a config file)
-
-* Add single quote support for (old) command line parser
-
-* Switch LWMON board default config from FRAM to EEPROM;
- in POST, EEPROM shows up on 8 addresses
-
-======================================================================
-Changes for U-Boot 0.2.0:
-======================================================================
-
-* Use 1-byte-read instead of -write for iprobe() function
- Add i2c commands to PM826 config
-
-* extend I2C POST code: check for list on known addresses
-
-* Improve log buffer code; use "loglevel" to decide which messages
- to log on the console, too (like in Linux); get rid of "logstart"
-
-* Add command line tool to access the U-Boot's environment
- (board-specific for TRAB now, to be fixed later)
-
-* Patch by Hans-Joerg Frieden, 06 Dec 2002
- Fix misc problems with AmigaOne support
-
-* Patch by Chris Hallinan, 3 Dec 2002:
- minor cleanup to the MPC8245 EPIC driver
-
-* Patch by Pierre Aubert , 28 Nov 2002
- Add support for external (SIU) interrupts on MPC8xx
-
-* Patch by Pierre Aubert , 28 Nov 2002
- Fix nested syscalls bug in standalone applications
-
-* Patch by David Müller, 27 Nov 2002:
- fix output of "pciinfo" command for CardBus bridge devices.
-
-* Fix bug in TQM8260 board detection - boards got stuck when board ID
- was not readable
-
-* Add LED indication for IDE activity on KUP4K board
-
-* Fix startup problems with VFD display on TRAB
-
-* Patch by Pierre Aubert, 20 Nov 2002
- Add driver for Epson SED13806 graphic controller.
- Add support for BMP logos in cfb_console driver.
-
-* Added support for both PCMCIA slots (at the same time!) on MPC8xx
-
-* Patch by Rod Boyce, 21 Nov 2002:
- fix PCMCIA on MBX8xx board
-
-* Patch by Pierre Aubert , 21 Nov 2002
- Add CFG_CPM_POST_WORD_ADDR to make the offset of the
- bootmode word in DPRAM configurable
-
-* Patch by Daniel Engström, 18 Nov 2002:
- Fixes for x86 port (mostly strings issues)
-
-* Patch by Ken Chou, 18 Nov 2002:
- Fix for natsemi NIC cards (DP83815)
-
-* Patch by Pierre Aubert, 19 Nov 2002:
- fix a bug for the MII configuration, and some warnings
-
-* Patch by Thomas Frieden, 13 Nov 2002:
- Add code for AmigaOne board
- (preliminary merge to U-Boot, still WIP)
-
-* Patch by Jon Diekema, 12 Nov 2002:
- - Adding URL for IEEE OUI lookup
- - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED
- being defined.
- - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and
- root-on-nfs macros are designed to switch how the default boot
- method gets defined.
-
-* Patch by Daniel Engström, 13 Nov 2002:
- Add support for i386 architecture and AMD SC520 board
-
-* Patch by Pierre Aubert, 12 Nov 2002:
- Add support for DOS filesystem and booting from DOS floppy disk
-
-* Patch by Jim Sandoz, 07 Nov 2002:
- Increase number of network RX buffers (PKTBUFSRX in
- "include/net.h") for EEPRO100 based boards (especially SP8240)
- which showed "Receiver is not ready" errors when U-Boot was
- processing the receive buffers slower than the network controller
- was filling them.
-
-* Patch by Andreas Oberritter, 09 Nov 2002:
- Change behaviour of NetLoop(): return -1 for errors, filesize
- otherwise; return code 0 is valid an means no file loaded - in this
- case the environment still gets updated!
-
-* Patches by Jon Diekema, 9 Nov 2002:
- - improve ADC/DAC clocking on the SACSng board to align
- the failing edges of LRCLK and SCLK
- - sbc8260 configuration tweaks
- - add status LED support for 82xx systems
- - wire sspi/sspo commands into command handler; improved error
- handlering
- - add timestamp support and alternate memory test to the
- SACSng configuration
-
-* Patch by Vince Husovsky, 7 Nov 2002:
- Add "-n" to linker options to get rid of "Not enough room for
- program headers" problem
-
-* Patch by David Müller, 05 Nov 2002
- Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
- so we can use an already existing name
-
-* Patch by Pierre Aubert, 05 Nov 2002
- Hardware relatied improvments in FDC boot code
-
-* Patch by Holger Schurig, 5 Nov 2002:
- Make the PXA really change it's frequency
-
-* Patch by Pierre Aubert, 05 Nov 2002
- Add support for slave serial Spartan 2 FPGAs
-
-* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
- drivers
-
-* Add support for log buffer which can be passed to Linux kernel's
- syslog mechanism; used especially for POST results.
-
-* Patch by Klaus Heydeck, 31 Oct 2002:
- Add initial support for kup4k board
-
-* Patch by Robert Schwebel, 04 Nov 2002:
- - use watchdog to reset PXA250 systems
- - added progress callbacks to (some of the) ARM code
- - update for Cogent CSB226 board
-
-* Add support for FPS860 board
-
-* Patch by Guillaume Alexandre,, 04 Nov 2002:
- Improve PCI access on 32-bits Compact PCI bus
-
-* Fix mdelay() on TRAB - this was still the debugging version with
- seconds instead of ms.
-
-* Patch by Robert Schwebel, 1 Nov 2002:
- XScale related cleanup (affects all ARM boards)
-
-* Cleanup of names and README.
-
-======================================================================
-Notes for U-Boot 0.1.0:
-======================================================================
-
-This is the initial version of "Das U-Boot", the Universal Boot Loader.
-
-It is based on version 2.0.0 (the "Halloween Release") of PPCBoot.
-For information about the history of the project please see the
-PPCBoot project page at http://sourceforge.net/projects/ppcboot
-
-======================================================================
+ Initial support for MPC8641 HPCN board.
--- /dev/null
+======================================================================
+Changes for U-Boot 1.1.5:
+======================================================================
+
+* Cleanup compile warnings. Prepare for release 1.1.5
+
+* Fix compile problem in include/configs/ep82xxm.h
+ (must have never been tested before!)
+
+* MCC200: Fix uninitialized variable problem in LCD driver
+
+* Add board/cpu specific NAND chip select function to 440 NDFC
+ Based on idea and implementation from Jeff Mann
+ Patch by Stefan Roese, 20 Oct 2006
+
+* Make 4xx bootup message shorter on 440EPx/GRx platforms
+ Patch by Stefan Roese, 18 Oct 2006
+
+* Add (preliminary) support for V38B board
+
+* PPC405EP: Add support for board configuration of CPC0_PCI register
+ This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
+ Patch by Tolunay Orkun, 07 Apr 2006
+
+* PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
+ - Add configuration of Open Drain GPIO Output selection
+ - Add configuration of initial value of GPIO output pins
+ Patch by Tolunay Orkun, 07 Apr 2006
+
+* Fix spelling; minor code cleanup.
+
+* Fix JFFS2 compilation problem
+ Patch by Stefan Roese, 12 Oct 2006
+
+* Cleanup of NAND update patch (remove changelog from cmd_nand.c)
+ Patch by Guido Classen, 10 Oct 2006
+
+* Several improvements to the new NAND subsystem:
+ - JFFS2 related commands implemented in mtd-utils style
+ - Support for bad blocks
+ - Bad block testing commands
+ - NAND lock commands
+ Please take a look at doc/README.nand for more details
+ Patch by Guido Classen, 10 Oct 2006
+
+* Define IH_CPU_AVR32
+ Make it possible to generate AVR32 uImage files with mkimage and
+ make cmd_bootm recognize them.
+ Patch by Haavard Skinnemoen, 22 Sep 2006
+
+* Fix buffer overflow problem in ft_build.c
+ Patch by Fredrik Roubert, 09 Oct 2006
+
+* Make bootp implementation RFC3046 compliant
+ Patch by Joakim Larsson, 27 Jun 2006
+
+* TQM5200: perform POST memory test only on STK52xx carrier board.
+ (and then only if PSC6_3 is read as "1" when booting).
+ Patch by Martin Krause, 21 Jun 2006
+
+* Move "ar" flags to config.mk to allow for silent "make -s"
+ Based on patch by Mike Frysinger, 20 Jun 2006
+
+* Coding style cleanup
+
+* Add support for EP82xxM boards
+ Patch by Aaron Sells, 20 Jun 2006
+
+* Fix comments in include/ppc440.h
+ Patch by Martin Hicks, 16 Jun 2006
+
+* Update for CAM5200 board:
+ - Map in a additional chip selects CS4 and CS5.
+ - Modify the port configration, configure six UARTs and no PCI,
+ ATA and USB.
+ - Add custom flash driver to handle specific byte swapping
+
+* Fix TLB setup for Ocotea board
+ Patch by Stefan Roese, 30 Sep 2006
+
+* Fix reset problem in sequoia sdram init code
+ Patch by Stefan Roese, 23 Sep 2006
+
+* Disable autoboot abort for FO300 when silent mode is enabled
+ (according to S1 switch setting).
+
+* Cleanup examples binaries
+
+* Add support for AMCC Rainier PPX440GRx eval board
+ Patch by Stefan Roese, 13 Sep 2006
+
+* Add NAND environment support for PPC440EPx Sequoia NAND boot config
+ Patch by Stefan Roese, 12 Sep 2006
+
+* Update NAND boot documentation
+ Patch by Stefan Roese, 12 Sep 2006
+
+* Fix alignment problem in "mtdparts" command
+
+* Add documentation on the latest build environment extensions to
+ the README file.
+
+* Remove dead code (i2o and dma) from cpu/mpc824x/drivers/ directory.
+
+* Fix LOG_DIR directory creation error.
+ Add support for automatic creation of BUILD_DIR directory.
+
+* Fix build problem cpu/ppc4xx/ndfc.c
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Fix build problem with CPCI440
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Change Yellowstone to use CFI write buffer
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Add support for AMCC Sequoia PPC440EPx eval board
+ - Add support for PPC440EPx & PPC440GRx
+ - Add support for PPC440EP(x)/GR(x) NAND controller
+ in cpu/ppc4xx directory
+ - Add NAND boot functionality for Sequoia board,
+ please see doc/README.nand-boot-ppc440 for details
+ - This Sequoia NAND image doesn't support environment
+ in NAND for now. This will be added in a short while.
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Fix mkimage -l bug with multifile images on 64bit platforms
+ Patch by David Updegraff, 06 Sep 2006
+
+* Fix build problems on sorcery board.
+
+* Fix coldfire build problems.
+ Patch by Marian Balakowicz, 01 Sep 2006
+
+* Add support for a saving build objects in a separate directory.
+ Modifications are based on the Linux kernel approach and support
+ two use cases:
+ 1) Add O= to the make command line 'make O=/tmp/build all'
+ 2) Set environement variable BUILD_DIR to point to the desired location
+ 'export BUILD_DIR=/tmp/build'
+ 'make'
+ The second approach can also be used with a MAKEALL script
+ 'export BUILD_DIR=/tmp/build'
+ './MAKEALL'
+ Command line 'O=' setting overrides the BUILD_DIR environent variable.
+ When none of the above methods is used the local build is performed
+ and the object files are placed in the source directory.
+
+* Remove the board/netstar/crcit binary from git repository.
+
+* Fix tools/updater build error.
+
+* Fix tools/easylogo build error.
+
+* Fixed problems on PRS200 board caused by adding splash screen on MCC200
+
+* Extended README entry on coding style
+
+* Added another example showing simple interrupt interception.
+
+* Added simple_strtoul(), getenv() and setenv() to the exported functions.
+ Also bumped up ABI version to reflect this change.
+
+* Added interrupt handling capabilities for mpc5xxx processors.
+ Also added Linux like BUG() macros.
+
+* Coding Style cleanup.
+ Patch by Stefano Babic, 31 Aug 2006
+
+* Add splashscreen support for MCC200 board.
+
+* Make the serial driver framework work with CONFIG_SERIAL_MULTI
+ enabled
+
+* PCIe endpoint support for AMCC Yucca 440SPe board
+ Patch by Tirumala R Marri, 26 Aug 2006
+
+* Improve DIMM detection for AMCC Yucca 440SPe board
+ Improved the memory DIMM detection for the Yucca 440SPe board for
+ the case where a memory DIMM is falsely detected as present.
+ This issue is seen on some AMCC Yucca 440SPe validation boards if
+ only one 512MB memory DIMM is installed, i.e. DIMM slot 0 is
+ populated and DIMM slot 1 is empty. In this case, U-Boot does
+ not correctly detect that there is only one DIMM memory module
+ installed and will falsely detect two DIMM memory modules are
+ present and therefore U-Boot will not calculate the correct amount
+ of total memory and u-boot will not booting up.
+ Patch by Adam Graham, 24 Aug 2006
+
+* Fix typo.
+
+* Code cleanup
+
+* Update for MCC200 / PRS200 boards:
+ - auto-adjust console device for Linux.
+ - fix typos.
+
+* Add a fix for a buggy USB device on the FO300 board.
+
+* Updates for MCC200 / PRS200 boards:
+ - support for configurations with SDRAM or DDR memory,
+ - support for highboot and lowboot
+ - adjusting environment definitions
+
+* Add support for WTK FO300 board (TQM5200 based).
+
+* Fix TQM834x hang.
+
+* Update for SC520 board.
+ Patch by David Updegraff, 02 Dec 2005
+
+* Fixed common.h spelling error.
+ Patch by Cory Tusar, 30 Nov 2005
+
+* Fix typo.
+ Patch by Andreas Engel, 28 Nov 2005
+
+* Fix fatload command on FAT32 formatted partitions.
+ Patch by Joachim Jaeger, 18 Nov 2005
+
+* Fix drivers/dm9000.c when configured in 32 bit mode.
+ Patch by Eric Benard, 17 Nov 2005
+
+* Cleanup debug code for yucca board.
+
+* MCC200: restrict addressable flash space to 32 MB
+
+* Add debug console on COM12 for MCC200 board
+
+* Fix control-c handing in CONFIG_CMDLINE_EDITING
+ Properly pass break code back from readline.
+ Patch by Roger Blofeld, 31 Jul 2006
+
+* Add commandline history support to all AMCC eval boards
+ Patch by Stefan Roese, 07 Aug 2006
+
+* Add Macronix MXLV320T flash support for AMCC Bamboo
+ Patch by Stefan Roese, 07 Aug 2006
+
+* Change "mii info" to not print an error upon missing PHY at address
+ Patch by Stefan Roese, 07 Aug 2006
+
+* Fix PCI-Express on PPC440SPe rev. A.
+
+* Fix preboot message on TQM85xx after switching to hush parser.
+
+* Adapt TQM85xx ramdisk address to Linux kernel memory map
+
+* Add initial support for PCI-Express on PPC440SPe (Yucca board).
+
+* Fix compiler warning for TRAB board.
+ Patch by Martin Krause, 07 Aug 2006
+
+* Prevent USB commands from working when USB is stopped.
+
+* Add rudimentary handling of alternate settings of USB interfaces.
+ This is in order to fix issues with some USB sticks timing out
+ during initialization. Some code readability improvements.
+
+* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
+ AMCC suggested to set the PMU bit to 0 for best performace on
+ the PPC440 DDR controller.
+ Please see doc/README.440-DDR-performance for details.
+ Patch by Stefan Roese, 28 Jul 2006
+
+* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
+ Please see doc/README.bamboo for details.
+ Patch by Stefan Roese, 27 Jul 2006
+
+* Fix CONFIG_CMDLINE_EDITING implementation
+ Patch by Stefan Roese, 27 Jul 2006
+
+* Fix preboot message on TQM5200 after switching to hush parser.
+
+* MCC200: set default configuration to low_boot DDR,
+ and support for configurable options high_boot and/or SDRAM.
+
+* Add support for 256 MB SDRAM on CPU87
+ Patch by Josef Wagner, 25 Nov 2005
+
+* Add configuration for cam5200 board (based on TQM5200S).
+
+* More code cleanup
+
+* Disabled kvme080 board in MAKEALL because of build problems.
+
+* Code cleanup
+
+* Update NetStar board
+ Patch by Ladislav Michl, 03 Nov 2005
+
+* Make code better readable.
+ Patch by Ladislav Michl, 14 Sep 2005
+
+* Enable initrd ATAG for xm250 board.
+ Patch by Josef Wagner, 05 Sep 2005
+
+* Add readline cmdline-editing extension
+ Patch by JinHua Luo, 01 Sep 2005
+
+* Add support for friendly-arm SBC-2410X board
+ Patch by JinHua Luo, 01 Sep 2005
+
+* Fix multi-part image support on i386 platform.
+ Patch by David Updegraff, 19 Aug 2005
+
+* Add support for KVME080 board
+ Patch by Sangmoon Kim, 18 Aug 2005
+
+* Fix MIPS LE build problem
+ Patch by Matej Kupljen, 10 Aug 2005
+
+* Check argument count in "mii" command.
+ Problem pointed out by Andrew Dyer, 13 Jun 2005
+
+* Cleanup TQM5200 board configurations:
+ - make highboot configurations use environment at high end, too,
+ to avoid flash fragmentation
+ - always use redundand environment
+ - don't enable video code for modules without graphics controller
+ - provide useful (though different) mtdparts settings
+ - get rid of CONFIG_CS_AUTOCONF which was always set anyway
+
+* Extend mkconfig tool to print more useful target name
+
+* Add support for high-boot on TQM5200 and TQM5200S boards.
+ Hint: the CPLD on the TQM5200 must be programmed with a software
+ version supporting the high boot option! The new TQM5200S is
+ already supporting this option. On the TQM5200 this option will be
+ supported in configurations with MPC5200 rev B processors.
+ To actually "high boot", set jumper X30 on the STK52xx.
+ Patch by Martin Krause, 12 Jul 2006
+
+* Add support for new TQM5200 revisions
+ - Support for TQM5200S (short version without graphic controller)
+ - Support for modules with 'N' type S29GL128N Spansion flashes
+ (requires changes to flash layout)
+ - Support for MPC5200B cpu (mostly support for second SDRAM bank)
+ Patch by Martin Krause, 07 Jul 2006
+
+* Fix support for PS/2 keyboard on TQM85xx boards
+ The PS/2 keyobard driver for the TQM85xx modules only supports the
+ internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
+ include a DUART, the TQM8560 modules can't be used with the PS/2
+ keyboard controller on the STK85xx board.
+ The PS/2 keyboard driver should work with the modules TQM8540,
+ TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
+ Make sure the PS/2 controller on the STK85xx is programmed. Jumper
+ settings: X66 1-2, 9-10; X61 2-3
+ Patch by Martin Krause, 21 Jun 2006
+
+* Adjust RTC century handling on STK52xx board to match Linux driver.
+ Patch by Martin Krause, 12 Jun 2006
+
+* Adjust filenames for USB update images on TRAB board.
+ During an automatic update via USB stick, U-Boot searches for
+ images with the name "firmware.img" and "kernel.img". This names
+ are now changed to "firmw_01.img" and "kernl_01.img". This is done,
+ to prevent updates of new boards (with the new macronics "c" step
+ flashes) with old, incompatible firmware or kernel versions.
+ Patch by Martin Krause, 21 Jun 2006
+
+* Bugfix in VFD routine on TRAB board.
+ Make sure upper lext pixel can be set to blue, too
+ (so far only red was possible).
+ Patch by Martin Krause, 15 Feb 2006
+
+* Enable buffered flash writes for TB5200 board.
+
+* Fix some bugs in TRAB board flash driver.
+ - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
+ - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
+ - remove "Unlock Bypass" mode, because macronix flashes do not support
+ this mode officially
+ - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
+ for Intel compatible flashes, not for AMD compatible.
+ Patch by Martin Krause, 15 Feb 2006
+
+* Add additional error messages to flash driver on TRAB board
+ (for erase errors and timeout errors)
+ Patch by Martin Krause, 14 Feb 2006
+
+* Add support for TB5200 board
+ The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
+ integrated in a little aluminium case.
+ Patch by Martin Krause, 8 Jun 2006
+
+* Enable buffered flash writes for TQM5200 board.
+
+* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
+
+* Add support for TQM885D board.
+ Patch by Martin Krause, 20 Mar 2006
+
+* Fix FEC initialisation: All MII configuration is done via FEC1
+ registers, but MII_SPEED was configured according to FEC used. So
+ if only FEC2 was used, this caused the real MII_SPEED register in
+ FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages.
+ Fix: always configure MII_SPEED on FEC1 only.
+ Patch by Markus Klotzbuecher, 12 Jul 2006
+
+* Add support for SPC1920 board.
+ Patch by Markus Klotzbuecher, 12 Jul 2006
+
+* MCC200 board: support console on any one of the Quad UART ports.
+
+* Fix error in flash protection calculation on MCC200 board.
+
+* Major PCMCIA Cleanup to make code better readable and maintainable.
+ Notes:
+ - Board-dependend code for RPXLITE and RPXCLASSIC-based boards
+ placed to the drivers/rpx_pmcia.c file to avoid duplication.
+ Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
+ - drivers/i82365.c has been split into two parts located at
+ board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
+ the only boards using CONFIG_82365).
+ - Changes were tested for clean build and *very* *few* boards.
+
+* Fix timer problems on AMCC yucca board.
+ Set Timer Clock Select to use CPU clock as a timer input source.
+
+* Bring yucca config more in line with other AMCC boards.
+
+* Add AMCC bamboo board to MAKEALL build script.
+
+* Fix AMCC bamboo eval board compilation errors.
+
+* Add system memory to the PCI region list for AMCC PPC44x CPUs.
+ Enabled it for Yucca board.
+
+* Cleanup config file and bootup output for Yucca board.
+
+* Fix CONFIG_440_GX define usage.
+
+* Remove autogenerated bmp_logo.h file.
+
+* Add support for AMCC 440SPe CPU based eval board (Yucca).
+
+* Call serial_initialize() before first debug() is used.
+
+* Cleanup trab board for GCC-4.x
+
+* VoiceBlue update: use new MTD flash partitioning methods, use more
+ reasonable TEXT_BASE, update default environment and enable keyed
+ autoboot.
+ Patch by Ladislav Michl, 16. Aug 2005
+
+* Add forgotten changes for the PLEB 2 Board.
+ Patch by David Snowdon, 13. Aug 2005
+
+* Add support for wrPPMC7xx/74xx boards
+ Patch by Richard Danter, 12 Aug 2005
+
+* Add support for gth2 board
+ Patch by Thomas Lange, Aug 11 2005
+
+* Add support for CONFIG_SERIAL_MULTI on MPC5xxx
+ Patch by Martin Krause, 8 Jun 2006
+
+ This patch supports two serial consoles on boards with
+ a MPC5xxx CPU. The console can be switched at runtime
+ by setting stdin, stdout and stderr to the desired serial
+ interface (serial0 or serial1). The PSCs to be used as
+ console port are definded by CONFIG_PSC_CONSOLE
+ and CONFIG_PSC_CONSOLE2.
+ See README.serial_multi for details.
+
+* Bugfix in I2C initialisation on S3C2400.
+ If the bus is blocked because of a previously interrupted
+ transfer, up to eleven clocks are generated on the I2CSCL
+ line to complete the transfer and to free the bus.
+ With this fix pin I2CSCL (PG6) is really configured as GPIO
+ so the clock pulses are really generated.
+ Patch by Martin Krause, 04 Apr 2006
+
+* Fix DDR6 errata on TQM834x boards
+ Patch by Thomas Waehner, 07 Mar 2006
+
+* Remove obsolete flash driver board/tqm5200/flash.c
+ Patch by Martin Krause, 11 Jan 2006
+
+* Update configuration for CMC-PU2 board
+ Patch by Martin Krause, 17 Nov 2005
+
+* Add support for PS/2 keyboard on TQM85xx board
+ Patch by Martin Krause, 07 Nov 2005
+
+ Tested on a STK85XX baseboard. Make sure the PS/2 controller
+ has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
+
+* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
+ In tsc2000_read_channel() the delay after setting the multiplexer
+ to a temperature channel is increased from 1,5 ms to 10 ms. This
+ is to allow the multiplexer inputs to stabilize after huge steps
+ of the input signal level.
+ Patch by Martin Krause, 08 Nov 2005
+
+* Adjust TQM5200 make targets
+ Make the automatic CS configuration the default.
+ The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
+ and CONFIG_TQM5200_AC are removed.
+ "TQM5200_config" is now the default for STK52XX.200 base boards.
+ On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
+ Patch by Martin Krause, 07 Nov 2005
+
+* Fix setting of environment variable "ver" on trab board
+ The environment variable "ver" is now set before
+ do_auto_update() is called, so that "ver" can be used
+ in USB update scripts.
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix wrong usage of udelay() in led_blink() on trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix udelay bug in vfd.c for trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Disable JFFS2 support for trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Change mtdparts definition on trab board to match current flash map
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix memory init problems on MCC200 board
+
+* Fix IxEthDB.h to compile again
+ Patch by Stefan Roese, 14 Jun 2006
+
+* Minor cleanup for PCS440EP board
+ Patch by Stefan Roese, 13 Jun 2006
+
+* Add MCF5282 support (without preloader)
+ relocate ichache_State to ram
+ u-boot can run from internal flash
+ Add EB+MCF-EV123 board support.
+ Add m68k Boards to MAKEALL
+ Patch from Jens Scharsig, 08 Aug 2005
+
+* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Add EPCS Controller bootrom work-around
+ -When booting from an epcs controller, the epcs bootrom may leave the
+ slave select in an asserted state causing soft reset hang. This
+ patch ensures slave select is negated at reset.
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Update PK1C20 board
+ -Update base addresses for standard configuration
+ -Eliminate use of CACHE_BYPASS in board code
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Fix I/O Macros and mini-app stubs
+ -Fix asm/io.h macros
+ -Eliminate use of CACHE_BYPASS in cpu code
+ -Eliminate assembler warnings
+ -Fix mini-app stubs and force no small data
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Fix U-Boot environment sector protection on MCC200 board
+
+* Minor cleanup for PCS440EP board
+
+* Update PCS440EP port to fit into one flash device (incl. environment)
+ Patch by Stefan Roese, 06 Jun 2006
+
+* Add support for PCS440EP board
+ Patch by Stefan Roese, 02 Jun 2006
+
+* Fix examples/Makefile; some build targets were lost
+
+* Fix watchdog handling in CFI flash driver
+ Just use udelay() when waiting for status changes which will
+ implicitely trigger the watchdog.
+
+* Fix PCI to memory window size problems on PM82x boards
+ We use the "automatic" mode that was used for the MPC8266ADS and
+ MPC8272 boards. Eventually this should be used on all boards?]
+ Patch by Wolfgang Grandegger, 17 Jan 2006
+
+* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
+ Patch by Stefan Roese, 29 May 2006
+
+* Update Intel IXP4xx support
+ - Add IXP4xx NPE ethernet MAC support
+ - Add support for Intel IXDPG425 board
+ - Add support for Prodrive PDNB3 board
+ - Add IRQ support
+ Patch by Stefan Roese, 23 May 2006
+
+* Fix problem in PVR detection for 440GR
+ Patch by Stefan Roese, 18 May 2006
+
+* Fix gcc 3.4.x AFLAGS setting for m68k platform.
+
+* Enable autoboot for M5271EVB board.
+
+* Changed default ramdisk addr in yosemite/yellowstone ports
+ Patch by Stefan Roese, 15 May 2006
+
+* Fix PCMCIA support on virtlab2
+
+* Add support for VirtLab2 board
+ (needed because of differences in the PCMCIA hardware).
+
+* Minor cleanup.
+
+* Update yosemite configuration to enable flash write buffer support
+ Patch by Stefan Roese, 10 May 2006
+
+* Fix compile warnings in common/xyzModem.c
+ Patch by Stefan Roese, 10 May 2006
+
+* Add support for AMCC 440EP Rev C and 440GR Rev B
+ Patch by John Otken, 08 May 2006
+
+* OMAP 5912/OSK: update EMIFS CS1 timings:
+ Problems have been seen in the linux kernel's smc91x network driver
+ due to improper bus timings. The latest 2.6 OMAP kernels currently
+ have a workaround, but this fix belongs in u-boot.
+ Patch by Kevin Hilman, 13 Oct 2005
+
+* Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports
+ Patch by Hiroki Kaminaga, 11 Mar 2006
+
+* Update omap5912osk board support
+ - Fix OMAP support that omap5912osk compiles in current source tree
+ - Update with code from "http://omap.spectrumdigital.com/osk5912"
+ to fix problems with DDR initialization
+ - Fix timer setup
+ - Use CFI flash driver and support complete 32MB of onboard flash
+ - Add "print_cpuinfo()" and "checkboard()" functions to display
+ CPU (with frequency) and Board infos
+ Patch by Stefan Roese, 10 May 2006
+
+* Fix watchdog issues for ColdFire boards.
+
+* Add M5271EVB board support.
+
+* Make R5200 specific low level initialization board conditional.
+
+* Update CPU target identification strings for ColdFire family.
+
+* Update register definitions for MCF5271.
+
+* Fix serial console support for MCF5271.
+
+* Fixes for gcc 3.4 based m68k toolchain,
+ based on patch by Jate Sujjavanich.
+
+* Fix lowboot support on MCC200 board
+
+* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:
+ - Removed MPC8349ADS port
+ - Added PCI support to MPC8349ADS
+ - reworked memory map to allow mapping of all regions with BATs
+ Patch by Kumar Gala, 20 Apr 2006
+
+* Coding Style cleanup
+
+* Write RTC seconds first to maintain settings integrity per
+ Maxim/Dallas DS1306 data sheet.
+ Patch by Alan J. Luse, 02 May 2006
+
+* Scheduled for removal: strnicmp() which is unused
+
+* Update for Intel Monahans boards:
+ - support for magic key detection and handling on delta board
+ - NAND support for zylonite board + some minor cleanup
+
+* Declare load_serial_ymodem() when using CFG_CMD_LOADB.
+ Patch by Jon Loeliger, 01 May 2006
+
+* Fixed handling of bad checksums with "mkimage -l"
+
+* Added support for BC3450 board
+ Patch by Stefan Strobl, 21 Oct 2005
+
+* Update for NC650 board:
+ - Support rev1 and rev2 hardware
+ - adapt to new NAND layer
+ - add CP850 configuration based on NC650
+
+* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
+ is configured; othrwise DMA accesses aren't cache coherent which
+ causes for example USB to fail.
+
+* Some code cleanup
+
+* Fix dbau1x00 boards broken by dbau1550 patch
+ PLL:s were not set for boards other than 1550.
+ Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
+ Default boot is now bootp for cards other than 1550.
+ Patch by Thomas Lange, 10 Aug 2005
+
+* Fixes common/cmd_flash.c:
+ - fix some compiler/parser error, if using m68k tool chain
+ - optical fix for protect on/off all messages, if using more
+ then one bank
+ Patch by Jens Scharsig, 28 Jul 2005
+
+* Fix Quad UART mapping on MCC200 board due to new HW revision
+
+* Fix JFFS2 support for legacy NAND driver.
+
+* Remove dependencies between DoC code and old legacy NAND driver.
+
+* Fix PM828_PCI target, for which PCI was *not* configured in.
+
+* Fix Lite5200B support: initialize SDelay register
+ See Freescale's AN3221 "MPC5200B SDRAM Initialization and
+ Configuration", 3.3.1 SDelay--MBAR + 0x0190
+
+* Changes/fixes for drivers/cfi_flash.c:
+
+ - Add Intel legacy lock/unlock support to common CFI driver
+
+ On some Intel flash's (e.g. Intel J3) legacy unlocking is
+ supported, meaning that unlocking of one sector will unlock
+ all sectors of this bank. Using this feature, unlocking
+ of all sectors upon startup (via env var "unlock=yes") will
+ get much faster.
+
+ - Fixed problem with multiple reads of envronment variable
+ "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
+
+ - Removed unwanted linefeeds from "protect" command when
+ CFG_FLASH_PROTECTION is enabled.
+
+ - Changed p3p400 board to use CFG_FLASH_PROTECTION
+
+ Patch by Stefan Roese, 01 Apr 2006
+
+* Changes/fixes for drivers/cfi_flash.c:
+ - Correctly handle the cases where CFG_HZ != 1000 (several
+ XScale-based boards)
+ - Fix the timeout calculation of buffered writes (off by a
+ factor of 1000)
+ Patch by Anders Larsen, 31 Mar 2006
+
+* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
+
+ 405 SDRAM: - The SDRAM parameters can now be defined in the board
+ config file and the 405 SDRAM controller values will
+ be calculated upon bootup (see PPChameleonEVB).
+ When those settings are not defined in the board
+ config file, the register setup will be as it is now,
+ so this implementation should not break any current
+ design using this code.
+
+ Thanks to Andrea Marson from DAVE for this patch.
+
+ 440 DDR: - Added function sdram_tr1_set to auto calculate the
+ TR1 value for the DDR.
+ - Added ECC support (see p3p440).
+
+ Patch by Stefan Roese, 17 Mar 2006
+
+* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
+ Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
+
+* Add support for ymodem protocol download
+ Patch by Stefano Babic, 29 Mar 2006
+
+* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
+ Merge from Markus Klotzbücher's repo, 01 Apr 2006
+
+* GCC-4.x fixes: clean up global data pointer initialization for all
+ boards
+
+* Update for Delta board:
+ - redundant NAND environment
+ - misc Monahans cleanups (remove dead code etc.)
+ - DA9030 Initialization; some minimal changes to PXA I2C driver to
+ make it work with the Monahans.
+ - Make Monahans clock frequency configurable using
+ CFG_MONAHANS_RUN_MODE_OSC_RATIO and
+ CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
+ Merge from Markus Klotzbücher's repo, 25 Mar 2006
+
+* Enable Quad UART om MCC200 board.
+
+* Cleanup MCC200 board configuration; omit non-existent stuff.
+
+* Add support for MPC859/866 Rev. A.0
+
+* Add command for handling DDR ECC registers on MPC8349EE MDS board.
+
+* Fix DDR ECC bit definitions for MPC83xx.
+
+* Add initial support for MPC8349E MDS board.
+
+* Add support for ECC DDR initialization on MPC83xx.
+
+* Add DMA support for MPC83xx.
+
+* Add sync in do_reset() routine for MPC83xx after RPR register
+ was written to. It is need on some targets when BAT translation
+ is enabled.
+
+* Add bit definitions for MPC83xx DDR controller registers.
+
+* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
+
+* Correct shift offsets in icache_status and dcache_status for MPC83xx.
+
+* Add support for DS1374 RTC chip.
+
+* Add support for Lite5200B board.
+ Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
+
+* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
+ timer and cpu_reset code from cpu/$(CPU) into the new
+ cpu/$(CPU)/$(SOC) directories
+ Patch by Andreas Engel, 13 Mar 2006
+
+* Change max size of uncompressed uImage's to 8MByte and add
+ CFG_BOOTM_LEN to adjust this setting.
+
+ As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
+ uImages was restricted to 4MBytes. This default size is now
+ increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
+ in the board config file.
+
+ Patch by Stefan Roese, 13 Mar 2006
+
+* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
+ Patch by Stefan Roese, 13 Mar 2006
+
+* cpu/ppc4xx/start.S : exceptions are enabled after relocation
+ Patch by Cedric Vincent, 06 Jul 2005
+
+* au1x00_eth.c: check malloc return value and abort if it failed
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Change the sequence of events in soft_i2c.c:send_ack() to keep from
+ incorrectly generating start/stop conditions on the bus.
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+ should look at LSB of L1CSRn registers to determine if L1 cache is
+ enabled, not the MSB.
+ Patch by Murray Jensen, 19 Jul 2005
+
+* Fix array overflow with fw_setenv on uninitialised environment
+ Patch by Murray Jensen, 15 Jul 2005
+
+* Add support for EmbeddedPlanet EP88x boards
+ Patch by Yuli Barcohen, 13 Jul 2005
+
+* Remove board specific configuration includes from the common xilinx
+ ethernet and iic adapter code.
+ Patch by Michael Libeskind, 12 Jul 2005
+
+* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add (some) definitions for the MPC85xx local bus controller
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add CPM2 I/O pin functions for MPC85xx processors
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Fix compile problem
+
+* Added PCI support for MPC8349ADS board
+ Patch by Kumar Gala 11 Jan 2006
+
+* Enable address translation on MPC83xx
+ Patch by Kumar Gala, 10 Feb 2006
+
+* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
+ Patch by Kumar Gala, 25 Jan 2006
+
+* Fixed defines for MPC83xx SICRL register to match current specs
+ Patch by Kumar Gala, 23 Jan 2006
+
+* Only disable the MPC83xx watchdog if its enabled out of reset.
+ If its disabled out of reset SW can later enable it if so desired
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow config of GPIO direction & data registers at boot on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Enable time handling on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Make System IO Config Registers board configurable on MPC83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Fixed PCI indirect config ops to handle multiple PCI controllers
+ We need to adjust the bus number we are trying to access based
+ on which PCI controller its on
+ Patch by Kumar Gala, 12 Jan 2006
+
+* Report back PCI bus when doing table based device config
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added support for PCI prefetchable region and BARs
+ If a host controller sets up a region as prefetchable and
+ a device's BAR denotes it as prefetchable, allocate the
+ BAR into the prefetch region.
+
+ If a BAR is prefetchable and no prefetchable region has
+ been setup by the controller we fall back to allocating
+ the BAR into the normally memory region.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add helper function for generic flat device tree fixups for mpc83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for passing initrd information via flat device tree
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added OF_STDOUT_PATH and OF_SOC
+
+ OF_STDOUT_PATH specifies the path to the device the kernel can use
+ for console output
+
+ OF_SOC specifies the proper name of the SOC node if one exists.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow board code to fixup the flat device tree before booting a kernel
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added CONFIG_ options for bd_t and env in flat dev tree
+
+ CONFIG_OF_HAS_BD_T will put a copy of the bd_t
+ into the resulting flat device tree.
+
+ CONFIG_OF_HAS_UBOOT_ENV will copy the environment
+ variables from u-boot into the flat device tree
+
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for the DHCP vendor optional bootfile (#67).
+ Ignores the vendor TFTP server name option (#66).
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
+ Patch by Andy Fleming, 14 Jun 2005
+
+* Fix bad register definitions for LTX971 PHY on MPC85xx boards.
+ Patch by Gerhard Jaeger, 21 Jun 2005
+
+* Add netconsole and some more commands to RPXlite_DW board
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix bad declaration on pci_cfgfunc_nothing
+ Patch by Sam Song, 19 Jun 2005
+
+* Adjust "echo" as a default command
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC
+ Patch by KokHow Teh, 16 Jun 2005
+
+* Add crc of data to jffs2 (in jffs2_1pass_build_lists()).
+ Patch by Rick Bronson, 15 Jun 2005
+
+* Coding Style cleanup
+
+* Avoid dereferencing NULL in find_cmd() if no valid commands were found
+ Patch by Andrew Dyer, 13 Jun 2005
+
+* Add ADI Blackfin support
+ - add support for Analog Devices Blackfin BF533 CPU
+ - add support for the ADI BF533 Stamp uClinux board
+ - add support for the ADI BF533 EZKit board
+ Patches by Richard Klingler, 11 Jun 2005
+
+* Add loads of ntohl() in image header handling
+ Patch by Steven Scholz, 10 Jun 2005
+
+* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
+ variable to set clock
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* RPXlite configuration fixes
+ - Use correct flash sector size
+ - Use correct memory test end address
+ - Add support for bzip2 compression
+ - Various small fixes
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Memory configuration changes for ZPC.1900 board
+ - Fix SDRAM timing on both local bus and 60x bus
+ - Add support for second flash bank (SIMM)
+ - Change boot flash base
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Add support for Adder boards with 16MB SDRAM;
+ add support for second FEC on Adder87x board.
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Fix conditional for including ks8695eth driver
+ Patch by Greg Ungerer, 04 Jun 2005
+
+* Fix Makefile: include config.mk only after CROSS_COMPILE is defined
+ Patch by Friedrich Lobenstock, 02 Jun 2005
+
+* Fix comment in common/soft_i2c.c
+ Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005
+
+* Cleanup compiler warnings.
+ Patch by Greg Ungerer, 21 May 2005
+
+* Word alignment fixes for word aligned NS16550 UART
+ Patch by Jean-Paul Saman, 01 Mar 2005
+
+ Fixes bug with UART that only supports word aligned access: removed
+ "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some
+ (broken!) versions of GCC generate byte accesses when encountering
+ the packed attribute regardless if the struct is already correctly
+ aligned for a platform. Peripherals that can only handle word
+ aligned access won't work properly when accessed with byte access.
+ The struct NS16550 is already word aligned for REG_SIZE = 4, so
+ there is no need to packed the struct in that case.
+
+* Fix behaviour if gatewayip is not set
+ Patch by Robin Gilks, 23 Dec 2004
+
+* Fix cleanup for netstart board.
+ Remove build results from repository
+
+* Some code cleanup for GCC 4.x
+
+* Fixes to support environment in NAND flash;
+ enable NAND flash based environment for delta board.
+
+* Add support for Intel Monahans CPU on Zylonite and Delta boards
+ (This is Work in Progress!)
+
+* Add support for TQM8260-AI boards.
+
+* Minor code cleanup
+
+* Merge the new NAND code (testing-NAND brach); see doc/README.nand
+ Rewrite of NAND code based on what is in 2.6.12 Linux kernel
+ Patch by Ladislav Michl, 29 Jun 2005
+
+* Add lowboot target to mcc200 board
+ Patch by Stefan Roese, 4 Mar 2006
+
+* Fix problem with flash_get_size() from CFI driver update
+ Patch by Stefan Roese, 1 Mar 2006
+
+* Make CFG_NO_FLASH work on ARM systems
+ Patch by Markus Klotzbuecher, 27 Feb 2006
+
+* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
+ use hush shell.
+
+* Convert mcc200 to use common CFI flash driver
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Add env-variable "unlock" to handle initial state of sectors
+ (locked/unlocked).
+
+ Only the U-Boot image and it's environment is protected,
+ all other sectors are unprotected (unlocked) if flash
+ hardware protection is used (CFG_FLASH_PROTECTION) and
+ the environment variable "unlock" is set to "yes".
+
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Update drivers/cfi_flash.c:
+ - find_sector() called in both versions of flash_write_cfiword()
+ Patch by Peter Pearse, 27th Feb 2006
+
+* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
+ Patch by Jose Maria Lopez, 16 Jan 2006
+
+* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
+ Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
+
+* Changes/fixes for drivers/cfi_flash.c:
+ We *should* check if there are any error bits if the previous call
+ returned ERR_OK (Otherwise we will have output an error message in
+ flash_status_check() already.) The original code would only check for
+ error bits if flash_status_check() returns ERR_TIMEOUT.
+ Patch by Marcus Hall, 23 Aug 2005
+
+* Changes/fixes for drivers/cfi_flash.c:
+ - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
+ - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
+ Patch by Sangmoon Kim, 19 Aug 2005
+
+* Fixes for drivers/cfi_flash.c:
+ - Fix wrong timeout value usage in flash_status_check()
+ - Round write_tout up when converting to msec in flash_get_size()
+ - Remove clearing flash status at the end of flash_write_cfibuffer()
+ which sets Intel 28F640J3 flash back to command mode on CSB472
+ Patch by Tolunay Orkun, 02 July 2005
+
+* Add basic support for the SMMACO4 Board from PanDaCom.
+ Patch by Heiko Schocher, 20 Feb 2006
+
+* Add GIT version information (commid ID) to untagged U-Boot versions
+
+ As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
+ of all unreleased (untagged) U-Boot images will be automatically
+ extended upon compiletime with a part of the GIT commit ID and
+ possibly with "dirty" if uncommited changes are detected.
+
+ Here an example for the resulting version:
+ "U-Boot 1.1.4-g3457ac18-dirty"
+
+ The version is now maintained in the toplevel Makefile and the
+ version headers are autogenerated.
+
+ Patch by Stefan Roese, 9 Feb 2006
+
+* Update default environment for INKA4x00 board.
+
+* Convert CPCI750 to use common CFI flash driver
+ Patch by Reinhard Arlt, 8 Feb 2006
+
+* Various changes to esd HH405 board specific files
+ Patch by Matthias Fuchs, 07 Feb 2006
+
+* Cleanup U-Boot boot messages on ARM.
+
+ To match the U-Boot user interface on ARM platforms to the U-Boot
+ standard (as on PPC platforms), some messages with debug character
+ are removed from the default U-Boot build.
+ Enable DEBUG for lib_arm/board.c to enable debug messages.
+ New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
+ Patch by Stefan Roese, 24 Jan 2006
+
+* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
+ Patch by Stefan Roese, 18 Jan 2006
+
+* Add VGA support (CT69000) to CPCI750 board.
+ Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
+ Patch by Reinhard Arlt, 30 Dec 2005
+
+* PMC405 and CPCI405: Moved configuration of pci resources
+ into config file.
+ PMC405 and CPCI2DP: Added firmware download and booting via pci.
+ Patch by Matthias Fuchs, 20 Dec 2005
+
+* Add ColdFire targets to MAKEALL script
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Add support for r5200 board
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Add support for Freescale M5271 processor
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Fix 28F256J3A support on PM520 board
+ (without bank-switching only 32 MB can be accessed)
+
+* Fix mkimage bug with multifile images created on 64 bit systems.
+
+* Add support for 28F256J3A flash (=> 64 MB) on PM520 board
+
+* Fix compiler problem with at91rm9200dk board.
+ Patch by Eugen Bigz, 19 Dec 2005
+
+======================================================================
+Changes for U-Boot 1.1.4:
+======================================================================
+
+* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
+ - Changed GPIO setup to enable another address line in order to
+ address 64M of FLASH.
+ - Added function sdram_tr1_set to auto calculate the tr1 value for
+ the DDR.
+ Patch by Steven Blakeslee, 12 Dec 2005
+
+* MPC5200: Set PCI retry counter to 0 = infinite retry;
+ The default of 255 is too short for slow devices.
+ Patch by Martin Nykodym, 12 Dec 2005
+
+* Change port configuration for O2DNT (CODEC1 on PSC1).
+
+* Fix register for PCI async mode on PPC440EP
+ Patch by Youngchul Bang, 08 Dec 2005
+
+* Fix U-Boot linking problems (add .eh_frame segment to linker script)
+ This segment may be required by some libgcc.a functions
+ (like _udivdi3).
+
+* Fix DPRAM offset/size for MPC8541/8555.
+ Simplify TQM85xx Makefile handling.
+
+* Fix data overflow (typo?) in rtc/ds1302.c
+
+* Fix U-Boot compilation for MIPS boards using ELDK 4.0
+
+* Add support for TQM8541/8555 boards, TQM85xx support reworked:
+ - Support for TQM8541/8555 boards added.
+ - Complete rework of TQM8540/8560 support.
+ - Common TQM85xx code now supports all current TQM85xx platforms
+ (TQM8540/8541/8555/8560).
+ - DDR SDRAM size detection added.
+ - CAS latency default values can be overwritten by setting "serial#"
+ to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
+ If problems are detected with this non default CAS latency,
+ the default values will be used instead.
+ - Flash size detection added.
+ - Moved FCC ethernet driver initialization behind TSEC driver init
+ -> TSEC is first device.
+ Patch by Stefan Roese, 30 Nov 2005
+
+* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
+ Patch by John Otken, 23 Nov 2005
+
+* Changed PPC44x startup message (cpu info, speed...) to common style:
+ On PPC44x platforms, the startup message generated in "cpu.c" only
+ comprised the ppc type and revision but not additional information
+ like speed etc. Those speed infos where printed in the board specific
+ code. This new implementation now prints all CPU infos in the common
+ cpu specific code. No board specific code is needed anymore and
+ therefore removed from all current 44x implementations.
+ Patch by Stefan Roese, 27 Nov 2005
+
+* Adjust TQM834x PHY addresses for latest hardware revision.
+
+* Increase malloc arena on TQM5200 board to 256 kB.
+ With 64 kb uniform flash sector size the old value of 128 kB was
+ too small.
+
+* Fix miiphy global data initialization (problem on 4xx boards when
+ no ethaddr is assigned). Initialization moved from
+ miiphy_register() to eth_initialize().
+
+ Based on initial patch for 4xx platform by Matthias Fuchs.
+
+* Remove unnnecessary #include <linux/types.h> from include/asm-*/u-boot.h
+
+* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code.
+ The COPYING file was extended to make clear that these files can be
+ used in non-GPL code, too.
+ Also, a corresponding note was placed in the headers of the affected files.
+
+* Add support for Prodrive P3P440 board:
+ - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
+ - CFG_FLASH_QUIET_TEST added to use the common CFI driver
+ for bank autodetection
+ Patch by Stefan Roese, 22 Nov 2005
+
+* Change all '$(...)' variable references into '${...}'
+ which makes the environment compatible with the hush shell.
+ WARNING: Support for the old '$(...)' syntax will be
+ discontinued in a later version.
+
+* Minor changes to init flags in TQM834x PCI.
+
+* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM)
+ Patch by Stefan Roese, 15 Nov 2005
+
+* New PPC 405EP board added: CMS700
+ Added CONFIG_NET_MULTI for VOM405 board.
+ Added reset_phy() for VOM405 board.
+ Patch by Matthias Fuchs, 09 Nov 2005
+
+* Updated PCI mapping for esd CPCI2DP board.
+ Add support for error LED.
+ Patch by Matthias Fuchs, 07 Nov 2005
+
+* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
+ Patch by Stefan Roese, 07 Nov 2005
+
+* Correct PPC Timebase register definitions (SPRN_TBRL...)
+ Patch by Stefan Roese, 07 Nov 2005
+
+* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
+ Patch by Stefan Roese, 05 Nov 2005
+
+* Additional fix for external IRQ config on Yellowstone & Yosemite
+ Patch by Stefan Roese, 03 Nov 2005
+
+* Add support for Ocotea pass 3 with 440GX Rev. F
+ Patch by Stefan Roese, 01 Nov 2005
+
+* Fix external IRQ configuration on Yellowstone & Yosemite
+ Patch by Stefan Roese, 28 Oct 2005
+
+* Add support for multiple PHYs.
+ Tested on the following boards:
+ cmcpu2 (at91rm9200/ether.c)
+ PPChameleon (ppc4xx/4xx_enet.c)
+ yukon (mpc8220/fec.c)
+ uc100 (mpc8xx/fec.c)
+ tqm834x (mpc834x/tsec.c) with EEPRO100
+ lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
+ Main changes include:
+ common/miiphyutil.c
+ - miiphy_register routine was added to allow multiple PHYs to be registered
+ - miiphy_read and miiphy_write are now defined in this file, and
+ require additional argument (char *devname)
+ - other miiphy_* routines also require additional device name argument
+ ../lib_i386/board.c
+ ../lib_ppc/board.c
+ Calling reset_phy() was moved to be executed *after* eth_initialize().
+ This is necessary as now some of the implementations of reset_phy()
+ may need to use miiphy_reset() which is not allowed before eth_initialize()
+ as eth_initialize registers all required miiphy_* routines.
+ Tested on IP860 and PHY initializes properly after this change.
+
+* Correct includes for flat tree builder.
+
+* Fix conflicting types (flash_write()) in trab auto_update.c.
+
+* Add PCI support for the TQM834x board.
+
+* Add missing 4xx board to MAKEALL
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix conflicting types (flash_write()) in esd auto_update.c
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix problem with sleep in NetConsole (use get_timer())
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Add NetConsole Support for AMCC eval boards
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix NetConsole support on 4xx (only print eth link on 1st transfer)
+ Patch by Stefan Roese, 18 Oct 2005
+
+* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo.
+ Fix identation on ext2ls help entry.
+ Patch by Stefan Roese, 14 Oct 2005
+
+* Add support for TQM834x boards.
+ Cleanup.
+
+* Cleanup for GCC-4.x
+
+* Add documentation for Open Firmware Flat Tree and usage.
+ Patch by Pantelis Antoniou, 13 Oct 2005
+
+* Add missing files for Pantelis Antoniou's patch
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Fix problem in ppc4xx eth-driver without ethaddr (only without
+ CONFIG_NET_MULTI set)
+ Patch by Stefan Roese, 10 Oct 2005
+
+* Fix gzip bmp support (test if malloc fails, warning when truncated).
+ Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board.
+ Patch by Stefan Roese, 07 Oct 2005
+
+* Add support for OF flat tree for the STXtc board.
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Support passing of OF flat trees to the kernel.
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Cleanup
+
+* Add support for NetSilicon NS7520 processor.
+ Patch by Art Shipkowski, 12 May 2005
+
+* Add support for AP1000 board.
+ Patch by James MacAulay, 07 Oct 2005
+
+* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200
+ Patch by Anders Larsen, 07 Oct 2005
+
+ The Atmel errata #11 states that the transfer buffer descriptor
+ table must be aligned on a 16-word boundary. As it turned out, this
+ is insufficient - it seems the table must be aligned on a boundary
+ at least as large as the table itself (in Linux this is not an
+ issue - the table is aligned on a PAGE_SIZE (4096) boundary).
+
+* Fixed compilation for ARM when using a (standard) hard-FP toolchain
+ Patch by Anders Larsen, 07 Oct 2005
+
+* Cleanup warnings for cpu/arm720t & cpu/arm1136 files.
+ sed the linker scripts, rather than pre-process them.
+ Patch by Peter Pearse, 07 Oct 2005
+
+* Update make target for ARM supported boards.
+ Use lowlevel_init() instead of platformsetup() [rename].
+ Patch by Peter Pearse, 06 Oct 2005
+
+* Fix booting from serial dataflash on AT91RM9200
+ Patch by Peter Menzebach, 29 Aug 2005
+
+* Add JFFS2 support for TRAB board
+ Patch by Martin Krause, 25 Aug 2005
+
+* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI
+ Patch by Marcus Hall, 24 Aug 2005
+
+* Fix the machine-id of the Cogent csb637 board
+ Patch by Anders Larsen, 05 Oct 2005
+
+* Complete support for the KwikByte KB920x boards
+ Patch by Anders Larsen, 05 Oct 2005
+
+* Set the AT91RM9200 clock to asynchronous mode
+ Patch by Anders Larsen, 03 May 2005
+
+* Set the AT91RM9200 clock to synchronous mode
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Add support for Cogent csb637
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix dm9161.c initialization
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005
+ (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5)
+
+* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix device partition intialization for SystemACE disks.
+ Patch by Stephen Williams, 28 Apr 2005
+
+* Added support for KwikByte KB920x boards (based on AT91RM9200)
+ Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
+
+* Add support for S29GL064M-R3 flash chip on xsengine board
+ Patch by Kurt Stremerch, 18 Apr 2005
+
+* E500 update: repoint IVPR to RAM when code is relocated
+ Patch by Kylo Ginsberg, 13 Apr 2005
+
+* Fix loop end test in lib_generic/string.c:strswab()
+ Patch by Andrew Dyer, October 10, 2005
+ Signed-off-by: Andrew Dyer <amdyer@gmail.com>
+
+* Cleanup
+
+* Update ARM Integrator boards:
+ Correct addessing errors in platform files.
+ Split off common core module data from Integrator header files to
+ include/armcoremodule.h.
+ Patch by Peter Pearse, 04 Oct 2005
+
+* Make sure only supported compiler options are used
+ Import "cc-option" shell function from kernel and
+ use it to get the correct ARM GCC options for individual CPUs
+ Patch by Peter Pearse, 30 Jun 2005
+
+* Fix 440GR to print correct cpu revision
+ Patch by Stefan Roese, 04 Oct 2005
+
+* Change board message on AMCC Yosemite & Yellowstone to common style
+ Patch by Stefan Roese, 03 Oct 2005
+
+* Fix compiler warning
+
+* Fix FEC PHY addresses for TQM85xx boards
+
+* Fix uninitialized variable problem in hush shell
+ Patch by Lars Rostock, 26 Sep 2005
+
+* Undo change of f6e20fc6ca... to include/configs/trab.h
+ (Must have been an accident?)
+
+* Add support for AT91RM9200 OHCI Controller.
+ Patch by Eric Benard, 07 Apr 2005
+
+* Update ARM mach-types.h
+ Patch by Eric Benard, 07 Apr 2005
+
+* Add support for MP2USB board.
+ Patch by Eric Benard, 07 Apr 2005
+
+* Add board support for armadillo HT1070
+ Patch by Rowel Atienza, 06 Apr 2005
+
+* Second Ethernet address enabled for MPC885ADS and MPC8272ADS.
+ Patch by Vitaly Bordug, 30 Mar 2005
+
+* Add iopset command on mpc8xx
+ Patch by Daniel Eisenhut, 25 Mar 2005
+
+* Add support for MII in eepro100 driver.
+ Patch by Gleb Natapov, 21 Mar 2005
+
+* Fixes to the Lubbock (PXA 25x) support:
+ - Resolve the FIXME with respect to saving the u-boot environment.
+ - Make the default load address land in real memory.
+ - Fix lan91c96 SMC_{in,out}{b,w,l}() macros
+ Patch by David Brownell, 10 Mar 2005
+
+* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board
+ Patch by Marc Leeman, 04 Mar 2005
+
+* OMAP242x H4 board update
+ - fix for ES2 differences.
+ - switch to using the cfi_flash driver.
+ - fix SRAM build address.
+ - fix for GP device operation.
+ - unlock SRAM for GP devices.
+ - display more device information.
+ - fix potential deadlock in omap24xx_i2c driver.
+ - fix DLL load values to match dpllout*1 operation.
+ - fix 2nd chip select init for combo DDR device.
+ - add support for CFI Intel 28F256L18 on H4 board.
+ Patch by Richard Woodruff, 03 Mar 2005
+
+* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h
+ Patch by Steven Scholz, 02 Mar 2005
+
+* Fix typo in eth.c
+ Patch by Ara Avanesyan, 24 Feb 2005
+
+* Remove unneeded #include <malloc.h>
+ Patch by Ladislav Michl, 22 Feb 2005
+
+* Add cramfs support for m68k
+ Patch by Zachary Landau, 21 Feb 2005
+
+* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs
+ Patch by Jeff Angielski, 21 Feb 2005
+
+* Fix au1x00_serial baud rate calculation:
+ remove hardcoded cpu clock divisor and use register instead;
+ round up instead of truncate
+ Patch by Andrew Dyer, 15 Feb 2005
+
+* Add Xilinx Spartan3 family FPGA support
+ Patch by Kurt Stremerch, 14 Feb 2005
+
+* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET
+ Patch by Zachary Landau, 11 Feb 2005
+
+* Fix VOH405 Support
+ Patch by Matthias Fuchs, 25 Sep 2005
+
+* Added support for PCI bridge on MPC8272ADS
+ Patch by Vitaly Bordug, Feb 09 2005
+
+* Update multicore CM9XX support for Integrator AP to allow booting from flash
+ Patch by Jean-Paul Saman, 8 Feb 2005
+
+* Fix strswab() to reliably find end of string
+ Patch by Andrew Dyer, 08 Feb 2005
+
+* Fix typos in include/ppc440.h
+ Patch by Andrew E Mileski, 04 Feb 2005
+
+* Add Vibren (was Accelent) PXA255 IDP Support
+ Patch by Cliff Brake, 04 Feb 2005
+
+* Fix tools/bmp_logo.c using incorrect offset to pixel data
+ Patch by Andrew Dyer, 31 Jan 2005
+
+* Add ARM946E cpu and core module targets; remap memory to 0x00000000
+ Patch by Peter Pearse, 2 Feb 2005
+
+* Fix error handling in tools/env/fw_env.c
+ Patch by Ara Avanesyan, 01 Feb 2005
+
+* Fix MGT5100 PSC baudrate calculation
+ Patch by Sebastian Schau, 27 Jan 2005
+
+* OMAP242x fix for GP device booting
+ - Add SRAM unlock for GP devices.
+ - Change DDR DLL unlock value to allow DPLLout*1 operation.
+ Patches by Richard Woodruff, 21 Jan 2005:
+
+* Add support for AMD's Pb1x00 eval board;
+ add MII routines to the au1x00 ethernet driver;
+ add USB ohci driver (work in progress)
+ Patch by Thomas Sailer, 20 Jan 2005
+
+* Update omap5912osk board
+ Use drivers/cfi_flash.c instead of private flash driver;
+ Remove hardcoded personalized settings from omap5912osk.h;
+ Fix spacing with (RO) marks in 'flinfo' output.
+ Patch by Michael Bendzick, 14 Jan 2005
+
+* Fix warnings for PCI code on ixp
+ Patch by Joe <lgxue@yahoo.com>, 13 Jan 2005
+
+* virtex2 fix for bogus download error messages
+ The virtex2 FPGA download code watches for init going active during
+ a download of config data as an error condition. init also goes
+ active after a configuration is finished in concert with the done
+ signal. So far, the code does not check for done active until all
+ of the configuration data is sent. If configuration data has a few
+ extra pad bytes at the end, this would cause an error message even
+ though the download had suceeded.
+ NOTE: virtex2 slave serial and spartan2 versions may still have the
+ same problem.
+ Patch by Andrew Dyer, 12 Jan 2005
+
+* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian
+ Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode"
+ message when probing for nonexistent flash in little endian mode.
+ As a side effect more efficient and smaller code is generated,
+ which is always a Good Thing (TM).
+ Patch by Ladislav Michl, 24 Sep 2005
+
+* Update for TFTP using a fixed UDP port
+ Use the approved environment variable names. Added "tftpdstp" to
+ allow ports other than 69 per Tolunay Orkun's recommendation.
+ Patch by Jerry Van Baren, 12 Jan 2005
+
+* Allow to force TFTP to use a fixed UDP port
+ (Add a configuration option CONFIG_TFTP_PORT and optional env
+ variable tftpport)
+ Patch by Jerry Van Baren, 10 Jan 2005
+
+* Fix ethernet timeouts on dbau1550 and other au1x00 systems
+ Patch by Leif Lindholm, 29 Dec 2004
+
+* Cleanup: fix broken builds
+
+* Fix PHY address argument passing with mii info command
+ Patch by Andrew Dyer, 28 Dec 2004
+
+* Cleanup (PPC4xx is AMCC now)
+
+* esd CPCI2DP board added
+ Patch by Matthias Fuchs, 22 Sep 2005
+
+* esd PMC405 board updated
+ Patch by Matthias Fuchs, 22 Sep 2005
+
+* Add SM501 support to HH405 board.
+ Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP).
+ Add support for eeprom write-enable (CFG_EEPROM_WREN).
+ Patch by Stefan Roese, 22 Sep 2005
+
+* Fix autonegotiation in tsec ethernet driver
+ Patch by Stefan Roese, 21 Sep 2005
+
+* Fix bug in auto_update (trab board)
+ Patch by Martin Krause, 16 Sep 2005
+
+* Fix computation of framebuffer palette for 8bpp LCD bitmaps
+ Patch by Francesco Mandracci, 16 Sep 2005
+
+* Update configuration for INKA4x0 board
+
+* Update configuration for PM854 board
+ Based on patch by R. Loeffl, 20 Jul 2005
+
+* Add PCI support to TQM8540 and TQM8560 boards
+ Patch by Stefan Roese, 15 Sep 2005
+
+* Update AMCC Yosemite to get a consistent setup for all AMCC eval
+ boards (baudrate, environment...). Flash driver fixed.
+ Patch by Stefan Roese, 15 Sep 2005
+
+* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd
+ ethernet port on ebony.
+ Patch by Stefan Roese, 7 Sep 2005
+
+* Added support for mtddevnum and mtddevname variables (mtdparts command)
+
+* Change default console baud rate for stxxtc board
+
+* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
+ Patch by Stefan Roese, 31 Aug 2005
+
+* Fix default command set (don't include CFG_CMD_DISPLAY command)
+ Patch by Pantelis Antoniou, 02 Sep 2005
+
+* Cleanup
+
+* Enable SM712 driver support for HMI1001 board.
+
+* Fix problems with ld version 2.16 (dot outside sections problem)
+ Pointed out by Gerhard Jaeger, 31 Aug 2005;
+ cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
+
+* Prepare U-Boot for gcc-4.x: fix global data pointer initialization
+
+* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux
+
+* Add keyboard and dot matrix display support for HMI1001 board.
+
+* Prepare U-Boot for gcc-4.x
+
+* Fixed Bamboo port to enable running without DDR-DIMM
+ (Bamboo has also 64MB onboard DDR)
+ Patch by Stefan Roese, 24 Aug 2005
+
+* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
+ now handling all 4xx cpu's
+ Patch by Stefan Roese, 16 Aug 2005
+
+* Fix make dependencies for at91rm9200 and ks8695 cpus
+ Patch by Steven Scholz, 23 Aug 2005
+
+* Add JFFS2 support for TQM5200 board
+
+* Add esd cpci5200 and pf5200 boards
+ Patch by Reinhard Arlt, 22 Aug 2005
+
+* Fix sysclock for TQM8540 and TQM8560 boards
+ Patch by Martin Krause, 25 Jul 2005
+
+* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2
+ Patch by Martin Krause, 08 Jun 2005
+
+* Add new board specific commands for TQM5200/STK52XX
+ - Sound commands (beep, wav, sound)
+ - Test commands (led, can, backlight, rs232)
+ Patch by Martin Krause, 02 May 2005
+
+* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
+ because of a bug in the AT91RM9200 CPU PLL
+ Patch by Martin Krause, 22 Apr 2005
+
+* Add automatic HW detection for another CMC_PU2 variant
+ Patch by Martin Krause, 20 Apr 2005
+
+* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration
+ Patch by Martin Krause, 19 Apr 2005
+
+* Fix initialization problem on TQM5200 without SM501
+ Patch by Martin Krause, 08 Apr 2005
+
+* Add RTC support for STK52XX.200
+ Patch by Martin Krause, 07 Apr 2005
+
+* Add support for IFM o2dnt board
+
+* Enable PCI on hmi1001 board
+
+* Fix return values of the jffs2 commands ls/fsload/fsinfo,
+ so we can use them to, e.g., check the existence of a file with
+ "if ls foo; then this; else that; fi" in the hush shell
+ Patch by Andreas Engel, 16 August 2005
+
+* Coding style cleanup
+
+* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
+ Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
+
+* Check return value of malloc in 440gx_enet.c
+ Patch by Travis B. Sawyer, 18 Jul 2005
+
+* Add Sandburst Metrobox and Sandburst Karef board support packages.
+ Second serial port on 440GX now defined as a system device.
+ Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
+ Patch by Travis B. Sawyer, 12 Jul 2005
+
+======================================================================
+Changes for U-Boot 1.1.3:
+======================================================================
+
+* Minor code cleanup
+
+* Add forgotten new fils from latest VoiceBlue update
+
+* Make bootretry feature work with hush shell.
+ Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too.
+ Patch by Andreas Engel, 19 Jul 2005
+
+* Update Hymod Board Database PHP code in "tools" directory
+ Patch by Murray Jensen, 01 Jul 2005
+
+* Make "tr" command use POSIX compliant; export HOSTOS make variable
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix Murray Jensen's mail address.
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Preserve PHY_BMCR during a soft reset.
+ Patch by Carl Riechers, 24 Jun 2005
+
+* VoiceBlue update: eeprom tool can also store firmware version now.
+ eeprom.bin is runable by jumping at load address.
+ Patch by Ladislav Michl, 23 May 2005
+
+* Move the AT91RM9200DK to the ARM Systems list.
+ Patch by Anders Larsen, 26 Apr 2005
+
+* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3
+ Patch by Anders Larsen, 26 Apr 2005
+
+* measure_gclk() is needed when DEBUG is enabled
+ Patch by Bryan O'Donoghue, 25 Apr 2005
+
+* Add UPD-Checksum code, fix problem in net.c (return instead of break)
+ Patch by Reinhard Arlt, 12 Aug 2005
+
+* esd PCI405 board updated
+ Patch by Matthias Fuchs, 28 Jul 2005
+
+* esd WUH405 and DU405 board updated
+ Patch by Matthias Fuchs, 27 Jul 2005
+
+* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I)
+ Patch by Matthias Fuchs, 4 May 2005
+
+* Update AMCC Yosemite to get a consistent setup for all AMCC eval
+ boards (baudrate, environment...). Flash driver fixed.
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Add NAND FLASH support for AMCC Bamboo 440EP eval board
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Add configuration for IFM AEV FIFO board.
+ Minor coding style cleanup.
+
+* Add configuration for IFM SPI eval board
+
+* Fix CompactFlash problem on HMI1001 board
+
+* Make new "mtdparts" code build with older compilers
+ Patch by Andrea Scian, 09 Aug 2005
+
+* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to
+ CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design
+ with the 405 defines and the linux kernel defines.
+ Patch by Stefan Roese, 08 Aug 2005
+
+* Fix compiler warnings with older GCC versions
+
+* Add common (with Linux) MTD partition scheme and "mtdparts" command
+
+ Old, obsolete and duplicated code was cleaned up and replace by the
+ new partitioning method. There are two possible approaches now:
+
+ The first one is to define a single, static partition:
+
+ #undef CONFIG_JFFS2_CMDLINE
+ #define CONFIG_JFFS2_DEV "nor0"
+ #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */
+ #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */
+ #define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+ The second method uses the mtdparts command line option and dynamic
+ partitioning:
+
+ /* mtdparts command line support */
+ #define CONFIG_JFFS2_CMDLINE
+ #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
+ #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+
+ Command line of course produces bigger images, and may be inappropriate
+ for some targets, so by default it's off.
+
+* Fix build problems for PM856 Board
+
+* Fix sign extension bug in 'fpga loadb' command;
+ make 'fpga loadb' always print the file header info
+ Patch by Andrew Dyer, 11 Jan 2005
+
+* Fix errors that occur when accessing SystemACE CF
+ Patch by Jeff Angielski, 09 Jan 2005
+
+* Document switching between U-Boot and PlanetCore on RPXlite
+ by Sam Song, 24 Dec 2004
+
+* Fix PowerQUICC II mask detection.
+ Patch by Eugene Surovegin, 20 Dec 2004
+
+* Add support for Altera NIOS DK1C20 board
+ Patch by Shlomo Kut, 13 Dec 2004
+
+* Add support for ep8248 board
+ Patch by Yuli Barcohen, 12 Dec 2004
+
+ Minor code cleanup.
+
+* Fix baudrate setting for KGDB on MPC8260
+ Patch by HoJin, 11 Dec 2004
+
+* Fix 'mii help' text formatting
+ Patch by Cory Tusar, 10 Dec 2004
+
+* Fix return code of NFS command
+ Patch by Hiroshi Ito, 11 Dec 2004
+
+* Fix typo
+
+* Fix compiler warnings in cpu/ppc4xx/usbdev.c
+ Patch by Steven Blakeslee, 04 Aug 2005
+
+* Add support for AMCC Bamboo PPC440EP eval board
+ Patch by Stefan Roese, 04 Aug 2005
+
+* Patch by Jon Loeliger
+ Fix style issues primarily in 85xx and 83xx boards.
+ - C++ comments
+ - Trailing white space
+ - Indentation not by TAB
+ - Excessive amount of empty lines
+ - Trailing empty lines
+
+* Patch by Ron Alder, 11 Jul 2005
+ Add Xianghua Xiao and Lunsheng Wang's support for the
+ GDA MPC8540 EVAL board.
+
+* Patch by Eran Liberty
+ Add support for the Freescale MPC8349ADS board.
+
+* Patch by Jon Loeliger, 25 Jul 2005
+ Move the TSEC driver out of cpu/mpc85xx as it will be shared
+ by the upcoming mpc83xx family as well.
+
+* Patch by Jon Loeliger, 05 May 2005
+ Implemented support for MPC8548CDS board.
+ Added DDR II support based on SPD values for MPC85xx boards.
+ This roll-up patch also includes bugfies for the previously
+ published patches:
+ DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
+
+* Patch by Jon Loeliger, 10 Feb 2005
+ Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
+
+* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
+ For MPC85xxCDS:
+ Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
+ for faster flash parts.
+ Add documentation for BR/OR for FLASH.
+
+* Patch by Jon Loeliger 08 Feb 2005
+ Determine L2 Cache size dynamically on 85XX boards.
+
+* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
+ - Convert the CPM2 based functionality to use new CONFIG_CPM2
+ option rather than a myriad of CONFIG_MPC8560-like variants.
+ Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
+ Eliminates the CONFIG_MPC8560 option entirely. Distributes the
+ new CONFIG_CPM2 option to each 8260 board.
+
+* Add support for MicroSys PM856 board
+ Patch by Josef Wagner, 03 Aug 2005
+
+* Minor fixes to PM854 board
+ Patch by Josef Wagner, 03 Aug 2005
+
+* Adjust configuration of XENIAX board
+ (chip select and GPIO required for USB operation)
+
+* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
+ routed to the Watchdog handler
+ Patch by Eugene Surovegin, 18 Jun 2005
+
+* (re)enabled scsi commands do_scsi() and do_scsiboot()
+ Patch by Denis Peter, 06 Dec 2004
+
+* Fix endianess problem in TFTP / NFS default filenames
+ Patch by Hiroshi Ito, 06 Dec 2004
+
+* Ignore broadcast status bit in received frames in 8260 FCC ethernet
+ loopback test code
+ Patch by Murray Jensen, 18 Jul 2005
+
+* Fix typo in mkconfig script (used == instead of =)
+ Patch by Murray Jensen, 18 Jul 2005
+
+* Cleanup build problems on 64 bit build hosts
+
+* Update MAINTAINERS file
+
+* Patch by Stefan Roese, 01 Aug 2005:
+ - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
+ (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
+ for details.
+ - Sycamore (PPC405GPr) eval board added (Walnut port is extended
+ to run on both 405GP and 405GPr eval boards).
+
+* Patch by Steven Blakeslee, 27 Jul 2005:
+ - Add support for AMCC PPC440EP/GR.
+ - Add support for AMCC Yosemite PPC440EP eval board.
+ - Add support for AMCC Yellowstone PPC440GR eval board.
+
+* Minor fixes for PPChameleon Board:
+ - fix alignment of NAND size
+ - make code do what the comment says
+
+* Implement h/w sector protection status synchronization at boot.
+ The code is provided for, and was tested on, the Yukon/Alaska
+ and PM520 boards only.
+
+ A bug in flash_real_protect() for the Yukon board was fixed by
+ adding a function that tells if two banks are on one flash chip.
+
+* Fix sysmon POST problem: check I2C error codes
+ This fixes a problem of displaying bogus voltages when the voltages
+ are so low that the I2C devices start failing while the rest of the
+ system keeps running.
+
+* Patch by Cedric Vincent, 6 Jul 2005:
+ Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c"
+
+* Patch by Jon Loeliger, 20 Jul 2005:
+ Add missing PCI IO port definitions.
+
+* Add CompactFlash support for HMI1001 board.
+
+* Adjust printed board ID for LWMON board.
+
+* Fix low-level OHCI transfers for ARM920t and MPC5xxx
+
+* Add new argument format for flash commands to allow for usage like
+ "erase $(addr) +$(filesize)", i. e. a size argument can be used and
+ U-Boot will automaticially find the end of the corresponding sector.
+
+* Patch by Stefan Roese, 5 Jul 2005:
+ Update uc100 board PHY setup
+
+* Patch by Stefan Roese, 1 Jul 2005:
+ Fix PHY address for CATcenter board (now correct!)
+
+* Patch by Stefan Roese, 30 Jun 2005:
+ Fix PHY addresses for PPChameleon and CATcenter boards
+ Change MAINTAINER for most esd boards
+
+* Patch by Detlev Zundel, 30 Jun 2005:
+ Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
+
+* Fix baudrate calculation problem on MPC5200 systems
+
+* Add EEPROM and RTC support for HMI1001 board
+
+* Patch by Detlev Zundel, 20 Jun 2005:
+ Fix initialization of low active GPIO pins on inka4x0 board
+
+* Enable redundant environment, disable HW flash protection of
+ HMI1001 board
+
+* Patch by Travis Sawyer, 10 Jun 2005:
+ Initialize allocated dev and private hw structures
+ after their respective allocation in 440gx_enet.c
+
+* Patch by Steven Scholz, 10 Jun 2005:
+ Fix byteorder problems with second argument of "bootm" with
+ standalone images;
+
+* Add support for HMI1001 board
+
+* Disable "date" and "sntp" commands on TQM866M
+
+* Fix watchdog reset problems on LWMON board
+
+* Patch by Juergen Selent, 17 May 2005:
+ Add support for Funkwerk VoVPN gateway module.
+
+* Cleanup debug code for MPC8220 FEC driver
+
+* Extend burst mode RAM test program to take a loop count
+ (0 = infinite)
+
+* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
+ those boards that use it.
+
+* Patches by Greg Ungerer, 19 May 2005:
+ - add support for the KS8695P (ARM 922 based) CPU
+ - add support for the OpenGear CM4008, CM4116 and CM4148 boards
+
+* Patch by Steven Scholz, 19 May 2005:
+ Add support for CONFIG_SERIAL_TAG on ARM boards
+
+* Add PCI support for Sorcery board.
+ Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
+
+* Fix compile problems caused by new burst mode SDRAM test;
+ make port pins to trigger logic analyzer configurable
+
+* Fix timer handling on MPC85xx systems
+
+* Fix debug code in omap5912osk flash driver
+
+* Add support for MPC8247 based "IDS8247" board.
+
+* Add support for 2 x TSEC interfaces on the TQM8540 board.
+
+* On LWMON we must use the watchdog to reset the board as the CPU
+ genereated HRESET pulse is too short to reset the external
+ circuitry.
+
+* Add test tool to exercise SDRAM accesses in burst mode
+ (as standalone program, MPC8xx/PowerPC only)
+
+* Increase CFG_MONITOR_LEN for Rattler board to match actual code
+ size.
+
+* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
+ March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
+ added to support LZO and LZARI compression modes (undefined by
+ default).
+
+* Fix problem with symbolic links in JFFS2 code.
+
+* Use linker ASSERT statement to prevent undetected overlapping of
+ sections on PPChameleon board; other boards might use this, too.
+
+* Patch by Stefan Roese, 03 May 2005:
+ Update for P3G4
+ Fix problems in cmd_universe.c
+
+* Patch by Matthias Fuchs, 03 May 2005:
+ Added missing variable declaration in cmd_nand.c
+ Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
+
+* Fix INKA4x0: use CS1 as gpio_wkup_6 output
+
+* Fix bug in the SDRAM initialization code for canmb, IceCube and
+ PM520 boards.
+ Fix PHY address for canmb board.
+
+* Cleanup serial console baudrate calculation on AT91RM9200;
+ get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
+
+* Patch by Matthias Fuchs, 18 Apr 2005:
+ Make PCI target address spaces on PMC405 and CPCI405 boards
+ configurable via environment variables
+
+* Auto-size RAM on canmb board.
+
+* Add support for canmb board
+
+* Patch by Stefan Roese, 13 Apr 2005:
+ Update for esd apc405
+
+* Fixes for TQM8560 board:
+ - fix clock rates
+ - remove debug messages
+ - fix flash sector protection
+
+* Patch by Steven Scholz, 07 Apr 2005:
+ Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
+
+* Patches by Steven Scholz, 07 Apr 2005:
+ Fix compiler warning in altera.c
+ Fix warning in cpu/arm920t/at91rm9200/i2c.c
+
+* Patch by Ladislav Michl, 06 Apr 2005:
+ Fix voiceblue configuration.
+
+* Patch by Stefan Roese, 06 Apr 2005:
+ Updates for OCOTEA board:
+ - Changed U-Boot size from 512kByte to 256kByte
+ - Fixed flash driver to support boot from soldered user flash
+ - Added README for switch from PIBS firmware to U-Boot
+
+* Patch by Travis Sawyer, 05 Apr 2005:
+ - Change timer frequency for ppc 440 from 10 ms to 1 ms.
+ Problem found by Andrew Wozniak.
+
+* Patch by Steven Scholz, 06 Apr 2005:
+ - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+ - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
+* Patches by Robert Whaley, 29 Nov 2004:
+ - update the pxa-regs.h file for PXA27x chips
+ - add PXA27x based ADSVIX board
+ - add support for MMC on PXA27x processors
+
+* Patch by Andrew E. Mileski, 28 Nov 2004:
+ Fix PPC4xx SPD SDRAM detection bug
+
+* Patch by Hiroshi Ito, 26 Nov 2004:
+ Fix logic of "test -z" and "test -n" commands
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+ Add support for VoiceBlue board.
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+ Fix netboot_common() prototypes.
+
+* Patch by Steven Scholz, 05 Apr 2005:
+ Use i.MX watchdog timer for reset_cpu()
+
+* Patch by Steven Scholz, 05 Apr 2005:
+ Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
+ subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
+ (now in interupts.c)
+
+* Add support for MPC8220 based "sorcery" board.
+
+* Add support for TQM8560 board.
+
+* Add FEC support for TQM8540 board.
+ Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
+
+* Patch by Martin Krause, 04 Apr 2005:
+ Update default configuration for CMC_PU2 board.
+
+* Patch by Steven Scholz, 04 Apr 2005:
+ - remove all references to CONFIG_INIT_CRITICAL for ARM based boards
+ - introduce two new configuration options instead:
+ CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
+
+* Patch by Steven Scholz, 04 Apr 2005:
+ Make sure that MDIO clock does not exceed 2.5 MHz on AT91
+
+* Fix timer code for ARM systems: make sure that udelay() does not
+ reset timers so it's save to use udelay() in timeout code.
+
+* Patch by Mathias Küster, 23 Nov 2004:
+ add udelay support for the mcf5282 cpu
+
+* Patch by Tolunay Orkun, 16 November 2004:
+ fix incorrect onboard Xilinx CPLD base address
+
+* Patch by Jerry Van Baren, 08 Nov 2004:
+ - Add low-boot option for MPC8260ADS board (if lowboot is selected,
+ the jumper for the HRCW source should select flash. If lowboot is
+ not selected, the jumper for the HRCW source should select the
+ BCSR.
+ - change default load base address to 0x00400000
+
+* Patch by Yuli Barcohen, 08 Nov 2004:
+ Add support for Analogue & Micro Rattler boards.
+ Tested on Rattler8248.
+
+* Patch by Andre Renaud, 08 Nov 2004:
+ Fix watchdog support in common/lcd.c
+
+* Patch by Marc Leeman, 05 Nov 2003:
+ Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
+ bug only affects the XPC8245 processors
+
+* Patches by Josef Wagner, 29 Oct 2004:
+ - Add support for MicroSys CPU87 board
+ - Add support for MicroSys PM854 board
+
+* Patch by Jian Zhang, 02 Nov 2004:
+ Add 16-bit NAND support
+
+* Patch by Scott McNutt, 01 Nov 2004:
+ Add missing NIOS/NIOS2 support for "iminfo" command
+
+* Patch by Detlev Zundel, 29 Oct 2004:
+ Add missing NIOS/NIOS2 support for "mkimage" tool.
+
+* Patch by David Adair, 27 Oct 2004:
+ Add missing 440GX SDRAM Controller reset
+
+* Patch by Steven Scholz, 25 Oct 2004:
+ Declare reset_cpu() in include/common.h instead locally
+
+* Patch by Yusdi Santoso, 22 Oct 2004:
+ - Add support for HIDDEN_DRAGON board
+ - fix endianess problem in driver/rtl1839.c
+
+* Patch by Allen Curtis, 21 Oct 2004:
+ support multiple serial ports
+
+* Patch by Richard Klingler, 03 Apr 2005:
+ Add call to eth_halt() in net/net.c when called functions fail
+ after eth_init() has been called.
+
+* Patch by Sam Song, 3 April 2005:
+ - Update README.Netconsole
+ - Update README
+
+* Prepare for SoC rework of ARM code:
+ - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL
+ - rename memsetup into lowlevel_init (function name and source files)
+ Patch by Steven Scholz, 03 Apr 2005:
+ - create SoC specific directories include/asm-arm/arch-imx and
+ include/asm-arm/arch-s3c24x0
+
+* Fix problems with SNTP support;
+ enable SNTP support in some boards.
+
+* Patches by Martin Krause, 01 Apr 2005:
+ - Fix flash erase timeout on CMC_PU2
+ - Add automatic HW detection for CMC_PU2 and CMC_BASIC
+
+* Patch by Steven Scholz, 13 March 2005:
+ fix cache enabling for AT91RM9200
+
+* Patch by Masami Komiya, 30 Mar 2005:
+ add SNTP support and expand time server and time offset fields of
+ DHCP support. See doc/README.SNTP
+
+* Patch by Steven Scholz, 13 Dec 2004:
+ Fix bug in at91rm920 ethernet driver
+
+* Patch by Steven Scholz, 13 Dec 2004:
+ Remove duplicated code by merging memsetup.S files for
+ at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
+
+* Patch by Detlev Zundel, 31 Mar 2005:
+ Cleanup duplicate definition of overwrite_console()
+
+* Update TQM5200 configuration;
+ prepare for Rev. 200 starter kit boards
+
+* Patch by Scott McNutt, 21 Oct 2004:
+ Add support for Nios-II EPCS Controller core.
+
+* Patch by Scott McNutt, 20 Oct 2004:
+ Nios-II cleanups:
+ - Add sysid command (Nios-II only).
+ - Locate default exception trampoline at proper offset.
+ - Implement I/O routines (readb, writeb, etc)
+ - Implement do_bootm_linux
+
+* Patches by Martin Krause, 22 Mar 2005:
+ - use TQM5200_auto as MAKEALL target for TQM5200 systems
+ - add support for SM501 graphics controller
+ - add support for graphic console on TQM5200
+ - add support for TQM5200 Rev 200
+ - cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Manfred Baral, 17 Mar 2005:
+ Fix typo
+
+* Fix RTC configuration for PPChameleon board
+
+* Cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Stefan Roese, 16 Mar 2005:
+ Update for esd auto_update and hh405 board
+
+* Adapt for U-Boot image size (new features enabled) on TQM5200
+
+* Update code for TQM8540 board (and 85xx in general):
+ - Change the name of the Ethernet driver: MOTO ENET -> ENET
+ - Reformat boot messages
+ - Enable redundant environment
+ - Replace the -O2 optimization flag with -mno-string
+
+* Patch by David Brownell, 10 Mar 2005:
+ Restore copyright statements in OHCI drivers.
+
+* Add support for TQM8540 board
+
+* Patch by Detlev Zundel, 14 Mar 2005:
+ NC650: changed NAND flash addressing to using UPMB
+
+* Patch by Stefan Roese, 14 Mar 2005:
+ Update for esd voh405 fpga image
+
+* INKA4x0: Allow initialization of LCD backlight dimming from
+ "brightness" environment variable.
+
+* Add port initialization for digital I/O on INKA4x0
+
+* Patch by Stefan Roese, 01 Mar 2005:
+ Update for esd boards dp405 and hub405
+
+* Fix get_partition_info() parameter error in all other calls
+ (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c).
+
+* Enable USB and IDE support for INKA4x0 board
+
+* Patch by Andrew Dyer, 28 Feb 2005:
+ fix ext2load passing an incorrect pointer to get_partition_info()
+ resulting in load failure for devices other than 0
+
+* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board
+
+* Cleanup USB and partition defines
+
+* Add support for ext2 filesystems and image timestamps to TQM5200 board
+
+* Add reset code for Coral-P on INKA4x0 board
+
+* Patch by Martin Krause, 28 Jun 2004:
+ Update for TRAB board.
+
+* Fix some missing "volatile"s in MPC5xxx FEC driver
+
+* Fix cirrus voltage detection (for CPC45)
+
+* Fix byteorder problem in usbboot and scsiboot commands.
+
+* Patch by Cajus Hahn, 04 Feb 2005:
+ - don't insist on leading '/' for filename in ext2load
+ - set default partition to useful value (1) in ext2load
+
+* Patch by Andrew Dyer, 08 Jan 2005:
+ fix wrong return codes in ext2 code
+
+* Removed '--no-warn-mismatch' option from Makefile. This option
+ makes 'ld' to overlook binary objects compatibility.
+
+* Moved $(PLATFORM_LIBS) from the library group (--start-group ...
+ --end-group) outside of the group. This will make 'ld' to do
+ _multiple_ search in the library group when resolving symbol
+ references and do only a _single_ seach in libgcc.a after the group
+ search.
+
+* Fix stability problems on CPC45 board again.
+
+* Make image detection for diskboot / usbboot / scsiboot more robust
+ (also check header checksum)
+
+* Update CPC45 board configuration.
+
+* Add USB and PCI support for INKA4x0 board
+
+* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO).
+
+* Code cleanup
+
+* Patch by Robin Getz, 13 Oct 2004:
+ Add standalone application to change SMC91C111 MAC addresses,
+ see examples/README.smc91111_eeprom
+
+* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
+ Fix Flash support for ARM Integrator CP.
+
+* Patch by Richard Woodruff, 10 Jan 2005:
+ Update support for OMAP2420 (ARM11) and H4 board:
+ o clean up and add new types to H4 memory probe code.
+ o fix to work with internal boot.
+ o added PRCM config III operation.
+ o fix marginal flash timings.
+ o add revison ATAG usage.
+ o enable voltage scaling at power chip.
+ o fix compile error for i2c.
+
+* Fix network problem (error when receiving multiple ARP packets)
+
+* Patch by Daniel Poirot, 12 Oct 2004:
+ Add support for Wind River sbc405 board
+
+* Patch by Rainer Brestan, 12 Oct 2004:
+ Make examples/Makefile more robust
+
+* Patch by Sam Song, 11 October 2004:
+ - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board
+ - Adjust CPU:BUS frequency ratio 1:1 when core frequency
+ less than 50MHz
+
+* Patch by Sam Song, 10 Oct 2004:
+ Fix a parameter error in run_command() in main.c
+
+* Patch by Richard Woodruff, 01 Oct 2004:
+ add support for the TI OMAP2420 processor and its H4 reference
+ board
+
+* Patch by Christian Pellegrin, 24 Sep 2004:
+ Added support for NE2000 compatible (DP8390, DP83902) NICs.
+
+* Patch by Leif Lindholm, 23 Sep 2004:
+ add support for the AMD db1550 board
+
+* Patch by Travis Sawyer, 15 Sep 2004:
+ Add CONFIG_SERIAL_MULTI support for ppc4xx,
+ update README.serial_multi
+
+* Patches by David Snowdon, 07 Sep 2004:
+ - add u-boot.hex target in the top level Makefile
+ - add support for the UNSW/NICTA PLEB 2 board (pleb2)
+ - use -mtune=xscale and -march=armv5 options for PXA
+
+* Patch by Florian Schlote, 08 Sep 2004:
+ Add support for SenTec-COBRA5272-board (ColdFire).
+
+* Patch by Gleb Natapov, 07 Sep 2004:
+ mpc824x: set PCI latency timer to a sane value
+ (is 0 after reset).
+
+* Patch by Kurt Stremerch, 03 Sep 2004:
+ Add bitstream configuration option for fpga command (Xilinx only).
+
+* Patch by Kurt Stremerch, 03 Sep 2004:
+ Add Xilinx Spartan2E family FPGA support
+
+* Patch by Jeff Angielski, 02 Sep 2004:
+ Add Added support for H2 revision of the EP8260 board.
+ Fixed formatting for some of the EP8260 related source files.
+
+* Patch by Jon Loeliger, 02 Sep 2004:
+ Reset monitor size back to 256 so environment can be written
+ to flash on MPC85xx ADS and CDS releases.
+
+* Patch by Paolo Broggini, 02 Sep 2004:
+ Make BSS clearing on ARM systems more robust
+
+* Patch by Yue Hu and Joe, 01 Sep 2004:
+ - add PCI support for ixp425;
+ - add EEPRO100 suppor tfor ixdp425 board.
+
+* Fix problem with protected sector detection in driver/cfi_flash.c
+
+======================================================================
+Changes for U-Boot 1.1.2:
+======================================================================
+
+* Code cleanup, mostly for GCC-3.3.x
+
+* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
+ pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
+ additional ethernet addresses.
+
+* Cleanup drivers/i82365.c - avoid duplication of code
+
+* Fix bogus "cannot span across banks" flash error message
+
+* Code cleanup
+
+* Add support for CompactFlash for the CPC45 Board.
+
+* Fix problems with CMC_PU2 flash driver.
+
+* Cleanup:
+ - avoid trigraph warning in fs/ext2/ext2fs.c
+ - rename UC100 -> uc100
+
+* Add support for UC100 board
+
+* Patch by Stefan Roese, 16 Dez 2004:
+ - ext2fs support added
+ - Tundra universe support added
+ - ColdFire MCF5249 support added (no preloader needed!)
+ - MCF5249 board TASREG added
+ - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405,
+ VOM405, WUH405
+ - some esd boards updated
+ - memory commands "mdc" and "mwc" added for cyclic read/write
+ (CONFIG_MX_CYCLIC, see README for further description)
+
+* Add support for INKA4X0 board
+
+* Patch by Steven Scholz, 12 Dec 2004:
+ Fix typo in AT91 memory setup.
+
+* Patch by Martin Krause, 27 Oct 2004:
+ - add support for "STK52xx" board (including PS/2 multiplexer)
+ - add hardware detection for TQM5200
+
+* Clean up CMC PU2 flash driver
+
+* Update MAINTAINERS file
+
+* Fix bug in MPC823 LCD driver
+
+* Fix udelay() on AT91RM9200 for delays < 1 ms.
+
+* Enable long help on CMC PU2 board;
+ fix reset issue;
+ increase CPU speed from 179 to 207 MHz.
+
+* Fix smc91111 ethernet driver for Xaeniax board (need to handle
+ unaligned tail part specially).
+
+* Update for AT91RM9200DK and CMC_PU2 boards:
+ - Enable booting directly from flash
+ - fix CMC_PU2 flash driver
+
+* Fix mkimage usage message
+
+* Map SRAM on NC650 board
+
+* Work around for Ethernet problems on Xaeniax board
+
+* Patch by TsiChung Liew, 23 Sep 2004:
+ - add support for MPC8220 CPU
+ - Add support for Alaska and Yukon boards
+
+* Fix configuration for ERIC board (needs more room)
+
+* Adjust MIPS compiler options at run-time depending on tools version
+ ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new,
+ "-mcpu=4kc" for old tools)
+
+* Add passing of the command line and memory size information to the
+ kernel on xaeniax board.
+
+* Enable NAND flash support for NC650 board.
+
+* Patch by Thomas Lange 07 Oct 2004:
+ Updated README for DBAu1x00 boards to match current status
+
+* Patch by Philippe Robin, 28 Sept 2004:
+ Fix Flash support for Versatile.
+
+* Patch by Roger Blofeld, 16 Sep 2004:
+ Fix timeout for DHCP command retry
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+ Fix early serial hang when CONFIG_SERIAL_MULTI is defined.
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+ Kick watchdog when bz-decompressing
+
+* Fix CFG_HZ problems on AT91RM9200 systems
+ [Remember: CFG_HZ should be 1000 on ALL systems!]
+
+* Patch by Gridish Shlomi, 30 Aug 2004:
+ - Add support to revA version of PQ27 and PQ27E.
+ - Reverted MPC8260ADS baudrate back to original 115200
+
+* Patch by Hojin, 17 Sep 2004:
+ Fix typo in cfi_flash.c
+
+* Patch by Mark Jonas, 09 September 2004:
+ mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong
+ error message
+
+* Patch by Mark Jonas, 31 August 2004:
+ Added option CFG_XLB_PIPELINING to enable XLB pipelining. This
+ improves FTP performance for MPC5200 systems. Enabled for IceCube
+ by default.
+
+* Patch by Michael Bendzick, 30 Aug 2004:
+ - Improve platform.S code for omap1510inn that detects whether code
+ is running from SDRAM or not. Patch allows SDRAM to be configured
+ if code is running out of SRAM at 0x20000000.
+
+* Patch by Frederick Klatt, 30 Aug 2004:
+ Add support for the Wind River SBC8540/SBC8560 boards
+
+* Configure SX1 board to use drivers/cfi_flash.c
+
+* Patches by Michael Bendzick, 30 Aug 2004:
+ - Configure omap1510inn board to use drivers/cfi_flash.c
+ - Make drivers/cfi_flash.c protect environment and redundant
+ environment.
+
+* Patch by Steven Scholz, 23 Jun 2004:
+ - Add script (tools/img2brec.sh) to programm U-Boot into
+ (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L
+
+* Patches by Scott McNutt, 24 Aug 2004:
+ - Add support for Altera Nios-II processors.
+ - Add support for Psyent PCI-5441 board.
+ - Add support for Psyent PK1C20 board.
+
+* Patches by Jon Loeliger, 24 Aug 2004:
+ - Add support for the MPC8541 and MPC8555 CDS boards
+ - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
+ - Convert MPC85xxADS to use common CFI flash driver
+ - Fix PCI window on MPC85xx; remove unneeded PCI initialization
+ from board_early_init_f()
+ - Provide SW workaround for PCI initialization on 85xx CDS
+
+* Patches by George G. Davis, 24 Aug 2004:
+ - Enable ramdisk/initrd tagged param support for omap1610h2_config
+ - Remove static network setup defaults from mx1ads_config
+ - update ARM boards to use constants from mach-types.h
+
+* Patch by Gary Jennejohn, 04 Oct 2004:
+ - fix I2C on at91rm9200
+ - add support for Ricoh RS5C372A RTC
+
+* Patch by Gary Jennejohn, 01 Oct 2004:
+ - add support for CMC PU2 board
+ - add support for I2C on at91rm9200
+
+* Patch by Gary Jennejohn, 28 Sep 2004:
+ fix baudrate handling on at91rm9200
+
+* Patch by Yuli Barcohen, 22 Aug 2004:
+ - remove ZPC.1900 board-specific flash driver;
+ switch the port to generic CFI driver;
+ - port clean-up
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+ Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB
+
+* Clean up tools/bmp_logo.c to not add trailing white space
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+ - Group common framebuffer functions in common/lcd.c
+ - Group common framebuffer macros and #defines in include/lcd.h
+ - Provide calc_fbsize() for video ATAG
+
+* Patch by Sam Song, 21 August 2004:
+ - Fix a typo in README
+ - Align "(RO)" output for "flinfo" after "protect on"
+ - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency
+ ratio 1:1 when core frequency less than 50MHz
+
+* Patches by Hinko Kocevar, 21 Aug 2004:
+ - fix some "use of label at end of compound statement" warnings
+ - Define type of LCD panel on lubbock board if CONFIG_LCD is used
+
+* Patch by Steven Scholz, 16 Aug 2004:
+ - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
+ - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
+ - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
+ - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
+ into cpu/arm920t/$(SOC)/
+
+* Patches by Sean Chang, 09 Aug 2004:
+ - Added support for both 8 and 16 bit mode access to System ACE CF
+ through MPU.
+ - Fixed missing System ACE CF device during get FAT partition info
+ in fat_register_device function.
+ - Enabled System ACE CF support on ML300.
+
+* Patch by Sean Chang, 09 Aug 2004:
+ Synch defines for saveenv and do_saveenv functions so they get
+ compiled under the same statement.
+
+* Patch by Sean Chang, 09 Aug 2004:
+ - Added I2C support for ML300.
+ - Added support for ML300 to read out its environment information
+ stored on the EEPROM.
+ - Added support to use board specific parameters as part of
+ U-Boot's environment information.
+ - Updated MLD files to support configuration for new features
+ above.
+
+* Patches by Travis Sawyer, 05 Aug 2004:
+ - Remove incorrect bridge settings for eth group 6
+ - Add call to setup bridge in ppc_440x_eth_initialize
+ - Fix ppc_440x_eth_init to reset the phy only if its the
+ first time through, otherwise, just check the phy for the
+ autonegotiated speed/duplex. This allows the use of netconsole
+ - only print the speed/duplex the first time the phy is reset.
+
+* Patch by Shlomo Kut, 29 Mar 2004:
+ Add support for MKS Instruments "Quantum" board
+
+* Fix build problem with Cogent boards;
+ avoid using <asm/byteorder.h> when using the host compiler
+
+* Patch by Ganapathi C, 04 Aug 2004:
+ Fix NFS timeout issue
+
+* Patch by Yuli Barcohen, 19 Jul 2004:
+ - Fix host tools building in Cygwin environment
+ - Fix header files search order for host tools
+
+* Patch by Tom Armistead, 19 Jul 2004:
+ Fix kgdb.S support for 74xx_75x cpu
+
+* Patch by Jon Loeliger, 15 Jul 2004:
+ Fix MPC85xx I2C driver
+
+* Fix problems with CDROM drive as slave device on Lite5200 IDE bus.
+
+* Patch by Stephen Williams, 15 July 2004
+ Set the PCI class code for JSE board as part of PCI interface setup
+
+* Patch by Michael Bendzick, 15 Jul 2004:
+ Fix problem with writes with odd sizes in drivers/cfi_flash.c when
+ CFG_FLASH_USE_BUFFER_WRITE is set
+
+* Patch by Yuli Barcohen, 13 Jul 2004:
+ Allow clock setting on MPC866/MPC885 series chips according to
+ environment variable `cpuclk'
+
+* Patch by Yuli Barcohen, 20 Apr 2004:
+ Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
+
+* Patch by Vincent Dubey, 24 Sep 2004:
+ Add support for xaeniax board
+
+* Add comment about non-GPL character of standalone applications to
+ COPYING file
+
+* Fix FEC ethernet problem on NSCU board.
+
+* Patch by Gary Jennejohn, 09 Sep 2004:
+ allow to use USART1 as console port on at91rm9200dk boards
+
+* Patch by Stefan Roese, 16 Sep 2004:
+ Update AR405 board.
+
+* Fix SysClk handling for PPChameleon and CATcenter boards
+
+* Patch by Detlev Zundel, 08 Sep 2004:
+ Update etags build target
+
+* Improve NetConsole support: add support for broadcast destination
+ address and buffered input.
+
+* Cleanup compiler warnings for GCC 3.3.x and later
+
+* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
+
+* Add support for IDS "NC650" board
+
+* Add automatic update support for LWMON board
+
+* Clear Block Lock-Bits when erasing flash on LWMON board.
+
+* Fix return code of "fatload" command
+
+* Enable MSDOS/VFAT filesystem support for LWMON board
+
+* Patch by Martin Krause, 03 Aug 2004:
+ change timing for SM501 graphics controller on TQM5200 module
+
+* Patch by Mark Jonas, 13 July 2004:
+ - Total5200 LCD now run in little endian mode. Endianess conversion
+ is done in hardware.
+ - Removed last reference to "console" environment variable.
+
+* Patches by Lars Munch, 12 Jul 2004:
+ - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
+ board specific
+ - split out the LXT971A PHY from ns_9750_eth.h
+ - split the dm9161 phy part out of at91rm9200_ether.c
+
+* Patch by Andreas Engel, 12 Jul 2004:
+ Replaced hardcoded PL011 clock frequency with config variable.
+ Fixed wrong CONFIG_CMD_DFL doc.
+
+* Patch by Thomas Viehweger, 09 Jun 2004:
+ make it possible to remove chpart when there is only one partition
+
+* Add support for console over UDP (compatible to Ingo Molnar's
+ netconsole patch under Linux)
+
+* Patch by Jon Loeliger, 16 Jul 2004:
+ - support larger DDR memories up to 2G on the PC8540/8560ADS and
+ STXGP3 boards
+ - Made MPC8540/8560ADS be 33Mhz PCI by default.
+ - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
+ and CONFIG_L2_INIT_RAM options.
+ - Refactor Local Bus initialization out of SDRAM setup.
+ - Re-implement new version of LBC11/DDR11 errata workarounds.
+ - Moved board specific PCI init parts out of CPU directory.
+ - Added TLB entry for PCI-1 IO Memory
+ - Updated README.mpc85xxads
+
+* Patch by Sascha Hauer, 28 Jun:
+ - add generic support for Motorola i.MX architecture
+ - add support for mx1ads, mx1fs2 and scb9328 boards
+
+* Patches by Marc Leeman, 23 Jul 2004:
+ - Add define for the PCI/Memory Buffer Configuration Register
+ - corrected comments in cpu/mpc824x/cpu_init.c
+
+* Add support for multiple serial interfaces
+ (for example to allow modem dial-in / dial-out)
+
+* Patch by Stefan Roese, 15 Jul 2004:
+ cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
+
+* Fix NSCU config; add ethernet wakeup code.
+
+* Add link for preloader for Motorola ColdFire to README.m68k
+
+* Patch by Michael Bendzick, 12 Jul 2004:
+ fix output formatting in drivers/cfi_flash.c
+
+* Patch by Mark Jonas, 02 Jul 2004:
+ Fix lowboot (again) on MPC5xxx
+
+* Patch by Curt Brune, 07 Jul 2004:
+ relocate exception vectors on arm720t if needed
+
+* Patch by George G. Davis, 06 Jul 2004:
+ - update mach-types.h to latest arm.linux.org.uk master list
+ - Set correct OMAP1610 bi_arch_number for build target
+
+* Patch by Curt Brune, 06 Jul 2004:
+ evb4510: add support for timer interrupt; cleanup
+
+* Patch by Dan Poirot, 06 Jul 2004:
+ Fix sbc8260 environment variables
+
+* Cleanup redundand "console" environment variable
+
+* Patch by Mark Jonas, 05 Jul 2004:
+ add support for the Total5100's and Total5200's LCD screen
+
+* Patches by Dan Eisenhut, 01 Jul 2004:
+ - README fixes.
+ - Move doc2000.h include to prevent compiler warning on some boards
+
+* Patch by Mark Jonas, 01 Jul 2004:
+ Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
+ MGT5100 and MPC5200 based Freescale platforms.
+
+* Patch by Philippe Robin, 01 Jul 2004:
+ Add initialization for Integrator and versatile board files.
+
+* Patch by Hinko Kocevar, 01 Jun 2004:
+ Fix VFD FB allocation, add LCD FB allocation on ARM
+
+* Patch by Martin Krause, 30 Jun 2004:
+ Add support for TQM5200 board
+
+* Patch by Martin Krause, 29 Jun 2004:
+ Add loopw command: infinite write loop on address range
+
+* Patches by Yasushi Shoji, 29 Jun 2004:
+ - add empty include/asm-microblaze/processor.h
+ - add to CREDITS and MAINTAINERS
+ - add gd initialization
+ - add MicroBlaze and SUZAKU board to MAKEALL script
+ - add reset support for SUZAKU
+ - add flush_cache() for MicroBlaze
+ - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed
+ size flash memory on SUZAKU
+
+* Patch by Prakash Kumar, 27 Jun 2004:
+ Add support for the PXA250 based Intrinsyc Cerf board.
+
+* Patch by Yasushi Shoji, 27 Jun 2004:
+ fix comment in include/common.h
+
+* Rename SBC8560 into sbc8560 for consistency
+
+* Patch by Daniel Poirot, 24 Jun 2004:
+ Add support for Wind River's sbc8240 board
+
+* Patches by Yasushi Shoji, 26 Jun 2004:
+ - drivers/serial_xuartlite.c: fix "return 0" in void function
+ - add microblaze support to mkimage tool
+
+* Patch by Fred Klatt, 25 Jun 2004:
+ Add support for WindRiver's sbc8560 board
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004
+ Small Bugs fixes for "at91rm9200dk" board:
+ - Timing modifications for SPI DataFlash access
+ - Fix NAND flash detection bug
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004:
+ Add Support for Flash AT49BV6416 for AT91RM9200DK board
+
+* Patch by Jon Loeliger, 17 June 2004:
+ Completion of the 8540ADS/8560ADS updates:
+ Fix some PCI and Rapid I/O memory maps,
+ Initialize both TSEC 1 and 2,
+ Initialize SDRAM
+ Update MAINTAINER for 85xx boards and README.mpc85xxads
+
+* Patch by Yuli Barcohen, 16 Jun 2004:
+ Remove obsolete AdderII port which was superseded by unified
+ AdderII/Adder87x port
+
+* Patch by Ladislav Michl, 16 Jun 2004:
+ Fix gcc-3.3.3 warnings for smc91111.c
+
+* Patch by Stefan Roese, 02 Jul 2004:
+ - Fix bug in 405 ethernet driver; allocated data not cleared!
+ - Fix problem in 405 i2c driver; don't try to print without console!
+
+* Patch by Paul Ruhland, 11 Jun 2004:
+ Remove debug code from 'board/lpd7a40x/flash.c'
+
+* Patch by Andrea Marson, 11 Jun 2004:
+ Update for PPChameleon board:
+ - support for SysClk @ 25MHz
+ - support for Silicon Motion SM712 VGA controller
+ - some clean ups
+
+* Patches by Richard Woodruff, 10 Jun 2004:
+ - fix problems with examples/stubs.c for GCC >= 3.4
+ - fix problems with gd initialization
+
+* Patch by Curt Brune, 17 May 2004:
+ - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+ - Add support for ESPD-Inc. EVB4510 Board
+
+* Patch by Marc Leeman, 11 May 2004:
+ Fix for MPC8245 - reading PPC Memory from another device with the
+ PPC as PCI target device corrupts data due to interenal hardware
+ buffering.
+
+* Fix "cls" command when used with splash screen
+
+* Increase NFS download timeout (now 1 min - 10 sec is to short for a
+ slow download of a big image)
+
+* Add "cls" function to MPC823 LCD driver so we can reinitialize the
+ display even after showing a bitmap
+
+* Patch by Josef Wagner, 04 Jun 2004:
+ - DDR Ram support for PM520 (MPC5200)
+ - support for different flash types (PM520)
+ - USB / IDE / CF-Card / DiskOnChip support for PM520
+ - 8 bit boot rom support for PM520/CE520
+ - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
+ - I2C and RTC support for CPC45
+ - support of new flash type (28F160C3T) for CPC45
+
+* Fix flash parameters passed to Linux for PPChameleon board
+
+* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
+
+* Patch by Paul Ruhland, 10 Jun 2004:
+ fix support for Logic SDK-LH7A404 board and clean up the
+ LH7A404 register macros.
+
+* Patch by Matthew McClintock, 10 Jun 2004:
+ Modify code to select correct serial clock on Sandpoint8245
+
+* Patch by Robert Schwebel, 10 Jun 2004:
+ Add support for Intel K3 strata flash.
+
+* Patch by Thomas Brand, 10 Jun 2004:
+ Fix "loads" command on DK1S10 board
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+ Add support for 8MB flash SIMM and JFFS2 file system on
+ Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+ Add support for Analogue&Micro Adder87x and the older AdderII board.
+
+* Patch by Ming-Len Wu, 09 Jun 2004:
+ Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
+
+* Patch by Sam Song, 09 Jun 2004:
+ - Add support for RPXlite_DW board
+ - Update FLASH driver for 4*AM29DL323DB90VI
+ - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
+
+* Patch by Mark Jonas, 08 June 2004:
+ - Make MPC5200 boards evaluate the SVR to print processor name and
+ version in checkcpu() (cpu/mpc5xxx/cpu.c).
+
+* Patch by Kai-Uwe Bloem, 06 May 2004:
+ Fix endianess problem in cramfs code
+
+* Patch by Tom Armistead, 04 Jun 2004:
+ Add support for MAX6900 RTC
+
+* Patches by Ladislav Michl, 03 Jun 2004:
+ - fix cfi_flash.c on LE systems
+ - let 'make mrproper' delete u-boot.img as well
+ - turn printf into debug in cfi_flash.c
+
+* Patch by Kurt Stremerch, 28 May 2004:
+ Add support for Exys XSEngine board
+
+* Patch by Martin Krause, 27 May 2004:
+ Fix a MPC5xxx I2C timing issue in i2c_probe().
+
+* Patch by Leif Lindholm, 27 May 2004:
+ Fix board_init_f() for dbau1x00 board.
+
+* Patch by Imre Deak, 26 May 2004:
+ On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
+ Set flash base accordingly, and decide whether to do or skip board
+ specific setup steps.
+
+* Patch by Josef Baumgartner, 26 May 2004:
+ Add missing define in include/asm-m68k/global_data.h
+
+* Patch by Josef Baumgartner, 25 May 2004:
+ Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
+
+* Patch by Paul Ruhland, 24 May 2004:
+ fix SDRAM initialization for LPD7A400 board.
+
+* Patch by Jian Zhang, 20 May 2004:
+ add support for environment in NAND flash
+
+* Patch by Yuli Barcohen, 20 May 2004:
+ Add support for Interphase iSPAN boards.
+
+* Patches by Paul Ruhland, 17 May 2004:
+ - Add I/O functions to the smc91111 ethernet driver to support the
+ Logic LPD7A40x boards.
+ - Add support for the Logic Zoom LH7A40x based SDK board(s),
+ specifically the LPD7A400.
+
+* Patches by Robert Schwebel, 15 May 2004:
+ - call MAC address reading code also for SMSC91C111;
+ - make SMSC91C111 timeout configurable, remove duplicate code
+ - fix get_timer() for PXA
+ - update doc/README.JFFS2
+ - use "bootfile" env variable also for jffs2
+
+* Patch by Tolunay Orkun, 14 May 2004:
+ Add support for Cogent CSB472 board (8MB Flash Rev)
+
+* Patch by Thomas Viehweger, 14 May 2004:
+ - flash.h: more flash types added
+ - immap_8260.h: some bits added (useful for RMII)
+ - cmd_coninfo.c: typo corrected, printf -> puts
+ - reduced size by replacing spaces with tab
+
+* Patch by Robert Schwebel, 13 May 2004:
+ Add 'imgextract' command: extract one part of a multi file image.
+
+* Patches by Jon Loeliger, 11 May 2004:
+ Dynamically handle REV1 and REV2 MPC85xx parts.
+ (Jon Loeliger, 10-May-2004).
+ New consistent memory map and Local Access Window across MPC85xx line.
+ New CCSRBAR at 0xE000_0000 now.
+ Add RAPID I/O memory map.
+ New memory map in README.MPC85xxads
+ (Kumar Gala, 10-May-2004)
+ Better board and CPU identification on MPC85xx boards at boot.
+ (Jon Loeliger, 10-May-2004)
+ SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
+ Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
+ (Jim Robertson, 10-May-2004)
+ Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
+ Supports multiple PHYs.
+ (Andy Fleming, 10-May-2004)
+ Some README.MPC85xxads updates.
+ (Kumar Gala, 10-May-2004)
+ Copyright updates for "Freescale"
+ (Andy Fleming, 10-May-2004)
+
+* Patch by Stephen Williams, 11 May 2004:
+ Add flash support for ST M29W040B
+ Reduce JSE specific flash.c to remove dead code.
+
+* Patch by Markus Pietrek, 04 May 2004:
+ Fix clear_bss code for ARM systems (all except s3c44b0 which
+ doesn't clear BSS at all?)
+
+* Fix "ping" problem on INC-IP board. Strange problem:
+ Sometimes the store word instruction hangs while writing to one of
+ the Switch registers, but only if the next instruction is 16-byte
+ aligned. Moving the instruction into a separate function somehow
+ makes the problem go away.
+
+* Patch by Rishi Bhattacharya, 08 May 2004:
+ Add support for TI OMAP5912 OSK Board
+
+* Patch by Sam Song May, 07 May 2004:
+ Fix typo of UPM table for rmu board
+
+* Patch by Pantelis Antoniou, 05 May 2004:
+ - Intracom board update.
+ - Add Codec POST.
+
+* Add support for the second Ethernet interface for the 'PPChameleon'
+ board.
+
+* Patch by Dave Peverley, 30 Apr 2004:
+ Add support for OMAP730 Perseus2 Development board
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+ Fix flash chip-select (OR0) option register setting on FADS boards.
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+ Report MII network speed and duplex setting properly when
+ auto-negotiate is not enabled.
+
+* Patch by Jarrett Redd, 29 Apr 2004:
+ Fix hang on reset on Ocotea board due to flash in wrong mode.
+
+* Patch by Dave Peverley, 29 Apr 2004:
+ add MAC address detection to smc91111 driver
+
+* Patch by David Müller, 28 Apr 2004:
+ fix typo in lib_arm/board.c
+
+* Patch by Tolunay Orkun, 20 Apr 2004:
+ - README update: add CONFIG_CSB272 and csb272_config
+ - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
+ i2cfast environment variable
+
+* Patch by Yuli Barcohen, 19 Apr 2004:
+ - Rename DUET_ADS to MPC885ADS
+ - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
+ - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
+ - Clean up FADS family port to use the new defines
+
+* Fix PCI support on CPC45 board
+
+* Patch by Scott McNutt, 25 Apr 2004:
+ Add Nios GDB/JTAG Console support:
+ - Add stubs to support gdb via JTAG.
+ - Add support for console over JTAG.
+ - Minor cleanup.
+
+* Add support for CATcenter board (based on PPChameleon ME module)
+
+* Patch by Klaus Heydeck, 12 May 2004:
+ Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
+ load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
+ various changes to KUP4 board specific files
+
+* Fix minor network problem on MPC5200: need some delay between
+ resetting the PHY and sending the first packet. Implemented in a
+ "natural" way by invoking the PHY reset and initialization code
+ only once after power on vs. each time the interface is brought up.
+
+* Add some limited support for low-speed devices to SL811 USB controller
+ (at least "usb reset" now passes successfully and "usb info" displays
+ correct information)
+
+* Change init sequence for multiple network interfaces: initialize
+ on-chip interfaces before external cards.
+
+* Fix memory leak in the NAND-specific JFFS2 code
+
+* Fix SL811 USB controller when attached to a USB hub
+
+* Fix config option spelling in PM520 config file
+
+* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
+ patches by Pantelis Antoniou, 30 Mar 2004)
+
+* Fix minor NAND JFFS2 related issue
+
+* Fixes for SL811 USB controller:
+ - implement workaround for broken memory stick
+ - improve error handling
+
+* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
+ cope with congested networks.
+
+======================================================================
+Changes for U-Boot 1.1.1:
+======================================================================
+
+* Patch by Travis Sawyer, 23 Apr 2004:
+ Fix VSC/CIS 8201 phy descrambler interoperability timing due to
+ errata from Vitesse Semiconductor.
+
+* Patch by Philippe Robin, 22 Apr 2004:
+ Fix ethernet configuration for "versatile" board
+
+* Patch by Kshitij Gupta, 21 Apr 2004:
+ Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
+
+* Patch by Steven Scholz, 24 Feb 2004:
+ Fix a bug in AT91RM9200 ethernet driver:
+ The MII interface is now initialized before accessing the PHY.
+
+* Patch by John Kerl, 19 Apr 2004:
+ Use U-boot's miiphy.h for PHY register names, rather than
+ introducing a new header file.
+
+* Update pci_ids.h from linux-2.4.26
+
+* Patch by Masami Komiya, 19 Apr 2004:
+ Fix problem cause by VLAN function on little endian architecture
+ without VLAN environment
+
+* Clean up the TQM8xx_YYMHz configurations; allow to use the same
+ binary image for all clock frequencies. Implement run-time
+ optimization of flash access timing based on the actual bus
+ frequency.
+
+* Modify KUP4X board configuration to use SL811 driver for USB memory
+ sticks (including FAT / VFAT filesystem support)
+
+* Add SL811 Host Controller Interface driver for USB
+
+* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README
+
+* Patch by Pantelis Antoniou, 19 Apr 2004:
+ Allow to use shell style syntax (i. e. ${var} ) with standard parser.
+ Minor patches for Intracom boards.
+
+* Patch by Christian Pell, 19 Apr 2004:
+ cleanup support for CF/IDE on PCMCIA for PXA25X
+
+* Temporarily disabled John Kerl's extended MII command code because
+ "miivals.h" is missing
+
+* Patches by Mark Jonas, 13 Apr 2004:
+ - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
+ - Add sync instructions to IceCube SDRAM init code
+ - Move SDRAM chip constants into seperate include files
+ - Unify DDR and SDR initialization code
+ - Unify all IceCube (Lite5xxx) target names
+
+* Patch by John Kerl, 16 Apr 2004:
+ Enable ranges in mii command, e.g. mii read 0-1f 0 or
+ mii read 4-7 18-1a. Also add mii dump subcommand for
+ pretty-printing standard regs 0-5.
+
+* Patch by Stephen Williams, 16 April 2004:
+ fix typo in JSE.h; update MAINTAINERS
+
+* Patch by Matthew S. McClintock, 14 Apr 2004:
+ fix initdram function for utx8245 board
+
+* Patch by Markus Pietrek, 14 Apr 2004:
+ use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag
+
+* Patch by Reinhard Meyer, 18 Apr 2004:
+ provide the IDE Reset Function for EMK 5200 boards
+
+* Patch by Masami Komiya, 12 Apr 2004:
+ fix pci_hose_write_config_{byte,word}_via_dword problems
+
+* Patch by Sangmoon Kim, 12 Apr 2004:
+ Update max RAM size for debris board
+
+* Patch by Travis Sawyer, 08 Apr 2004:
+ Add TLB entry for second DIMM slot on ocotea
+
+* Patch by Masami Komiya, 08 Apr 2004:
+ add RTL8169 network driver
+
+* Patch by Dan Malek, 07 Apr 2004:
+ - Add support for RPC/STx GP3, Motorola 8560 board
+ - Update 85xx TSEC driver so it searches MII for first available PHY
+ and uses that one.
+ - Add functions to support console MII commands.
+
+* Patch by Tolunay Orkun, 07 Apr 2004:
+ Move initialization of bi_iic_fast[]
+ from board_init_f() to board_init_r()
+
+* Patch by Yasushi Shoji, 07 Apr 2004:
+ Cleanup microblaze port
+
+* Patch by Sangmoon Kim, 07 Apr 2004:
+ Add auto SDRAM module detection for Debris board
+
+* Patch by Rune Torgersen, 06 Apr 2004:
+ - Fix some PCI problems on the MPC8266ADS board
+ - Fix the location of some PCI entries in the immap structure
+
+* Patch by Yasushi Shoji, 07 Apr 2004:
+ - add support for microblaze processors
+ - add support for AtmarkTechno "suzaku" board
+
+* Configure PPChameleon board to use redundand environment in flash
+
+* Configure PPChameleon board to use JFFS2 NAND support.
+
+* Added support for JFFS2 filesystem (read-only) on top of NAND flash
+
+* Patch by Rune Torgersen, 16 Apr 2004:
+ LBA48 fixes
+
+* Patches by Pantelis Antoniou, 16 Apr 2004:
+ - add support for a new version of an Intracom board and fix
+ various other things on others.
+ - add verify support to the crc32 command (define
+ CONFIG_CRC32_VERIFY to enable it)
+ - fix FEC driver for MPC8xx systems:
+ 1. fix compilation problems for boards that use dynamic
+ allocation of DPRAM
+ 2. shut down FEC after network transfers
+ - HUSH parser fixes:
+ 1. A new test command was added. This is a simplified version of
+ the one in the bourne shell.
+ 2. A new exit command was added which terminates the current
+ executing script.
+ 3. Fixed handing of $? (exit code of last executed command)
+ - Fix some compile problems;
+ add "once" functionality for the netretry variable
+
+* Patch by George G. Davis, 02 Apr 2004:
+ add support for Intel Assabet board
+
+* Patch by Stephen Williams, 01 Apr 2004:
+ Add support for Picture Elements JSE board
+
+* Patch by Christian Pell, 01 Apr 2004:
+ Add CompactFlash support for PXA systems.
+
+* Patches by Pantelis Antoniou, 30 Mar 2004:
+ - add auto-complete support to the U-Boot CLI
+ - add support for NETTA and NETPHONE boards; fix NETVIA board
+ - add support for the Epson 156x series of graphical displays
+ (These displays are serial and not suitable for using a normal
+ framebuffer console on them)
+ - add infrastructure needed in order to POST any DSPs in a board
+ - improve and fix various things in the MPC8xx FEC driver:
+ 1. The new 87x and 88x series of processors have two FECs,
+ and the new driver supports them both.
+ 2. Another change in the 87x/88x series is support for
+ the RMII (Reduced MII) interface. However numerous
+ changes are needed to make it work since the PHYs
+ are connected to the same lines. That means that
+ you have to address them correctly over the MII
+ interface.
+ 3. We now correctly match the MII/RMII interface
+ configuration to what the PHY reports.
+ - Fix problem when readingthe MII status register. Due to the
+ internal design of many PHYs you have to read the register
+ twice. The problem is more apparent in 10Mbit mode.
+ - add new mode ".jffs2s" for reading from a NAND device: it just
+ skips over bad blocks.
+ - add networking support for VLANs (802.1q), and CDP (Cisco
+ Discovery Protocol)
+ - some minor patches / cleanup
+
+* Patch by Yuli Barcohen, 28 Mar 2004:
+ - Add support for MPC8272 family including MPC8247/8248/8271/8272
+ - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
+ - Change configuration method for MPC8260ADS family
+
+* add startup code to clear the BSS of standalone applications
+
+* Fix if / elif handling bug in HUSH shell
+
+======================================================================
+Changes for U-Boot 1.1.0:
+======================================================================
+
+* Patch by Mark Jonas: Remove config.tmp files only when
+ unconfiguring the board
+
+* Adapt RMU board for bigger flash memory
+
+* Patch by Klaus Heydeck, 13 Mar 2003:
+ Add support for KUP4X Board
+
+* Patch by Pavel Bartusek, 21 Mar 2004
+ Add Reiserfs support
+
+* Patch by Hinko Kocevar, 20 Mar 2004
+ - Add auto-release for SMSC LAN91c111 driver
+ - Add save/restore of PTR and PNR regs as suggested in datasheet
+
+* Patch by Stephen Williams, 19 March 2004
+ Increase speed of sector reads from SystemACE,
+ shorten poll timeout and remove a useless reset
+
+* Patch by Tolunay Orkun, 19 Mar 2004:
+ Make GigE PHY 1000Mbps Speed/Duplex detection conditional
+ (CONFIG_PHY_GIGE)
+
+* Patch by Brad Kemp, 18 Mar 2004:
+ prevent machine checks during a PCI scan
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ Fix string cleaning in IDE identification
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ - Unify video mode handling for Chips & Technologies 69000 Video
+ chip and Silicon Motion SMI 712/710/810 Video chip
+ - Add selection of the video output (CRT or LCD) via 'videoout'
+ environment variable for the Silicon Motion
+ - README update
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ include/common.h typo fix
+
+* Patches by Tolunay Orkun, 17 Mar 2004:
+ - Add support for bd->bi_iic_fast[] initialization via environment
+ variable "i2cfast" (CONFIG_I2CFAST)
+ - Add "i2cfast" u-boot environment variable support for csb272
+
+* Patch by Carl Riechers, 17 Mar 2004:
+ Ignore '\0' characters in console input for use with telnet and
+ telco pads.
+
+* Patch by Leon Kukovec, 17 Mar 2004:
+ typo fix for strswab prototype #ifdef
+
+* Patches by Thomas Viehweger, 16 Mar 2004:
+ - show PCI clock frequency on MPC8260 systems
+ - add FCC_PSMR_RMII flag for HiP7 processors
+ - in do_jffs2_fsload(), take load address from load_addr if not set
+ explicit, update load_addr otherwise
+ - replaced printf by putc/puts when no formatting is needed
+ (smaller code size, faster execution)
+
+* Patch by Phillippe Robin, 16 Mar 2004:
+ avoid dereferencing NULL pointer in lib_arm/armlinux.c
+
+* Patch by Stephen Williams, 15 Mar 2004:
+ Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation
+
+* Patch by Tolunay Orkun, 15 Mar 2004:
+ Initialize bi_opbfreq to real OPB frequency via get_OPB_freq()
+
+* Patch by Travis Sawyer, 15 Mar 2004:
+ Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port
+
+* Add start-up delay to make sure power has stabilized before
+ attempting to switch on USB on SX1 board.
+
+* Patch by Josef Wagner, 18 Mar 2004:
+ - Add support for MicroSys XM250 board (PXA255)
+ - Add support for MicroSys PM828 board (MPC8280)
+ - Add support for 32 MB Flash on PM825/826
+ - new SDRAM refresh rate for PM825/PM826
+ - added support for MicroSys PM520 (MPC5200)
+ - replaced Query by Identify command in CPU86/flash.c
+ to support 28F160F3B
+
+* Fix wrap around problem with udelay() on ARM920T
+
+* Add support for Macronix flash on TRAB board
+
+* Patch by Pierre Aubert, 15 Mar 2004:
+ Fix buffer overflow in IDE identification
+
+* Fix power-off of LCD for out-of-band temperatures on LWMON board
+
+* Remove redundand #define in IceCube.h
+
+* Patch by Steven Scholz, 27 Feb 2004:
+ - Adding get_ticks() and get_tbclk() for AT91RM9200
+ - Many white space fixes in cpu/at91rm9200/interrupts.c
+
+* Patches by Steven Scholz, 20 Feb 2004:
+ some cleanup in AT91RM9200 related code
+
+* Patches by Travis Sawyer, 12 Mar 2004:
+ - Fix Gigabit Ethernet support for 440GX
+ - Add Gigabit Ethernet Support to MII PHY utilities
+
+* Patch by Brad Kemp, 12 Mar 2004:
+ Fixes for drivers/cfi_flash.c:
+ - Better support for x8/x16 implementations
+ - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
+ - Added defines for AMD command and address constants
+
+* Patch by Leon Kukovec, 12 Mar 2004:
+ Fix get_dentfromdir() to correctly handle deleted dentries
+
+* Patch by George G. Davis, 11 Mar 2004:
+ Remove hard coded network settings in TI OMAP1610 H2
+ default board config
+
+* Patch by George G. Davis, 11 Mar 2004:
+ add support for ADS GraphicsClient+ board.
+
+* Patch by Pierre Aubert, 11 Mar 2004:
+ - add bitmap command and splash screen support in cfb console
+ - add [optional] origin in the bitmap display command
+
+* Patch by Travis Sawyer, 11 Mar 2004:
+ Fix ocotea board early init interrupt setup.
+
+* Patch by Thomas Viehweger, 11 Mar 2004:
+ Remove redundand code; add PCI-specific bits to include/mpc8260.h
+
+* Patch by Stephan Linz, 09 Mar 2004
+ - Add support for the SSV ADNP/ESC1 (Nios Softcore)
+
+* Patch by George G. Davis, 9 Mar 2004:
+ fix recent build failure for SA1100 target
+
+* Patch by Travis Sawyer, 09 Mar 2004:
+ Support native interrupt mode for the IBM440GX.
+ Previously it was running in 440GP compatibility mode.
+
+* Patch by Philippe Robin, 09 Mar 2004:
+ Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
+ Platform support.
+
+* Patch by Masami Komiya, 08 Mar 2004:
+ Don't overwrite server IP address or boot file name
+ when the boot server does not return values
+
+* Patch by Tolunay Orkun, 5 Mar 2004:
+ Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
+
+* Patch by Tolunay Orkun, 5 Mar 2004:
+ Fix early board initialization for Cogent CSB272 board
+
+* Patch by Ed Okerson, 3 Mar 2004:
+ fix CFI flash writes for little endian systems
+
+* Patch by Reinhard Meyer, 01 Mar 2004:
+ generalize USB and IDE support for MPC5200 with according
+ changes to IceCube.h and TOP5200.h
+ add Am29LV256 256 MBit FLASH support for TOP5200 boards
+ add info about USB and IDE to README
+
+* Patch by Yuli Barcohen, 4 Mar 2004:
+ Fix problems with GCC 3.3.x which changed handling of global
+ variables explicitly initialized to zero (now in .bss instead of
+ .data as before).
+
+* Patch by Leon Kukovec, 02 Mar 2004:
+ add strswab() to fix IDE LBA capacity, firmware and model numbers
+ on little endian machines
+
+* Patch by Masami Komiya, 02 Mar 2004:
+ - Remove get_ticks() from NFS code
+ - Add verification of RPC transaction ID
+
+* Patch by Pierre Aubert, 02 Mar 2004:
+ cleanup for IDE and USB drivers for MPC5200
+
+* Patch by Travis Sawyer, 01 Mar 2004:
+ Ocotea:
+ - Add IBM PPC440GX Ref Platform support (Ocotea)
+ Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
+ Adapted to U-Boot and 440GX port
+ 440gx_enet.c:
+ - Add gracious handling of all Ethernet Pin Selections for 440GX
+ - Add RGMII selection for Cicada CIS8201 Gigabit PHY
+ ppc440.h:
+ - Add needed bit definitions
+ - Fix formatting
+
+* Patch by Carl Riechers, 1 Mar 2004:
+ Add PPC440GX prbdv0 divider to fix memory clock calculation.
+
+* Patch by Stephan Linz, 27 Feb 2004
+ - avoid problems for targets without NFS download support
+
+* Patch by Rune Torgersen, 27 Feb 2004:
+ - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
+ - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
+ - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)
+
+* Patch by Masami Komiya, 27 Feb 2004:
+ Fix rarpboot: add autoload by NFS
+
+* Patch by Dan Eisenhut, 26 Feb 2004:
+ fix flash_write return value in saveenv
+
+* Patch by Stephan Linz, 11 Dec 2003
+ expand config.mk to avoid trigraph warnings on NIOS
+
+* Rename "BMS2003" board into "HMI10"
+
+* SX1 patches: use "serial#" for USB serial #; use redundand environment
+ storage; auto-set console on USB port (using preboot command)
+
+* Add support for SX1 mobile phone; add support for USB-based console
+ (enable with "setenv stdout usbtty; setenv stdin usbtty")
+
+* Fix LOWBOOT configuration for MPC5200 with DDR memory
+
+* Fix SDRAM timings for LITE5200 / IceCube board
+
+* Handle Auti-MDIX / connection status for INCA-IP
+
+* Fix USB problems when attempting to read 0 bytes
+
+* Patch by Travis Sawyer, 26 Feb 2004:
+ Fix broken compile for XPEDITE1K target.
+
+* Patch by Stephan Linz, 26 Feb 2004:
+ Bug fix for NFS code on NIOS targets
+
+* Patch by Stephen Williams, 26 Feb 2004:
+ Break up SystemACE reads of large block counts
+
+* Patch by Pierre Aubert, 26 Feb 2004
+ add IDE support for MPC5200
+
+* Patch by Masami Komiya, 26 Feb 2004:
+ add autoload via NFS
+
+* Patch by Stephen Williams
+ Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
+ elsewhere in the source.
+
+* Patch by Steven Scholz, 25 Feb 2004:
+ - Timeouts in FPGA code should be based on CFG_HZ
+ - Minor cleanup in code for Altera FPGA ACEX1K
+
+* Patch by Steven Scholz, 25 Feb 2004:
+ Changed "Directory Hierarchy" section in README
+
+* Patch by Masami Komiya, 25 Feb 2004:
+ Reduce copy count in nfs_read_reply() of NFS code
+
+* Patch by Markus Pietrek, 24 Feb 2004:
+ NS9750 DevBoard added
+
+* Patch by Pierre Aubert, 24 Feb 2004
+ add USB support for MPC5200
+
+* Patch by Steven Scholz, 24 Feb 2004:
+ - fix MII commands to use values from last command
+
+* Patch by Torsten Demke, 24 Feb 2004:
+ Add support for the eXalion platform (SPSW-8240, F-30, F-300)
+
+* Patch by Rahul Shanbhag, 19 Feb 2004:
+ Fixes for for OMAP1610 board:
+ - shift some IRQ specific code to platform.S file
+ - remove duplicatewatchdog reset code from start.S
+
+* Make Auto-MDIX Support configurable on INCA-IP board
+
+* Fix license for mkimage tool
+
+* Patch by Masami Komiya, 24 Feb 2004:
+ Update NetBootFileXferSize in NFS code
+
+* Patch by Scott McNutt, 24 Feb 2004:
+ fix packet length in NFS code
+
+* Patch by Masami Komiy, 22 Feb 2004:
+ Add support for NFS for file download
+
+* Patch by Andrea Scian, 17 Feb 2004:
+ Add support for S3C44B0 processor and DAVE B2 board
+
+* Patch by Steven Scholz, 20 Feb 2004:
+ - Add support for MII commands on AT91RM9200 boards
+ - some cleanup in AT91RM9200 ethernet code
+
+* Patch by Peter Ryser, 20 Feb 2004:
+ Add support for the Xilinx ML300 platform
+
+* Patch by Stephan Linz, 17 Feb 2004:
+ Fix watchdog support for NIOS
+
+* Patch by Josh Fryman, 16 Feb 2004:
+ Fix byte-swapping for cfi_flash.c for different bus widths
+
+* Patch by Jon Diekema, 14 Jeb 2004:
+ Remove duplicate "FPGA Support" notes from the README file
+
+* Patches by Reinhard Meyer, 14 Feb 2004:
+ - update board/emk tree; use common flash driver
+ - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
+ [adapted for other PPC CPUs -- wd]
+ - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c
+
+* Patch by Jon Diekema, 13 Feb 2004:
+ Call show_boot_progress() whenever POST "FAILED" is printed.
+
+* Patch by Nishant Kamat, 13 Feb 2004:
+ Add support for TI OMAP1610 H2 Board
+ Fixes for cpu/arm926ejs/interrupt.c
+ (based on Richard Woodruff's patch for arm925, 16 Oct 03)
+ Fix for a timer bug in OMAP1610 Innovator
+ Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2
+
+* Patches by Stephan Linz, 12 Feb 2004:
+ - add support for NIOS timer with variable period preload counter value
+ - prepare POST framework support for NIOS targets
+
+* Patch by Denis Peter, 11 Feb 2004:
+ add POST support for the MIP405 board
+
+* Patch by Laurent Mohin, 10 Feb 2004:
+ Fix buffer overflow in common/usb.c
+
+* Patch by Tolunay Orkun, 10 Feb 2004:
+ Add support for Cogent CSB272 board
+
+* Patch by Thomas Elste, 10 Feb 2004:
+ Add support for NET+50 CPU and ModNET50 board
+
+* Patch by Sam Song, 10 Feb 2004:
+ Fix typos in cfi_flash.c
+
+* Patch by Leon Kukovec, 10 Feb 2004
+ Fixed long dir entry slot id calculation in get_vfatname
+
+* Patch by Robin Gilks, 10 Feb 2004:
+ add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==,
+ !=, <>, <, >, <=, >=)
+
+* Fix problem with side effects in macros in include/usb.h
+
+* Patch by David Benson, 13 Nov 2003:
+ bug 841358 - fix TFTP download size limit
+
+* Fixing bug 850768:
+ improper flush_cache() in load_serial()
+
+* Fixing bug 834943:
+ MPC8540 - missing volatile declarations
+
+* Patch by Stephen Williams, 09 Feb 2004:
+ Add support for Xilinx SystemACE chip:
+ - New files common/cmd_ace.c and include/systemace.h
+ - Hook systemace support into cmd_fat and the partition manager
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+ Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+ o 440GX:
+ - Fix PCI Indirect access for type 1 config cycles with ppc440.
+ - Add phymode for 440 enet
+ - fix pci pre init
+ o XPedite1K:
+ - Change board_pre_init to board_early_init_f
+ - Add user flash to bus controller setup
+ - Fix pci pre init
+ - Fix is_pci_host to check GPIO for monarch bit
+ - Force xpedite1k to pci conventional mode (via #define option)
+
+* Patch by Brad Kemp, 4 Feb 2004:
+ - handle the machine check that is generated during the PCI scans
+ on 82xx processors.
+ - define the registers used in the IMMR by the PCI subsystem.
+
+* Patch by Pierre Aubert, 03 Feb 2004:
+ cpu/mpc5xxx/start.S: copy MBAR into SPR311
+
+* Patch by Jeff Angielski, 03 Feb 2004:
+ Fix copy & paste error in cpu/mpc8260/pci.c
+
+* Patch by Reinhard Meyer, 24 Jan 2004:
+ Fix typo in cpu/mpc5xxx/pci_mpc5200.c
+
+* Add Auto-MDIX support for INCA-IP
+
+* Some code cleanup
+
+* Patch by Josef Baumgartner, 10 Feb 2004:
+ Fixes for ColdFire port
+
+* Patch by Brad Kemp, 11 Feb 2004:
+ Fix CFI flash driver problems
+
+* Make sure to use a bus clock divider of 2 only when running TQM8xxM
+ modules at CPU clock frequencies above 66 MHz.
+
+* Optimize flash programming speed for LWMON (by another 100% :-)
+
+* Patch by Jian Zhang, 3 Feb 2004:
+ - Changed the incorrect FAT12BUFSIZE
+ - data_begin in fsdata can be negative. Changed it to be short.
+
+* Patches by Stephan Linz, 30 Jan 2004:
+ 1: - board/altera/common/flash.c:flash_erase():
+ o allow interrupts befor get_timer() call
+ o check-up each erased sector and avoid unexpected timeouts
+ - board/altera/dk1c20/dk1s10.c:board_early_init_f():
+ o enclose sevenseg_set() in cpp condition
+ - remove the ASMI configuration for DK1S10_standard_32 (never present)
+ - fix some typed in mistakes in the NIOS documentation
+ 2: - split DK1C20 configuration into several header files:
+ o two new files for each NIOS CPU description
+ o U-Boot related part is remaining in DK1C20.h
+ 3: - split DK1S10 configuration into several header files:
+ o two new files for each NIOS CPU description
+ o U-Boot related part is remaining in DK1S10.h
+ 4: - Add support for the Microtronix Linux Development Kit
+ NIOS CPU configuration at the Altera Nios Development Kit,
+ Stratix Edition (DK-1S10)
+ 5: - Add documentation for the Altera Nios Development Kit,
+ Stratix Edition (DK-1S10)
+ 6: - Add support for the Nios Serial Peripharel Interface (SPI)
+ (master only)
+ 7: - Add support for the common U-Boot SPI framework at
+ RTC driver DS1306
+
+* Patch by Rahul Shanbhag, 28 Jan 2004:
+ Fix flash protection/locking handling for OMAP1610 innovator board.
+
+* Patch by Rolf Peukert, 28 Jan 2004:
+ fix flash write problems on CSB226 board (write with 32 bit bus width)
+
+* Patches by Mark Jonas, 16 Jan 2004:
+ - fix rounding error when calculating baudrates for MPC5200 PSCs
+ - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
+ time which is not supported
+
+* Patch by Yuli Barcohen, 26 Jan 2004:
+ Allow bzip2 compression for small memory footprint boards
+
+* Patch by Brad Kemp, 21 Jan 2004:
+ Add support for CFI flash driver for both the Intel and the AMD
+ command sets.
+
+* Patch by Travis Sawyer, 20 Jan 2004:
+ Fix pci bridge auto enumeration of sibling p2p bridges.
+
+* Patch by Tolunay Orkun, 12 Jan 2004:
+ Add some delays as needed for Intel LXT971A PHY support
+
+* Patches by Stephan Linz, 09 Jan 2004:
+ - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
+ - make DK1C20 board configuration related to ASMI conform to
+ documentation
+
+* Patch by Anders Larsen, 09 Jan 2004:
+
+ ARM memory layout fixes: the abort-stack is now set up in the
+ correct RAM area, and the BSS is zeroed out as it should be.
+
+ Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
+ of the linker scripts are replaced by '__bss_start' and '_end',
+ resp., which is a further step to eliminate unnecessary differences
+ between the implementation of the CPU architectures.
+
+* Patch by liang a lei, 9 Jan 2004:
+ Fix Intel 28F128J3 ID in include/flash.h
+
+* Patch by Masami Komiya, 09 Jan 2004:
+ add support for TB0229 board (NEC VR4131 MIPS processor)
+
+* Patch by Leon Kukovec, 12 Dec 2003:
+ changed extern __inline__ into static __inline__ in
+ include/linux/byteorder/swab.h
+
+* Patch by Travis Sawyer, 30 Dec 2003:
+ Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
+ select MDI port based on enabled EMAC device.
+ Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
+ base PrPMC board.
+
+* Patch by Wolter Kamphuis, 15 Dec 2003:
+ made CONFIG_SILENT_CONSOLE usable on all architectures
+
+* Disable date command on TQM866M - there is no RTC on MPC866
+
+* Fix variable CPU clock for MPC859/866 systems for low CPU clocks
+
+* Implement adaptive SDRAM timing configuration based on actual CPU
+ clock frequency for INCA-IP; fix problem with board hanging when
+ switching from 150MHz to 100MHz
+
+* Add PCMCIA CS support for BMS2003 board
+
+* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
+ see doc/README.MPC866 for details;
+ implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
+ calculate CPU clock frequency from PLL register values.
+
+* Add support for 128 MB RAM on TQM8xxL/M modules
+
+* Fix PS/2 keyboard problem caused by statically initialized variable
+ pointing to a location in flash
+
+* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130.
+
+* The PS/2 mux on the BMS2003 board needs 450 ms after power on
+ before we can access it; add delay in case we are faster (with no
+ CF card inserted)
+
+* Cleanup of some init functions
+
+* Make sure SCC Ethernet is always stopped by the time we boot Linux
+ to avoid Linux crashes by early packets coming in.
+
+* Accelerate flash accesses on LWMON board by using buffered writes
+
+* Fix typo in Makefile;
+ fix problem with PARTNUM detection
+
+* Patch by Reinhard Meyer, 09 Jan 2004:
+ - add RTC support for MPC5200 based boards (requires RTC_XTAL)
+
+* Add support for IDE LED on BMS2003 board
+ (exclusive with status LED!)
+
+* Add support for PS/2 keyboard (used with PS/2 multiplexor on
+ BMS2003 board)
+
+* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004:
+ Add common files for "emk" boards
+
+* Add a common get_ram_size() function and modify the the
+ board-specific files to invoke that common implementation.
+
+======================================================================
+Changes for U-Boot 1.0.1:
+======================================================================
+
+* Set default clock for INCA-IP to 150 MHz
+
+* Make BMS2003 use a separate config file to avoid #ifdef mess;
+ add I2C support; add support for DS1337 RTC
+
+* Add CompactFlash support for BMS2003 board
+
+* Add support for status LED on BMS2003 board
+
+* Patch by Scott McNutt, 02 Jan 2004:
+ Add support for the Nios Active Serial Memory Interface (ASMI)
+ on Cyclone devices
+
+* Patch by Andrea Marson, 16 Dec 2003:
+ Add support for the PPChameleon ME and HI modules
+
+* Patch by Yuli Barcohen, 22 Dec 2003:
+ Add support for Motorola DUET ADS board (MPC87x/88x)
+
+* Patch by Robert Schwebel, 15 Dec 2003:
+ add support for cramfs (uses JFFS2 command interface)
+
+* Patches by Stephan Linz, 11 Dec 2003:
+ - more documentation for NIOS port
+ - new struct nios_pio_t, struct nios_spi_t
+ - Reconfiguration for NIOS Development Kit DK1C20:
+ o move board related code from board/dk1c20
+ to board/altera/dk1c20
+ o create a new common source path board/altera/common
+ and move generic flash access stuff into it
+ o change/expand configuration file DK1C20.h
+ - Add support for NIOS Development Kit DK1S10
+ - Add status LED support for NIOS systems
+ - Add dual 7-segment LED support for Altera NIOS DevKits
+
+* Patch by Ronen Shitrit, 10 Dec 2003:
+ Add support for the Marvell DB64360 / DB64460 development boards
+
+* Patch by Detlev Zundel, 10 Dec 2003:
+ fix dependency problem in examples/Makefile
+
+* Patch by Denis Peter, 8 Dec 2003
+ - add support for the PATI board (MPC555)
+ - add SPI support for the MPC5xx
+
+* Patch by Anders Larsen, 08 Dec 2003:
+ add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG
+ to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target;
+ cleanup some redundand #defines
+
+* Patch by André Schwarz, 8 Dec 2003:
+ fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
+ - TX and RX deskriptors must be quad-word aligned
+ - does not work with only one TX deskriptor
+ - standard reset method does not work
+
+* Patch by Masami Komiya, 08 Dec 2003:
+ add RTL8139 ethernet driver
+
+* Patches by Ed Okerson, 07 Dec 2003:
+ - fix ethernet for the AU1x00 processors in little-endian mode.
+ - extend memsetup.S for the AU1x00 processors in BE and LE modes
+
+* Minor code cleanup (coding style)
+
+* Patch by Reinhard Meyer, 30 Dec 2003:
+ - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
+ - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
+ - turned debug print of PHY registers into a function (called in two places)
+ - added support for EMK MPC5200 based modules
+
+* Fix MPC8xx PLPRCR_MFD_SHIFT typo
+
+* Add support for TQM866M modules
+
+* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
+
+* Fix a few compiler warnings
+
+* Patch by Reinhard Meyer, 28 Dec 2003:
+ Add initial support for TOP5200 board
+
+* Make CPU clock on ICA-IP board controllable by a "cpuclk"
+ environment variable which can set to "100", "133", or "150". The
+ CPU clock will be configured accordingly upon next reboot. Other
+ values are ignored. In case of an invalid or undefined "cpuclk"
+ value, the compile-time default CPU clock speed will be used.
+
+* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory
+ window that is used to access the UART registers by the Linux driver)
+
+* Patch by Reinhard Meyer, 20 Dec 2003:
+ Fix clock calculation for the MPC5200 for higher clock frequencies
+ (above 2**32 / 10 = 429.5 MHz).
+
+* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration
+
+* Fix IceCube CLKIN configuration (it's 33.000000MHz)
+
+* Add new configuration for IceCube board with DDR memory
+
+* Update TRAB memory configurations
+
+* Add JFFS2 support for INCA-IP board
+
+* Patch by Bill Hargen, 09 Dec 2003:
+ - BUBINGA405EP: changed flash driver to protect top sector containing
+ first instruction.
+ - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM.
+ - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access).
+ - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1).
+ - 405EP: added/fixed support for "reginfo" command.
+ - 4xx: removed spurious MII error messages on "mii info" command.
+
+* Patch by Bernhard Kuhn, 28 Nov 2003:
+ add support for ColdFire CPU
+ add support for Motorola M5272C3 and M5282EVB boards
+
+* Patch by Pierre Aubert, 24 Nov 2003:
+ - add a return value for the fpga command
+ - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT
+ is defined. If ide_preinit fails, ide_init is aborted.
+ - fix an endianess problem in fat.h
+
+* Patch by Wolter Kamphuis, 05 Dec 2003:
+ Add support for SNMC's QS850/QS823/QS860T boards
+
+* Patch by Yuli Barcohen, 3 Dec 2003:
+ "revive" U-Boot support for old Motorola MPC860ADS board
+
+* Patch by Cam(ilo?), 03 Dec 2003:
+ make examples build even with broken Montavista objcopy
+
+* Patch by Pavel Bartusek, 27 Nov 2003:
+ fix conversion problem with "bootretry" evironment variable
+
+* Patch by Andre Schwarz, 24 Nov 2003:
+ add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
+
+* Patch by Pavel Bartusek, 21 Nov 2003:
+ set ZMII bridge speed on 440
+
+* Patch by Anders Larsen, 17 Nov 2003:
+ Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
+
+* Patches by David Müller, 14 Nov 2003:
+ - board/mpl/common/common_util.c
+ * implement support for BZIP2 compressed images
+ * various cleanups (printf -> puts, ...)
+ - board/mpl/common/flash.c
+ * report correct errors to upper layers
+ * check the erase fail and VPP low bits in status reg
+ - board/mpl/vcma9/cmd_vcma9.c
+ - board/mpl/vcma9/flash.c
+ * various cleanups (printf -> puts, ...)
+ - common/cmd_usb.c
+ * fix typo in comment
+ - cpu/arm920t/usb_ohci.c
+ * support for S3C2410 is missing in #if line
+ - drivers/cs8900.c
+ * reinit some registers in case of error (cable missing, ...)
+ - fs/fat/fat.c
+ * support for USB/MMC devices is missing in #if line
+ - include/configs/MIP405.h
+ - include/configs/PIP405.h
+ * enable BZIP2 support
+ * enlarge malloc space to 1MiB because of BZIP2 support
+ - include/configs/VCMA9.h
+ * enable BZIP2 support
+ * enlarge malloc space to 1MiB because of BZIP2 support
+ * enable USB support
+ - lib_arm/armlinux.c
+ * change calling convention of ARM Linux kernel as
+ described on http://www.arm.linux.org.uk/developer/booting.php
+
+* Patch by Thomas Lange, 14 Nov 2003:
+ Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to
+ support all these AMD boards.
+
+* Patch by Thomas Lange, 14 Nov 2003:
+ Workaround for mips au1x00 physical memory accesses (the au1x00
+ uses a 36 bit bus internally and cannot access physical memory
+ directly. Use the uncached SDRAM address instead of the physical
+ one.)
+
+* Patch by Xue Ligong (Joe), 13 Nov 2003:
+ add Realtek 8019 ethernet driver
+
+* Patch by Yuli Barcohen, 13 Nov 2003:
+ MPC826xADS/PQ2FADS cleanup
+
+* Patch by Anders Larsen, 12 Nov 2003:
+ Update README to mark the PORTIO commands non-standard
+
+* Patch by Nicolas Lacressonnière, 12 Nov 2003:
+ update for for Atmel AT91RM9200DK development kit:
+ - support for environment variables in DataFlash
+ - Atmel DataFlash AT45DB1282 support
+
+* Patch by Jeff Carr, 11 Nov 2003:
+ add support for new version of 8270 processors
+
+* Patches by George G. Davis, 05 Nov 2003:
+ - only pass the ARM linux initrd tag to the kernel when an initrd
+ is actually present
+ - update omap1510inn configuration file
+
+* Patches by Stephan Linz, 3 Nov 2003:
+ - more endianess fixes for LAN91C111 driver
+ - CFG_HZ configuration patch for NIOS Cyclone board
+
+* Patch by Stephan Linz, 28 Oct 2003:
+ fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c
+
+* Patch by Steven Scholz, 20 Oct 2003:
+ - make "mii info <addr>" show infor for PHY at "addr" only
+ - Endian fix for miiphy_info()
+
+* Patch by Gleb Natapov, 19 Sep 2003:
+ Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c
+
+* Patch by Anders Larsen, 17 Sep 2003:
+ Bring ARM memory layout in sync with the documentation:
+ stack and malloc-heap are now located _below_ the U-Boot code
+
+* Accelerate booting on TRAB board: read and check autoupdate image
+ headers first instead of always reading the whole images.
+
+* Fix type in MPC5XXX code (pointed out by Victor Wren)
+
+* Enabled password check on RMU board
+
+* Fix configuration problem with IceCube in LOWBOOT configuration:
+ envrionment got embedded, corrupting the image layout.
+
+* Fix NEC display names (it's 6440 [for 640x480], not 6640).
+
+* Added BMS2003 board
+ add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display
+
+* Fix flash driver for TRAB board (must use Unlock Bypass Reset
+ command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
+ and CPLD
+
+* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
+ recent tools
+
+* Add checksum verification to 'imls' command
+
+* Add bd_info fields needed for 4xx Linux I2C driver
+
+* Patch by Martin Krause, 4 Nov. 2003:
+ Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)
+
+* Print used network interface when CONFIG_NET_MULTI is set
+
+* Patch by Bernhard Kuhn, 28 Oct 2003:
+ Add low boot support for MPC5200
+
+* Fix problem with dual PCMCIA support (NSCU)
+
+* Fix MPC5200 I2C initialization function
+
+======================================================================
+Changes for U-Boot 1.0.0:
+======================================================================
+
+* Fix parameter passing to standalone images with bootm command
+
+* Patch by Kyle Harris, 30 Oct 2003:
+ Fix build errors for ixdp425 board
+
+* Patch by David M. Horn, 29 Oct 2003:
+ Fixes to build under CYGWIN
+
+* Get IceCube MGT5100 working (again)
+
+* Fix problems in memory test on some boards (which was not
+ non-destructive as intended)
+
+* Patch by Gary Jennejohn, 28 Oct 2003:
+ Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack
+ to prevent stack overflow on ARM systems
+
+* Patch by Stephan Linz, 28 Oct 2003:
+ fix init sequence error for NIOS port
+
+* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name
+
+* Add CONFIG_VERSION_VARIABLE to TRAB configuration
+
+* Patch by Xiao Xianghua, 23 Oct 2003:
+ small patch for mpc85xx
+
+* Fix small problem in MPC5200 I2C driver
+
+* Fix FCC3 support on ATC board
+
+* Correct header printing for multi-image files in do_bootm()
+
+* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED
+
+* Fix PCI problems on PPChameleon board
+
+* Patch by Steven Scholz, 18 Oct 2003:
+ Fix AT91RM9200 ethernet driver
+
+* Patch by Nye Liu, 17 Oct 2003:
+ Fix typo in include/mpc8xx.h
+
+* Patch by Richard Woodruff, 16 Oct 03:
+ Fixes for cpu/arm925/interrupt.c
+ - Initialize timestamp & lastdec vars.
+ - fix timestamp overflows.
+ - fix lastdec overflow.
+ - smarter normalization to allow udelay() below 1ms to work.
+
+* Patch by Scott McNutt, 16 Oct
+ add networking support for the Altera Nios Development Kit,
+ Cyclone Edition (DK-1C20)
+
+* Patch by Jon Diekema, 14 Oct 2003:
+ add hint about doc/README.silent to README file
+
+* Add CompactFlash support for NSCU
+
+* Fix PCI problems on PPChameleonEVB
+
+* TRAB auto-update: Base decision if we have to strip the image
+ header on image type as encoded in the header
+ (include image type patch by Martin Krause, 17 Oct 2003)
+
+* Patches by Xianghua Xiao, 15 Oct 2003:
+
+ - Added Motorola CPU 8540/8560 support (cpu/85xx)
+ - Added Motorola MPC8540ADS board support (board/mpc8540ads)
+ - Added Motorola MPC8560ADS board support (board/mpc8560ads)
+
+* Fix flash timings on TRAB board
+
+* Make sure HUSH is initialized for running auto-update scripts
+
+* Make 5200 reset command _really_ reset the board, without running
+ any other code after it
+
+* Fix errors with flash erase when range spans across banks
+ that are mapped in reverse order
+
+* Fix flash mapping and display on P3G4 board
+
+* Patch by Kyle Harris, 15 Jul 2003:
+ - add support for Intel IXP425 CPU
+ - add support for IXDP425 eval board
+
+* Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent
+ for more information
+
+* Patch by Steven Scholz, 10 Oct 2003
+ - Add support for Altera FPGA ACEX1K
+
+* Patches by Thomas Lange, 09 Oct 2003:
+ - fix cmd_ide.c for non ppc boards (read/write functions did not
+ add ATA base address)
+ - fix for shannon board
+ - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
+ - Endian swap ATA identity for all big endian CPUs, not just PPC
+ - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
+ args to linux
+ - add support for dbau1x00 board (MIPS32)
+
+* Patch by Sangmoon Kim, 07 Oct 2003:
+ add support for debris board
+
+* Patch by Martin Krause, 09 Oct 2003:
+ Fixes for TRAB board
+ - /board/trab/rs485.c: correct baudrate
+ - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
+ udelay(); fix some timing problems with adc controller
+ - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
+ modify commands: touch and buzzer
+
+* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE
+ (quick & dirty workaround for rogue pointer problem in get_vfatname());
+ Use direct function calls for auto_update instead of hush commands
+
+* Patch by Scott McNutt, 04 Oct 2003:
+ - add support for Altera Nios-32 CPU
+ - add support for Nios Cyclone Development Kit (DK-1C20)
+
+* Patch by Steven Scholz, 29 Sep 2003:
+ - A second parameter for bootm overwrites the load address for
+ "Standalone Application" images.
+ - bootm sets environment variable "filesize" to the resulting
+ (uncompressed) data length for "Standalone Application" images
+ when autostart is set to "no". Now you can do something like
+ if bootm $fpgadata $some_free_ram ; then
+ fpga load 0 $some_free_ram $filesize
+ fi
+
+* Patch by Denis Peter, 25 Sept 2003:
+ add support for the MIP405 Rev. C board
+
+* Patch by Yuli Barcohen, 25 Sep 2003:
+ add support for Zephyr Engineering ZPC.1900 board
+
+* Patch by Anders Larsen, 23 Sep 2003:
+ add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only
+ implemented for the x86 architecture)
+
+* Patch by Sangmoon Kim, 23 Sep 2003:
+ fix pll_pci_to_mem_multiplier table for MPC8245
+
+* Patch by Anders Larsen, 22 Sep 2003:
+ enable timed autoboot on PXA
+
+* Patch by David Müller, 22 Sep 2003:
+ - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver
+ returns correct libgcc file path
+ - "latency" reduction of busy-loop waiting to improve "U-Boot" boot
+ time on s3c24x0 systems
+
+* Patch by Jon Diekema, 19 Sep 2003:
+ - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet
+ link state to the fault LED.
+ - In NetLoop, make the Fault LED reflect the link status. The link
+ status gets updated on entry, and on timeouts.
+
+* Patch by Anders Larsen, 18 Sep 2003:
+ allow mkimage to build and run on Cygwin-hosted systems
+
+* Patch by Frank Müller, 18 Sep 2003:
+ use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in
+ cpu/mpc8xx/fec.c
+
+* Patch by Pantelis Antoniou, 16 Sep 2003:
+ add tool to compute fileds in the PLPRCR register for MPC86x
+
+* Use IH_TYPE_FILESYSTEM for TRAB "disk" images.
+
+* Fix build problems under FreeBSD
+
+* Add generic filesystem image type
+
+* Make fatload set filesize environment variable
+
+* enable basic / medium / high-end configurations for PPChameleonEVB
+ board; fix NAND code
+
+* enable TFTP client code to specify to the server the desired
+ timeout value (see RFC-2349)
+
+* Improve SDRAM setup for TRAB board
+
+* Suppress all output with splashscreen configured only if "splashimage"
+ is set
+
+* Fix problems with I2C support for mpc5200
+
+* Adapt TRAB configuration and auto_update to new memory layout
+
+* Add configuration for wtk board
+
+* Add support for the Sharp LQ065T9DR51U LCD display
+
+* Patch by Rune Torgersen, 17 Sep 2003:
+ - Fixes for MPC8266 default config
+ - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
+
+* Patches by Jon Diekema, 17 Sep 2003:
+ - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
+ env_common.c)
+ - sbc8260 tweaks
+ - adjust "help" output
+
+* Patches by Anders Larsen, 17 Sep 2003:
+ - fix spelling errors
+ - set GD_FLG_DEVINIT flag only after device function pointers
+ are valid
+ - Allow CFG_ALT_MEMTEST on systems where address zero isn't
+ writeable
+ - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
+ - trigger watchdog while waiting in serial driver
+
+* Add auto-update code for TRAB board using USB memory sticks,
+ support new configuration with more memory
+
+* disable MPC5200 bus pipelining as workaround for bus contention
+
+* Modify XLB arbiter priorities on MPC5200 so all devices use same
+ priority; configure critical interrupts to be handled like external
+ interrupts
+
+* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
+ go back to 66 MHz for stability
+
+* Patches by Jon Diekema, 15 Sep 2003:
+ - add description for missing CFG_CMD_* entries in the README file
+ - sacsng tweaks
+
+* Patch by Gleb Natapov, 14 Sep 2003:
+ enable watchdog support for all MPC824x boards that have a watchdog
+
+* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
+ "Non-octet Aligned Frame" errors we see at 100 Mbps
+
+* Patch by Sharad Gupta, 14 Sep 2003:
+ fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+
+* Patch by llandre, 11 Sep 2003:
+ update configuration for PPChameleonEVB board
+
+* Patch by David Müller, 13 Sep 2003:
+ various changes to VCMA9 board specific files
+
+* Add I2C support for MGT5100 / MPC5200
+
+* Patch by Rune Torgersen, 11 Sep 2003:
+ Changed default memory option on MPC8266ADS to NOT be Page Based
+ Interleave, since this doesn't work very well with the standard
+ 16MB DIMM
+
+* Patch by George G. Davis, 12 Sep 2003:
+ fix Makefile settings for sk98 driver
+
+* Patch by Stefan Roese, 12 Sep 2003:
+ - new boards added: DP405, HUB405, PLU405, VOH405
+ - some esd boards updated
+ - cpu/ppc4xx/sdram.c: disable memory controller before setting
+ first values
+ - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems
+
+* Patch by Martin Krause, 11 Sep 2003:
+ add burn-in tests for TRAB board
+
+* Enable instruction cache on MPC5200 board
+
+* Patch by Denis Peter, 11 Sep 2003:
+ - fix USB data pointer assignment for bulk only transfer.
+ - prevent to display erased directories in FAT filesystem.
+
+* Change output format for NAND flash - make it look like for other
+ memory, too
+
+======================================================================
+Changes for U-Boot 0.4.8:
+======================================================================
+
+* Add I2C and RTC support for RMU board
+
+* Patches by Denis Peter, 9 Sep 2003:
+ add FAT support for IDE, SCSI and USB
+
+* Patches by Gleb Natapov, 2 Sep 2003:
+ - cleanup of POST code for unsupported architectures
+ - MPC824x locks way0 of data cache for use as initial RAM;
+ this patch unlocks it after relocation to RAM and invalidates
+ the locked entries.
+
+* Patch by Gleb Natapov, 30 Aug 2003:
+ new I2C driver for mpc107 bridge. Now works from flash.
+
+* Patch by Dave Ellis, 11 Aug 2003:
+ - JFFS2: fix typo in common/cmd_jffs2.c
+ - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
+ - JFFS2: remove node version 0 warning
+ - JFFS2: accept JFFS2 PADDING nodes
+ - SXNI855T: add AM29LV800 support
+ - SXNI855T: move environment from EEPROM to flash
+ - SXNI855T: boot from JFFS2 in NOR or NAND flash
+
+* Patch by Bill Hargen, 11 Aug 2003:
+ fixes for I2C on MPC8240
+ - fix i2c_write routine
+ - fix iprobe command
+ - eliminates use of global variables, plus dead code, cleanup.
+
+* Add support for USB Mass Storage Devices (BBB)
+ (tested with USB memory sticks only)
+
+* Avoid flicker on TRAB's VFD
+
+* Add support for SK98xx driver
+
+* Add PCI support for SL8245 board
+
+* Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB)
+ or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
+ Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
+
+* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz)
+ to allow for more accurate baudrate settings
+ (error now 0.7% at 115 kbps, instead of 3.5% before)
+
+* Patch by Andreas Mohr, 4 Sep 2003:
+ Fix a lot of spelling errors
+
+* Add support for PPChameleon Eval Board
+
+* Add support for P3G4 board
+
+* Fix problem with MGT5100 FEC driver: add "early" MAC address
+ initialization
+
+* Patch by Yuli Barcohen, 7 Aug 2003:
+ check BCSR to detect if the board is configured in PCI mode
+
+======================================================================
+Changes for U-Boot 0.4.7:
+======================================================================
+
+* Patch by Raghu Krishnaprasad, 7 Aug 2003:
+ add support for Adder II MPC852T module
+
+* Patch by George G. Davis, 19 Aug 2003:
+ fix TI Innovator/OMAP1510 pin configs
+
+* Patches by Kshitij, 18 Aug 2003
+ - add support for arm926ejs cpu core
+ - add support for TI OMAP 1610 Innovator Board
+
+* Patch by Yuli Barcohen, 14 Aug 2003:
+ add support for bzip2 uncompression
+
+* Add GCC library to examples/Makefile so GCC utility functions will
+ be resolved, too
+
+* Add I2C and RTC support for RMU board using software I2C driver
+ (because of better response to iprobe command); fix problem with
+ "reset" command
+
+* Patch by Matthias Fuchs, 28 Aug 2003:
+ Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
+ CONFIG_BOOTP_MAKS (see README).
+
+* Fix ICU862 environment problem
+
+* Fix RAM size detection for RMU board
+
+* Implement "reset" for MGT5100/MPC5200 systems
+
+======================================================================
+Changes for U-Boot 0.4.6:
+======================================================================
+
+* Make Ethernet autonegotiation on INCA-IP work for all clock rates;
+ allow selection of clock frequency as "make" target
+
+* Implement memory autosizing code for IceCube boards
+
+* Configure network port on INCA-IP for autonegotiation
+
+* Fix overflow problem in network timeout code
+
+* Patch by Richard Woodruff, 8 Aug 2003:
+ Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
+
+======================================================================
+Changes for U-Boot 0.4.5:
+======================================================================
+
+* Update for TQM board defaults:
+ disable clocks_in_mhz, enable boot count limit
+
+* Removed tools/gdb from "make all" target. Added make target "gdbtools"
+ in toplevel directory instead. Removed astest.c from tools/gdb because
+ it is no longer relevant.
+
+* Fix PCI support for MPC5200 / IceCube Board
+
+* Map ISP1362 USB OTG controller for NSCU board
+
+* Patch by Brad Parker, 02 Aug 2003:
+ fix sc520_cdp problems
+
+* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements)
+
+* Allow erase command to cross flash bank boundaries
+
+* Patch by Scott McNutt, 21 Jul 2003:
+ Add support for LynuxWorks Kernel Downloadable Images (KDIs).
+ Both LynxOS and BlueCat linux KDIs are supported.
+
+* Patch by Richard Woodruff, 25 Jul 2003:
+ use more reliable reset for OMAP/925T
+
+* Patch by Nye Liu, 25 Jul 2003:
+ fix typo in mpc8xx.h
+
+* Patch by Richard Woodruff, 24 Jul 2003:
+ Fixes for cmd_nand.c:
+ - Fixed null dereferece which could result in incorrect ECC values.
+ - Added support for devices with no Ready/Busy signal hooked up.
+ - Added OMAP1510 read/write protect handling.
+ - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock
+ for non-JFFS2.
+ - Switched default ECC to be JFFS2.
+
+* Allow crc32 to be used at address 0x000
+
+* Provide consistent interface to standalone applications to access
+ the 'global_data' structure
+ Provide a doc/README.standalone more useful to users/developers.
+
+* Make IceCube MGT5100 FEC driver work
+
+* Implement new mechanism to export U-Boot's functions to standalone
+ applications: instead of using (PPC-specific) system calls we now
+ use a jump table; please see doc/README.standalone for details
+
+* Patch by Dave Westwood, 24 Jul 2003:
+ added support for Unity OS (a proprietary OS)
+
+* Patch by Detlev Zundel, 23 Jul 2003:
+ add "imls" command to print flash table of contents
+
+* Fix cold boot detection for log buffer reset
+
+* Return error for invalid length specifiers with "cp.X" etc.
+
+* Fix startup problem on MIPS
+
+* Allow for CONFIG_SPLASH_SCREEN even when no explicit
+ bitmap support is configured
+
+* Patch by Bill Hargen, 18 Jul 2003:
+ - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c
+
+* Patch by Denis Peter, 18 Jul 2003:
+ - fix memory configuration for MIP405T
+ - fix printout of baudrate for "loadb <loadaddr> <baudrate>"
+
+* Cleanup of TQM82xx configurations; use "official" board types
+ to make selection easier.
+
+* Patch by Martin Krause, 17 Jul 2003:
+ add delay to get I2C working with "imm" command and s3c24x0_i2c.c
+
+* Patch by Richard Woodruff, 17 July 03:
+ - Fixed bug in OMAP1510 baud rate divisor settings.
+
+* Patch by Nye Liu, 16 July 2003:
+ MPC860FADS fixes:
+ - add MPC86xADS support (uses MPC86xADS.h)
+ - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
+ o PLPRCR changes
+ o BRG changes (EXTAL/XTAL restricted to 10MHz)
+ o don't trust gclk() software measurement by default, depend on
+ CONFIG_8xx_GCLK_FREQ
+ - add DRAM SIMM not installed detection
+ - use more "correct" SDRAM initialization sequence
+ - allow different SDRAM sizes (8xxADS has 8M)
+ - default DER is 0
+ - remove unused MAMR defines from FADS860T.h (all done in fads.c)
+ - rename MAMR/MBMR defines to be more consistent. Should eventually
+ be merged into MxMR to better reflect the PowerQUICC datasheet.
+
+* Patch by Yuli Barcohen, 16 Jul 2003:
+ support new Motorola PQ2FADS-ZU evaluation board which replaced
+ MPC8260ADS and MPC8266ADS
+
+======================================================================
+Changes for U-Boot 0.4.4:
+======================================================================
+
+* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)
+
+* Add support for MGT5100 and MPC5200 processors
+
+* Patch by Lutz Dennig, 15 Jul 2003:
+ update for R360MPI board
+
+======================================================================
+Changes for U-Boot 0.4.3:
+======================================================================
+
+* Patches by Kshitij, 04 Jul 2003
+ - added support for arm925t cpu core
+ - added support for TI OMAP 1510 Innovator Board
+
+* Patches by Martin Krause, 14 Jul 2003:
+ - add I2C support for s3c2400 systems (trab board)
+ - (re-) add "ping" to command table
+
+* Fix handling of "slow" POST routines
+
+* Patches by Yuli Barcohen, 13 Jul 2003:
+ - Correct flash and JFFS2 support for MPC8260ADS
+ - fix PVR values and clock generation for PowerQUICC II family
+ (8270/8275/8280)
+
+* Patch by Bernhard Kuhn, 08 Jul 2003:
+ - add support for M68K targets
+
+* Patch by Ken Chou, 3 Jul:
+ - Fix PCI config table for A3000
+ - Fix iobase for natsemi.c
+ (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
+
+* Allow to enable "slow" POST routines by key press on power-on
+* Fix temperature dependend switching of LCD backlight on LWMON
+* Tweak output format for LWMON
+
+* Patch by Stefan Roese, 11 Jul 2003:
+ - Fix bug in CONFIG_VERSION_VARIABLE.
+ - AR405 config updated.
+ - OCRTC/ORSG: bsp command added.
+ - ASH405 bsp update.
+
+======================================================================
+Changes for U-Boot 0.4.2:
+======================================================================
+
+* Add support for NSCU board
+
+* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
+
+* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
+ mirror bit flash on TQM8xxM modules
+
+* Patch by Kenneth Johansson, 30 Jun 2003:
+ get rid of MK_CMD_ENTRY macro; update doc/README.command
+
+* Patch by Seb James, 30 Jun 2003:
+ Improve documentation of I2C configuration in README
+
+* Fix problems with previous log buffer "fixes"
+
+* Fix minor help text issues
+
+* "log append" did not append a newline
+
+======================================================================
+Changes for U-Boot 0.4.1:
+======================================================================
+
+* Fix some missing commands, cleanup header files
+ (autoscript, bmp, bsp, fat, mmc, nand, portio, ...)
+
+* Rewrite command lookup and help command (fix problems with bubble
+ sort when sorting command name list). Minor cleanup here and there.
+
+* Merge from "stable branch", tag LABEL_2003_06_28_1800-stable:
+ - Allow to call sysmon function interactively
+ - PIC on LWMON board needs delay after power-on
+ - Add missing RSR definitions for MPC8xx
+ - Improve log buffer handling: guarantee clean reset after power-on
+ - Add support for EXBITGEN board (aka "genie")
+ - Add support for SL8245 board
+
+* Code cleanup:
+ - remove trailing white space, trailing empty lines, C++ comments, etc.
+ - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
+
+* Patches by Kenneth Johansson, 25 Jun 2003:
+ - major rework of command structure
+ (work done mostly by Michal Cendrowski and Joakim Kristiansen)
+
+======================================================================
+Changes for U-Boot 0.4.0:
+======================================================================
+
+* Patches by Robert Schwebel, 26 Jun 2003:
+ - csb226 configuration updated
+ - credits for logodl port updated
+ - innokom configuration updated
+ - logodl tree update, still with coding style inconsistencies
+ - added OCM for ppc405 warning to README
+
+* Patch by Pantelis Antoniou, 25 Jun 2003:
+ update NetVia with V2 board support
+
+* Header file cleanup for ARM
+
+* Patch by Murray Jensen, 24 Jun 2003:
+ - make sure to use only U-boot provided header files
+ - fix problems with ".rodata.str1.4" section as used by GCC-3.x
+
+* Patch by Stefan Roese, 24 Jun 2003:
+ - Update esd ASH405 board files.
+ - Update esd DASA_SIM config file.
+ - Add ping command to some esd boards.
+
+* Patch by Yuli Barcohen, 23 Jun 2003:
+ Update for MPC8260ADS board
+
+* Patch by Murray Jensen, 23 Jun 2003:
+ - cleanup of GCC 3.x compiler warnings
+
+* Patch by Rune Torgersen, 4 Jun 2003:
+ add large memory support for MPC8266ADS board
+
+* Patch by Richard Woodruff, 19 June 03:
+ - Enabled standard u-boot device abstraction for ARM
+ - Enabled console device for ARM
+ - Initilized bi_baudrate for ARM
+
+* Patch by Bill Hargen, 23 Apr 2003:
+ fix byte order for 824x I2C addresses (write op)
+
+* Patch by Murray Jensen, 20 Jun 2003:
+ - hymod update
+ - cleanup (especially for gcc-3.x compilers)
+
+* Patch by Tom Guilliams, 20 Jun 2003:
+ added CONFIG_750FX support for IBM 750FX processors
+
+* Patch by Devin Crumb, 02 Apr 2003:
+ Fix clock divider rounding problem in drivers/serial.c
+
+* Patch by Richard Woodruff, 19 June 03:
+ - Fixed smc91c111 driver to sync with the u-boot environment
+ (driver/smc91c111.c).
+ - Added eth_init error return check in NetLoop (net/net.c).
+
+* Patch by Ken Chou, 19 June 2003:
+ Added support for A3000 SBC board (Artis Microsystems Inc.)
+
+* Patches by Murray Jensen, 17 Jun 2003:
+ - Hymod board database mods: add "who" field and new xilinx chip types
+ - provide new "init_cmd_timeout()" function so code external to
+ "common/main.c" can use the "reset_cmd_timeout()" function before
+ entering the main loop
+ - add DTT support for adm1021 (new file dtt/adm1021.c; config
+ slightly different. see include/configs/hymod.h for an example
+ (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and
+ CFG_DTT_ADM1021 defined)
+ - add new "eeprom_probe()" function which has similar args and
+ behaves in a similar way to "eeprom_read()" etc.
+ - add 8260 FCC ethernet loopback code (new "eth_loopback_test()"
+ function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST)
+ - gdbtools copyright update
+ - ensure that set_msr() executes the "sync" and "isync" instructions
+ after the "mtmsr" instruction in cpu/mpc8260/interrupts.c
+ - 8260 I/O ports fix: Open Drain should be set last when configuring
+ - add SIU IRQ defines for 8260
+ - allow LDSCRIPT override and OBJCFLAGS initialization: change to
+ config.mk to allow board configurations to override the GNU
+ linker script, selected via the LDSCRIPT, make variable, and to
+ give an initial value to the OBJCFLAGS make variable
+ - 8260 i2c enhancement:
+ o correctly extends the timeout depending on the size of all
+ queued messages for both transmit and receive
+ o will not continue with receive if transmit times out
+ o ensures that the error callback is done for all queued tx
+ and rx messages
+ o correctly detects both tx and rx timeouts, only delivers one to
+ the callback, and does not overwrite an earlier error
+ o logic in i2c_probe now correct
+ - add "vprintf()" function so that "panic()" function can be
+ technically correct
+ - many Hymod board changes
+
+* Patches by Robert Schwebel, 14 Jun 2003:
+ - add support for Logotronic DL datalogger board
+ - cleanup serial line after kermit binary download
+ - add debugX macro (debug level support)
+ - update mach-types.h to latest arm.linux.org.uk master list.
+
+* Patches by David Müller, 12 Jun 2003:
+ - rewrite of the S3C24X0 register definitions stuff
+ - "driver" for the built-in S3C24X0 RTC
+
+* Patches by Yuli Barcohen, 12 Jun 2003:
+ - Add MII support and Ethernet PHY initialization for MPC8260ADS board
+ - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
+ configuration word supplied by FPGA on some MPC8260ADS boards
+
+* Patch by Pantelis Antoniou, 10 Jun 2003:
+ Unify status LED interface
+
+* Add support for DS12887 RTC; add RTC support for ATC board
+
+* Patch by Nicolas Lacressonniere, 11 Jun 2003:
+ Modifications for Atmel AT91RM9200DK ARM920T based development kit
+ - Add Atmel DataFlash support for reading and writing.
+ - Add possibility to boot a Linux from DataFlash with BOOTM command.
+ - Add Flash detection on Atmel AT91RM9200DK
+ (between Atmel AT49BV1614 and AT49BV1614A flashes)
+ - Replace old Ethernet PHY layer functions
+ - Change link address
+
+* Patch by Frank Smith, 9 Jun 2003:
+ use CRIT_EXCEPTION for machine check on 4xx
+
+* Patch by Detlev Zundel, 13 Jun 2003:
+ added implementation of the "carinfo" command in cmd_immap.c
+
+* Fix CONFIG_NET_MULTI support in include/net.h
+
+* Patches by Kyle Harris, 13 Mar 2003:
+ - Add FAT partition support
+ - Add command support for FAT
+ - Add command support for MMC
+ ----
+ - Add Intel PXA support for video
+ - Add Intel PXA support for MMC
+ ----
+ - Enable MMC and FAT for lubbock board
+ - Other misc changes for lubbock board
+
+* Patch by Robert Schwebel, April 02, 2003:
+ fix for SMSC91111 driver
+
+* Patch by Vladimir Gurevich, 04 Jun 2003:
+ make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option
+
+* Patch by Stefan Roese, 05 Jun 2003:
+ - PPC4xx: Fix bug for initial stack in data cache as pointed out by
+ Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in
+ data cache can be used even if the chip select is in use.
+ - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count
+ (see README for further description).
+ - Changed config files of CONFIG_EEPRO100 boards to use the
+ CFG_RX_ETH_BUFFER define.
+
+* Add support for RMU board
+
+* Add support for TQM862L at 100/50 MHz
+
+* Patch by Pantelis Antoniou, 02 Jun 2003:
+ major reconstruction of networking code;
+ add "ping" support (outgoing only!)
+
+* Patch by Denis Peter, 04 June 2003:
+ add support for the MIP405T board
+
+* Patches by Udi Finkelstein, 2 June 2003:
+ - Added support for custom keyboards, initialized by defining a
+ board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
+ - Added support for the RBC823 board.
+ - cpu/mpc8xx/lcd.c now automatically calculates the
+ Horizontal Pixel Count field.
+
+* Fix alignment problem in BOOTP (dhcp_leasetime option)
+ [pointed out by Nicolas Lacressonnière, 2 Jun 2003]
+
+* Patch by Mark Rakes, 14 May 2003:
+ add support for Intel e1000 gig cards.
+
+* Patch by Nye Liu, 3 Jun 2003:
+ fix critical typo in MAMR definition (include/mpc8xx.h)
+
+* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
+
+* Patch by Klaus Heydeck, 2 Jun 2003
+ Minor changes for KUP4K configuration
+
+* Patch by Marc Singer, 29 May 2003:
+ Fixed rarp boot method for IA32 and other little-endian CPUs.
+
+* Patch by Marc Singer, 28 May 2003:
+ Added port I/O commands.
+
+* Patch by Matthew McClintock, 28 May 2003
+ - cpu/mpc824x/start.S: fix relocation code when booting from RAM
+ - minor patches for utx8245
+
+* Patch by Daniel Engström, 28 May 2003:
+ x86 update
+
+* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
+ add nand flash support to SXNI855T configuration
+ fix/extend nand flash support:
+ - fix 'nand erase' command so does not erase bad blocks
+ - fix 'nand write' command so does not write to bad blocks
+ - fix nand_probe() so handles no flash detected properly
+ - add doc/README.nand
+ - add .jffs2 and .oob options to nand read/write
+ - add 'nand bad' command to list bad blocks
+ - add 'clean' option to 'nand erase' to write JFFS2 clean markers
+ - make NAND read/write faster
+
+* Patch by Rune Torgersen, 23 May 2003:
+ Update for MPC8266ADS board
+
+* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
+ instead CFG_MONITOR_LEN is now only used to determine _at_compile_
+ _time_ (!) if the environment is embedded within the U-Boot image,
+ or in a separate flash sector.
+
+* Cleanup CFG_DER #defines in config files (wd maintained only)
+
+* Fix data abort exception handling for arm920t CPU
+
+* Fix alignment problems with flash driver for TRAB board
+
+* Patch by Donald White, 21 May 2003:
+ fix calculation of base address in pci_hose_config_device()
+
+* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always
+ execute "cmd2", even if "cmd1" fails. Note that this is different
+ to "run var1 var2" where the contents of "var2" will NOT be
+ executed when a command in "var1" fails.
+
+* Add zero-copy ramdisk support (requires corresponding kernel support!)
+
+* Patch by Kyle Harris, 20 May 2003:
+ In preparation for an ixp port, rename cpu/xscale and arch-xscale
+ into cpu/pxa and arch-pxa.
+
+* Patch by Stefan Roese, 23 May 2003:
+ - IBM PPC405EP port added.
+ - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not
+ UART0) is used as default U-Boot console. PPC4xx only!
+ - esd ASH405 board added (PPC405EP based).
+ - BUBINGA405EP board added (PPC405EP based - IBM Eval Board).
+ - esd CPCI405AB board added.
+ - esd PMC405 board added.
+ - Update of some esd boards.
+
+* Patch by Denis Peter, 19 Mai 2003:
+ add support for the MIP405-3 board
+
+* Patch by Dave Ellis, 22 May 2003:
+ Fix problem with only partially cleared .bss segment
+
+* Patch by Rune Torgersen, 12 May 2003:
+ get PCI to work on a MPC8266ADS board; incorporate change to
+ cpu/mpc8260/pci.c to enable overrides of PCI memory parameters
+
+* Patch by Nye Liu, 1 May 2003:
+ minor patches for the FADS8xx
+
+* Patch by Thomas Schäfer, 28 Apr 2003:
+ Fix SPD handling for 256 ECC DIMM on Walnut
+
+* Add support for arbitrary bitmaps for TRAB's VFD command;
+ allow to pass boot bitmap addresses in environment variables;
+ allow for zero boot delay
+
+* Patch by Christian Geißinger, 19 May 2002:
+ On TRAB: wait until the dummy byte has been completely sent
+
+* Patch by David Updegraff, 22 Apr 2003:
+ update for CrayL1 board
+
+* Patch by Pantelis Antoniou, 21 Apr 2003:
+ add boot support for ARTOS (a proprietary OS)
+
+* Patch by Steven Scholz, 11 Apr 2003:
+ Add support for RTC DS1338
+
+* Patch by Rod Boyce, 24 Jan 2003:
+ Fix counting of extended partitions in diskboot command
+
+* Patch by Christophe Lindheimer, 20 May 2003:
+ allow the use of CFG_LOADS when CFG_NO_FLASH is set
+
+* Fix SDRAM timing on Purple board
+
+* Add support for CompactFlash on ATC board
+ (includes support for Intel 82365 and compatible PC Card controllers,
+ and Yenta-compatible PCI-to-CardBus controllers)
+
+* Patch by Mathijs Haarman, 08 May 2003:
+ Add lan91c96 driver (tested on Lubbock and custom PXA250 board only)
+
+* Fix problem with usage of "true" (undefined in current versions of bfd.h)
+
+* Add support for Promess ATC board
+
+* Patch by Keith Outwater, 28 Apr 2003:
+ - Miscellaneous corrections and additions to GEN860T board specific code.
+ - Added GEN860_SC variant to GEN860T.
+ - Miscellaneous corrections to GEN860T documentation.
+ - Correct duplicate entry in U-Boot CREDITS file.
+ - Add GEN860T_SC entry in MAINTAINERS file.
+ - Update CREDITS file with GEN860T_SC info.
+
+* Update Smiths Aerospace addresses in MAINTAINERS file
+
+* Fix error handling in hush's version of "run" command
+
+* LWMON extensions:
+ - Splashscreen support
+ - modem support
+ - sysmon support
+ - temperature dependend enabling of LCD
+
+* Allow booting from old "PPCBoot" disk partitions
+
+* Add support for TQM8255 Board / MPC8255 CPU
+
+======================================================================
+Changes for U-Boot 0.3.1:
+======================================================================
+
+* Make sure Block Lock Bits get cleared in R360MPI flash driver
+
+* MPC823 LCD driver: Fill color map backwards, to allow for steady
+ display when Linux takes over
+
+* Patch by Erwin Rol, 27 Feb 2003:
+ Add support for RTEMS (this time for real).
+
+* Add support for "bmp info" and "bmp display" commands to load
+ bitmap images; this can be used (for example in a "preboot"
+ command) to display a splash screen very quickly after poweron.
+
+* Add support for 133 MHz clock on INCA-IP board
+
+* Patch by Lutz Dennig, 10 Apr 2003:
+ Update for R360MPI board
+
+* Add new meaning to "autostart" environment variable:
+ If set to "no", a standalone image passed to the
+ "bootm" command will be copied to the load address
+ (and eventually uncompressed), but NOT be started.
+ This can be used to load and uncompress arbitrary
+ data.
+
+* Patch by Stefan Roese, 10 Apr 2003:
+ Changed DHCP client to use IP address from server option field #54
+ from the OFFER packet in the server option field #54 in the REQUEST
+ packet. This fixes a problem using a Windows 2000 DHCP server,
+ where the DHCP-server is not the TFTP-server.
+
+* Set max brightness for MN11236 displays on TRAB board
+
+* Add support for TQM862L modules
+
+======================================================================
+Changes for U-Boot 0.3.0:
+======================================================================
+
+* Patch by Arun Dharankar, 4 Apr 2003:
+ Add IDMA example code (tested on 8260 only)
+
+* Add support for Purple Board (MIPS64 5Kc)
+
+* Add support for MIPS64 5Kc CPUs
+
+* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
+
+* Patch by Denis Peter, 04 Apr 2003:
+ - update MIP405-4 board
+
+* Patch by Stefan Roese, 4 Apr 2003:
+ - U-Boot version environment variable "ver" added
+ (CONFIG_VERSION_VARIABLE).
+ - Changed PPC405GPr version from A to B.
+ - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.
+
+* Patches by Denis Peter, 03 April 2003:
+ - fix PCI IRQs on MPL boards
+ - fix two more un-relocated pointer problems
+
+* Fix behaviour of "run" command:
+ - print error message iv variable does not exist
+ - terminate processing of arguments in case of error
+
+* Patches by Peter Figuli, 10 Mar 2003
+ - Add support for BTUART on PXA platform
+ - Add support for WEP EP250 (PXA) board
+
+* Fix flash problems on INCA-IP; add tool to allow bruning images to
+ flash using a BDI2000
+
+* Implement fix for I2C Edge Conditions problem for all boards that
+ use the bit-banging driver (common/soft_i2c.c)
+
+* Patch by Martin Winistoerfer, 23 Mar 2003
+ - Add port to MPC555/556 microcontrollers
+ - Add support for cmi customer board with
+ Intel 28F128J3A, 28F320J3A or 28F640J3A flash.
+
+* Patch by Rick Bronson, 28 Mar 2003:
+ - fix common/cmd_nand.c
+
+* Patch by Arun Dharankar, 24 Mar 2003:
+ - add threads / scheduler example code
+
+* Add patches by Robert Schwebel, 31 Mar 2003:
+ - add ctrl-c support for kermit download
+ - align bdinfo output on ARM
+ - csb226 board: bring in sync with innokom/memsetup.S
+ - csb226 board: fix MDREFR handling
+ - misc doc fixes / extensions
+ - innokom board: cleanup, MDREFR fix in memsetup.S, config update
+ - add BOOT_PROGRESS to armlinux.c
+
+* Add CPU ID, version, and clock speed for INCA-IP
+
+* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
+ - fix SRAM and SDRAM memory sizing
+ - add status LED support
+ - add MAC address for second (SCC1) ethernet port
+
+* Update default environment for TQM8260 board
+
+* Patch by Rick Bronson, 16 Mar 2003:
+ - Add NAND flash support for reading, writing, and erasing NAND
+ flash (certain forms of which are called SmartMedia).
+ - Add support for Atmel AT91RM9200DK ARM920T based development kit.
+
+* Patches by Robert Schwebel, 19 Mar 2003:
+ - use arm-linux-gcc as default compiler for ARM
+ - fix i2c fixup code
+ - fix missing baudrate setting
+ - added $loadaddr / CFG_LOAD_ADDR support to loadb
+ - moved "ignoring trailing characters" _before_ u-boot wants to
+ print out diagnostics messages; removes bogus characters at the
+ end of transmission
+
+* Patch by John Zhan, 18 Mar 2003:
+ Add support for SinoVee Microsystems SC8xx boards
+
+* Patch by Rolf Offermanns, 21 Mar 2003:
+ ported the dnp1110 related changes from the current armboot cvs to
+ current u-boot cvs. smc91111 does not work. problem marked in
+ smc91111.c, grep for "FIXME".
+
+* Patch by Brian Auld, 25 Mar 2003:
+ Add support for STM flash chips on ebony board
+
+* Add PCI support for MPC8250 Boards (PM825 module)
+
+* Patch by Stefan Roese, 25 Mar 2003:
+ - PCI405 update.
+
+* Patch by Stefan Roese, 20 Mar 2003:
+ - CPCI4052 update (support for revision 3).
+ - Set edge conditioning circuitry on PPC405GPr for compatibility
+ to existing PPC405GP designs.
+ - Clip udiv to 5 bits on PPC405 (serial.c).
+
+* Extend INCAIP board support:
+ - add automatic RAM size detection
+ - add "bdinfo" command
+ - pass flash address and size to Linux kernel
+ - switch to 150 MHz clock
+
+* Avoid flicker on the TRAB's VFD by synchronizing the enable with
+ the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100
+ boards, version 153 for Rev. 200 boards).
+
+* Patch by Vladimir Gurevich, 12 Mar 2003:
+ Fix relocation problem of statically initialized string pointers
+ in common/cmd_pci.c
+
+* Patch by Kai-Uwe Blöm, 12 Mar 2003:
+ Cleanup & bug fixes for JFFS2 code:
+ - the memory mangement was broken. It caused havoc on malloc by
+ writing beyond the block boundaries.
+ - the length calculation for files was wrong, sometimes resulting
+ in short file reads.
+ - data copying now optionally takes fragment version numbers into
+ account, to avoid copying from older data.
+ See doc/README.JFFS2 for details.
+
+* Patch by Josef Wagner, 12 Mar 2003:
+ - 16/32 MB and 50/80 MHz support with auto-detection for IP860
+ - ETH05 and BEDBUG support for CU824
+ - added support for MicroSys CPC45
+ - new BOOTROM/FLASH0 and DOC base for PM826
+
+* Patch by Robert Schwebel, 12 Mar 2003:
+ Fix the chpart command on innokom board
+
+* Name cleanup:
+ mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h
+ s/PPCBoot/U-Boot/ in some files
+ s/pImage/uImage/ in some files
+
+* Patch by Detlev Zundel, 15 Jan 2003:
+ Fix '' command line quoting
+
+* Patch by The LEOX team, 19 Jan 2003:
+ - add support for the ELPT860 board
+ - add support for Dallas ds164x RTC
+
+* Patches by David Müller, 31 Jan 2003:
+ - minimal setup for CardBus bridges
+ - add EEPROM read/write support in the CS8900 driver
+ - add support for the builtin I2C controller in the Samsung s3c24x0 chips
+ - add support for MPL's VCMA9 (Samsung s3c2410 based) board
+
+* Patch by Steven Scholz, 04 Feb 2003:
+ add support for RTC DS1307
+
+* Patch by Reinhard Meyer, 5 Feb 2003:
+ fix PLPRCR/SCCR init sequence on 8xx to allow for
+ changes of EBDF by software
+
+* Patch by Vladimir Gurevich, 07 Feb 2003:
+ "API-compatibility patch" for 4xx I2C driver
+
+* TRAB fixes / extensions:
+ - Restore VFD brightness as saved in environment
+ - add support for Fujitsu flashes
+ - make sure both buzzers are turned off (drive low level)
+
+* Patches by Robert Schwebel, 06 Mar 2003:
+ - fix bug in BOOTP code (must use NetCopyIP)
+ - update of CSB226 port
+ - clear BSS segment on XScale
+ - added support for i2c_init_board() function
+ - update to the Innokom plattform
+
+* Extend support for redundand environments for configurations where
+ environment size < sector size
+
+* Patch by Rune Torgersen, 13 Feb 2003:
+ Add support for Motorola MPC8266ADS board
+
+* Patch by Kyle Harris, 19 Feb 2003:
+ patches for the Intel lubbock board:
+ memsetup.S - general cleanup (based on Robert's csb226 code)
+ flash.c - overhaul, actually works now
+ lubbock.c - fix init funcs to return proper value
+
+* Patch by Kenneth Johansson, 26 Feb 2003:
+ - Fixed off by one in RFTA calculation.
+ - No need to abort when LDF is lower than we can program it's only
+ minimum timing so clamp it to what we can do.
+ - Takes function pointer to function for reading the spd_nvram. Usefull
+ for faking data or hardcode a module without the nvram.
+ - fix other user for above change
+ - fix some comments.
+
+* Patches by Brian Waite, 26 Feb 2003:
+ - fix port for evb64260 board
+ - fix PCI for evb64260 board
+ - fix PCI scan
+
+* Patch by Reinhard Meyer, 1 Mar 2003:
+ Add support for EMK TOP860 Module
+
+* Patch by Yuli Barcohen, 02 Mar 2003:
+ Add SPD EEPROM support for MPC8260ADS board
+
+* Patch by Robert Schwebel, 21 Jan 2003:
+ - Add support for Innokom board
+ - Don't complain if "install" fails
+ - README cleanup (remove duplicated lines)
+ - Update PXA header files
+
+* Add documentation for existing POST code (doc/README.POST)
+
+* Patch by Laudney Ren, 15 Jan 2003:
+ Fix handling of redundand environment in "tools/envcrc.c"
+
+* Patch by Detlev Zundel, 28 Feb 2003:
+ Add bedbug support for 824x systems
+
+* Add support for 16 MB flash configuration of TRAB board
+
+* Patch by Erwin Rol, 27 Feb 2003:
+ Add support for RTEMS
+
+* Add image information to README
+
+* Patch by Stefan Roese, 18 Feb 2003:
+ CPCIISER4 configuration updated.
+
+* Patch by Stefan Roese, 17 Feb 2003:
+ Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).
+
+* Patch by Stefan Roese, 13 Feb 2003:
+ Add "pcidelay" environment variable (in ms, enabled via
+ CONFIG_PCI_BOOTDELAY).
+ PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after
+ RST# to respond to configuration cycles (33MHz -> 1s).
+
+* Fix dual PCMCIA slot support (when running with just one
+ slot populated)
+
+* Add VFD type detection to trab board
+
+* extend drivers/cs8900.c driver to synchronize ethaddr environment
+ variable with value in the EEPROM
+
+* Patch by Stefan Roese, 10 Feb 2003:
+ Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c)
+
+* Add support for MIPS32 4Kc CPUs
+
+* Add support for INCA-IP Board
+
+======================================================================
+Changes for U-Boot 0.2.2:
+======================================================================
+
+* Add dual ethernet support on PM826
+
+* Add support for LXT971 PHY on PM826
+
+* Patch by Tord Andersson, 16 Jan 2003:
+ Fix flash sector count for TQM8xxL
+
+* Fix I2C EEPROM problem on ICU862 board (would only write the first
+ 16 bytes out of each 32 byte block)
+
+======================================================================
+Changes for U-Boot 0.2.1:
+======================================================================
+
+* Add support for V37 board
+ (patch by Jón Benediktsson, 11 Dec 2002)
+
+* Update baudrate in bd_info when it gets changed
+
+* Add watchdog trigger points while waiting for serial port
+ (so far only 8xx -- needed on LWMON with 100ms watchdog)
+
+* Improve command line tool to access the U-Boot's environment
+ (figuration of the utility, using a config file)
+
+* Add single quote support for (old) command line parser
+
+* Switch LWMON board default config from FRAM to EEPROM;
+ in POST, EEPROM shows up on 8 addresses
+
+======================================================================
+Changes for U-Boot 0.2.0:
+======================================================================
+
+* Use 1-byte-read instead of -write for iprobe() function
+ Add i2c commands to PM826 config
+
+* extend I2C POST code: check for list on known addresses
+
+* Improve log buffer code; use "loglevel" to decide which messages
+ to log on the console, too (like in Linux); get rid of "logstart"
+
+* Add command line tool to access the U-Boot's environment
+ (board-specific for TRAB now, to be fixed later)
+
+* Patch by Hans-Joerg Frieden, 06 Dec 2002
+ Fix misc problems with AmigaOne support
+
+* Patch by Chris Hallinan, 3 Dec 2002:
+ minor cleanup to the MPC8245 EPIC driver
+
+* Patch by Pierre Aubert , 28 Nov 2002
+ Add support for external (SIU) interrupts on MPC8xx
+
+* Patch by Pierre Aubert , 28 Nov 2002
+ Fix nested syscalls bug in standalone applications
+
+* Patch by David Müller, 27 Nov 2002:
+ fix output of "pciinfo" command for CardBus bridge devices.
+
+* Fix bug in TQM8260 board detection - boards got stuck when board ID
+ was not readable
+
+* Add LED indication for IDE activity on KUP4K board
+
+* Fix startup problems with VFD display on TRAB
+
+* Patch by Pierre Aubert, 20 Nov 2002
+ Add driver for Epson SED13806 graphic controller.
+ Add support for BMP logos in cfb_console driver.
+
+* Added support for both PCMCIA slots (at the same time!) on MPC8xx
+
+* Patch by Rod Boyce, 21 Nov 2002:
+ fix PCMCIA on MBX8xx board
+
+* Patch by Pierre Aubert , 21 Nov 2002
+ Add CFG_CPM_POST_WORD_ADDR to make the offset of the
+ bootmode word in DPRAM configurable
+
+* Patch by Daniel Engström, 18 Nov 2002:
+ Fixes for x86 port (mostly strings issues)
+
+* Patch by Ken Chou, 18 Nov 2002:
+ Fix for natsemi NIC cards (DP83815)
+
+* Patch by Pierre Aubert, 19 Nov 2002:
+ fix a bug for the MII configuration, and some warnings
+
+* Patch by Thomas Frieden, 13 Nov 2002:
+ Add code for AmigaOne board
+ (preliminary merge to U-Boot, still WIP)
+
+* Patch by Jon Diekema, 12 Nov 2002:
+ - Adding URL for IEEE OUI lookup
+ - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED
+ being defined.
+ - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and
+ root-on-nfs macros are designed to switch how the default boot
+ method gets defined.
+
+* Patch by Daniel Engström, 13 Nov 2002:
+ Add support for i386 architecture and AMD SC520 board
+
+* Patch by Pierre Aubert, 12 Nov 2002:
+ Add support for DOS filesystem and booting from DOS floppy disk
+
+* Patch by Jim Sandoz, 07 Nov 2002:
+ Increase number of network RX buffers (PKTBUFSRX in
+ "include/net.h") for EEPRO100 based boards (especially SP8240)
+ which showed "Receiver is not ready" errors when U-Boot was
+ processing the receive buffers slower than the network controller
+ was filling them.
+
+* Patch by Andreas Oberritter, 09 Nov 2002:
+ Change behaviour of NetLoop(): return -1 for errors, filesize
+ otherwise; return code 0 is valid an means no file loaded - in this
+ case the environment still gets updated!
+
+* Patches by Jon Diekema, 9 Nov 2002:
+ - improve ADC/DAC clocking on the SACSng board to align
+ the failing edges of LRCLK and SCLK
+ - sbc8260 configuration tweaks
+ - add status LED support for 82xx systems
+ - wire sspi/sspo commands into command handler; improved error
+ handlering
+ - add timestamp support and alternate memory test to the
+ SACSng configuration
+
+* Patch by Vince Husovsky, 7 Nov 2002:
+ Add "-n" to linker options to get rid of "Not enough room for
+ program headers" problem
+
+* Patch by David Müller, 05 Nov 2002
+ Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
+ so we can use an already existing name
+
+* Patch by Pierre Aubert, 05 Nov 2002
+ Hardware relatied improvments in FDC boot code
+
+* Patch by Holger Schurig, 5 Nov 2002:
+ Make the PXA really change it's frequency
+
+* Patch by Pierre Aubert, 05 Nov 2002
+ Add support for slave serial Spartan 2 FPGAs
+
+* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
+ drivers
+
+* Add support for log buffer which can be passed to Linux kernel's
+ syslog mechanism; used especially for POST results.
+
+* Patch by Klaus Heydeck, 31 Oct 2002:
+ Add initial support for kup4k board
+
+* Patch by Robert Schwebel, 04 Nov 2002:
+ - use watchdog to reset PXA250 systems
+ - added progress callbacks to (some of the) ARM code
+ - update for Cogent CSB226 board
+
+* Add support for FPS860 board
+
+* Patch by Guillaume Alexandre,, 04 Nov 2002:
+ Improve PCI access on 32-bits Compact PCI bus
+
+* Fix mdelay() on TRAB - this was still the debugging version with
+ seconds instead of ms.
+
+* Patch by Robert Schwebel, 1 Nov 2002:
+ XScale related cleanup (affects all ARM boards)
+
+* Cleanup of names and README.
+
+======================================================================
+Notes for U-Boot 0.1.0:
+======================================================================
+
+This is the initial version of "Das U-Boot", the Universal Boot Loader.
+
+It is based on version 2.0.0 (the "Halloween Release") of PPCBoot.
+For information about the history of the project please see the
+PPCBoot project page at http://sourceforge.net/projects/ppcboot
+
+======================================================================
MPC8541CDS MPC8541
MPC8555CDS MPC8555
+ MPC8641HPCN MPC8641D
+
Dan Malek <dan@embeddededge.com>
STxGP3 MPC85xx
r5200 mcf52x2
#########################################################################
+# AVR32 Systems: #
+# #
+# Maintainer Name, Email Address #
+# Board CPU #
+#########################################################################
+
+Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+ ATSTK1000 AT32AP7000
+
+#########################################################################
# End of MAINTAINERS list #
#########################################################################
icecube_5100 icecube_5200 lite5200b mcc200 \
o2dnt pf5200 PM520 TB5200 \
Total5100 Total5200 Total5200_Rev2 TQM5200 \
- TQM5200_B TQM5200S \
+ TQM5200_B TQM5200S v38b \
"
#########################################################################
r5200 M5271EVB \
"
+#########################################################################
+## AVR32 Systems
+#########################################################################
+
+LIST_avr32="atstk1002"
+
#-----------------------------------------------------------------------
#----- for now, just run PPC by default -----
mips|mips_el| \
nios|nios2| \
x86|I486| \
- coldfire)
+ coldfire| \
+ avr32)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
VERSION = 1
PATCHLEVEL = 1
-SUBLEVEL = 4
+SUBLEVEL = 5
EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
ifeq ($(ARCH),blackfin)
CROSS_COMPILE = bfin-elf-
endif
+ifeq ($(ARCH),avr32)
+CROSS_COMPILE = avr32-
+endif
endif
endif
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
+ifeq ($(CPU),mpc86xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif
ifeq ($(CPU),bf533)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o
$(MAKE) -C $@ all
$(NAND_SPL): version
- $(MAKE) -C nand_spl all
+ $(MAKE) -C nand_spl/board/$(BOARDDIR) all
$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin
- cat nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+ cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
version:
@echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
@ exit 1
endif
+.PHONY : CHANGELOG
+CHANGELOG:
+ git log --no-merges U-Boot-1_1_5.. > $@
+
#########################################################################
unconfig:
}
@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
+v38b_config: unconfig
+ @./mkconfig -a V38B ppc mpc5xxx v38b
+
inka4x0_config: unconfig
@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
rainier_config: unconfig
- @echo "#define CONFIG_RAINIER" > include/config.h
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_RAINIER" > $(obj)include/config.h
@echo "Configuring for rainier board as subset of sequoia..."
@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
rainier_nand_config: unconfig
- @echo "#define CONFIG_RAINIER" > include/config.h
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)nand_spl
+ @mkdir -p $(obj)board/amcc/sequoia
+ @echo "#define CONFIG_RAINIER" > $(obj)include/config.h
@echo "Configuring for rainier board as subset of sequoia..."
- @ln -s board/amcc/sequoia/Makefile nand_spl/Makefile
- @echo "#define CONFIG_NAND_U_BOOT" >> include/config.h
+ @echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h
@echo "Compile NAND boot image for sequoia"
@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
- @echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp
- @echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk
+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc
sequoia_nand_config: unconfig
- @ln -s board/amcc/sequoia/Makefile nand_spl/Makefile
- @echo "#define CONFIG_NAND_U_BOOT" >include/config.h
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)nand_spl
+ @mkdir -p $(obj)board/amcc/sequoia
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@echo "Compile NAND boot image for sequoia"
@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
- @echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp
- @echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk
+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sycamore_config: unconfig
@echo "Configuring for sycamore board as subset of walnut..."
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
#########################################################################
+## MPC86xx Systems
+#########################################################################
+
+MPC8641HPCN_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc86xx mpc8641hpcn
+
+
+#########################################################################
## 74xx/7xx Systems
#########################################################################
@echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h
@$(MKCONFIG) -a pb1x00 mips mips pb1x00
+#========================================================================
+# AVR32
+#========================================================================
+#########################################################################
+## AT32AP7xxx
+#########################################################################
+
#########################################################################
## MIPS64 5Kc
#########################################################################
rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
rm -f $(obj)include/bmp_logo.h
- find nand_spl -lname "*" -print | xargs rm -f
- rm -f nand_spl/u-boot-spl nand_spl/u-boot-spl.map
+ rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
clobber: clean
find $(OBJTREE) -type f \( -name .depend \
rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+ [ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
- arm925t Files specific to ARM 925 CPUs
- arm926ejs Files specific to ARM 926 CPUs
- arm1136 Files specific to ARM 1136 CPUs
+ - at32ap Files specific to Atmel AVR32 AP CPUs
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- examples Example code for standalone applications, etc.
- include Header Files
- lib_arm Files generic to ARM architecture
+- lib_avr32 Files generic to AVR32 architecture
- lib_generic Files generic to all architectures
- lib_i386 Files generic to i386 architecture
- lib_m68k Files generic to m68k architecture
----------------------
CONFIG_NIOS2
+ AVR32 based CPUs:
+ ----------------------
+ CONFIG_AT32AP
- Board Type: Define exactly one of
CONFIG_PCI5441 CONFIG_PK1C20
CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
+ AVR32 based boards:
+ -------------------
+
+ CONFIG_ATSTK1000
+
+- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
+ Define exactly one of
+ CONFIG_ATSTK1002
+
- CPU Module Type: (if CONFIG_COGENT is defined)
Define exactly one of
Board code has addition modification that it wants to make
to the flat device tree before handing it off to the kernel
+ CONFIG_OF_BOOT_CPU
+
+ This define fills in the correct boot cpu in the boot
+ param header, the default value is zero if undefined.
+
- Serial Ports:
CFG_PL010_SERIAL
4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
LynxOS, pSOS, QNX, RTEMS, ARTOS;
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
-* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
+* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
- Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC).
+ Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
* Compression Type (uncompressed, gzip, bzip2)
* Load Address
* Entry Point
bash#
+Boot Linux and pass a flat device tree:
+-----------
+
+First, U-Boot must be compiled with the appropriate defines. See the section
+titled "Linux Kernel Interface" above for a more in depth explanation. The
+following is an example of how to start a kernel and pass an updated
+flat device tree:
+
+=> print oftaddr
+oftaddr=0x300000
+=> print oft
+oft=oftrees/mpc8540ads.dtb
+=> tftp $oftaddr $oft
+Speed: 1000, full duplex
+Using TSEC0 device
+TFTP from server 192.168.1.1; our IP address is 192.168.1.101
+Filename 'oftrees/mpc8540ads.dtb'.
+Load address: 0x300000
+Loading: #
+done
+Bytes transferred = 4106 (100a hex)
+=> tftp $loadaddr $bootfile
+Speed: 1000, full duplex
+Using TSEC0 device
+TFTP from server 192.168.1.1; our IP address is 192.168.1.2
+Filename 'uImage'.
+Load address: 0x200000
+Loading:############
+done
+Bytes transferred = 1029407 (fb51f hex)
+=> print loadaddr
+loadaddr=200000
+=> print oftaddr
+oftaddr=0x300000
+=> bootm $loadaddr - $oftaddr
+## Booting image at 00200000 ...
+ Image Name: Linux-2.6.17-dirty
+ Image Type: PowerPC Linux Kernel Image (gzip compressed)
+ Data Size: 1029343 Bytes = 1005.2 kB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+ Uncompressing Kernel Image ... OK
+Booting using flat device tree at 0x300000
+Using MPC85xx ADS machine description
+Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
+[snip]
+
+
More About U-Boot Image Types:
------------------------------
--- /dev/null
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic -mrelax
+PLATFORM_LDFLAGS += --relax
#
include $(TOPDIR)/config.mk
-include $(TOPDIR)/include/config.mk
LIB = $(obj)lib$(BOARD).a
# AMCC 440EPx Reference Platform (Sequoia) board
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFA0000
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o flash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_info sdram = {
+ .phys_addr = CFG_SDRAM_BASE,
+ .row_bits = 11,
+ .col_bits = 8,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 5,
+};
+
+void board_init_memories(void)
+{
+ gd->sdram_size = sdram_init(&sdram);
+}
+
+void board_init_info(void)
+{
+ gd->bd->bi_phy_id[0] = 0x10;
+ gd->bd->bi_phy_id[1] = 0x11;
+}
--- /dev/null
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS += --gc-sections
+TEXT_BASE = 0x00000000
+LDSCRIPT = $(obj)board/atmel/atstk1000/u-boot.lds
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATSTK1000_EXT_FLASH
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
+{
+ unsigned long flags;
+
+ flags = disable_interrupts();
+
+ dcache_flush_unlocked();
+
+ writew(0xaa, flash + 0x555);
+ writew(0x55, flash + 0xaaa);
+ writew(0x90, flash + 0x555);
+ info->flash_id = readl(flash);
+ writew(0xff, flash);
+
+ readw(flash);
+
+ if (flags)
+ enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long addr;
+ unsigned int i;
+
+ gd->bd->bi_flashstart = CFG_FLASH_BASE;
+ gd->bd->bi_flashsize = CFG_FLASH_SIZE;
+ gd->bd->bi_flashoffset = __edata_lma - _text;
+
+ flash_info[0].size = CFG_FLASH_SIZE;
+ flash_info[0].sector_count = 135;
+
+ flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
+
+ for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+ flash_info[0].start[i] = addr;
+ for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+ flash_info[0].start[i] = addr;
+
+ return CFG_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n",
+ info->flash_id >> 16, info->flash_id & 0xffff);
+ printf("Size: %ld MB in %d sectors\n",
+ info->size >> 10, info->sector_count);
+}
+
+int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ unsigned long flags;
+ unsigned long start_time;
+ uint16_t *fb, *sb;
+ unsigned int i;
+ int ret;
+ uint16_t status;
+
+ if ((s_first < 0) || (s_first > s_last)
+ || (s_last >= info->sector_count)) {
+ puts("Error: first and/or last sector out of range\n");
+ return ERR_INVAL;
+ }
+
+ for (i = s_first; i < s_last; i++)
+ if (info->protect[i]) {
+ printf("Error: sector %d is protected\n", i);
+ return ERR_PROTECTED;
+ }
+
+ fb = (uint16_t *)uncached(info->start[0]);
+
+ dcache_flush_unlocked();
+
+ for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+ printf("Erasing sector %3d...", i);
+
+ sb = (uint16_t *)uncached(info->start[i]);
+
+ flags = disable_interrupts();
+
+ start_time = get_timer(0);
+
+ /* Unlock sector */
+ writew(0xaa, fb + 0x555);
+ writew(0x70, sb);
+
+ /* Erase sector */
+ writew(0xaa, fb + 0x555);
+ writew(0x55, fb + 0xaaa);
+ writew(0x80, fb + 0x555);
+ writew(0xaa, fb + 0x555);
+ writew(0x55, fb + 0xaaa);
+ writew(0x30, sb);
+
+ /* Wait for completion */
+ ret = ERR_OK;
+ do {
+ /* TODO: Timeout */
+ status = readw(sb);
+ } while ((status != 0xffff) && !(status & 0x28));
+
+ writew(0xf0, fb);
+
+ /*
+ * Make sure the command actually makes it to the bus
+ * before we re-enable interrupts.
+ */
+ readw(fb);
+
+ if (flags)
+ enable_interrupts();
+
+ if (status != 0xffff) {
+ printf("Flash erase error at address 0x%p: 0x%02x\n",
+ sb, status);
+ ret = ERR_PROG_ERROR;
+ break;
+ }
+ }
+
+ if (ctrlc())
+ printf("User interrupt!\n");
+
+ return ERR_OK;
+}
+
+int __flashprog write_buff(flash_info_t *info, uchar *src,
+ ulong addr, ulong count)
+{
+ unsigned long flags;
+ uint16_t *base, *p, *s, *end;
+ uint16_t word, status;
+ int ret = ERR_OK;
+
+ if (addr < info->start[0]
+ || (addr + count) > (info->start[0] + info->size)
+ || (addr + count) < addr) {
+ puts("Error: invalid address range\n");
+ return ERR_INVAL;
+ }
+
+ if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+ puts("Error: misaligned source, destination or count\n");
+ return ERR_ALIGN;
+ }
+
+ base = (uint16_t *)uncached(info->start[0]);
+ end = (uint16_t *)uncached(addr + count);
+
+ flags = disable_interrupts();
+
+ dcache_flush_unlocked();
+ sync_write_buffer();
+
+ for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+ p < end && !ctrlc(); p++, s++) {
+ word = *s;
+
+ writew(0xaa, base + 0x555);
+ writew(0x55, base + 0xaaa);
+ writew(0xa0, base + 0x555);
+ writew(word, p);
+
+ sync_write_buffer();
+
+ /* Wait for completion */
+ do {
+ /* TODO: Timeout */
+ status = readw(p);
+ } while ((status != word) && !(status & 0x28));
+
+ writew(0xf0, base);
+ readw(base);
+
+ if (status != word) {
+ printf("Flash write error at address 0x%p: 0x%02x\n",
+ p, status);
+ ret = ERR_PROG_ERROR;
+ break;
+ }
+ }
+
+ if (flags)
+ enable_interrupts();
+
+ return ret;
+}
+
+#endif /* CONFIG_ATSTK1000_EXT_FLASH */
--- /dev/null
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = CFG_FLASH_BASE;
+ _text = .;
+ .text : {
+ *(.text)
+ *(.text.*)
+ }
+
+ . = ALIGN(CFG_ICACHE_LINESZ);
+ __flashprog_start = .;
+ .flashprog : {
+ *(.flashprog)
+ }
+ . = ALIGN(CFG_ICACHE_LINESZ);
+ __flashprog_end = .;
+
+ . = ALIGN(8);
+ .rodata : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+ _etext = .;
+
+ __data_lma = ALIGN(8);
+ . = CFG_INTRAM_BASE;
+ _data = .;
+ .data : AT(__data_lma) {
+ *(.data)
+ *(.data.*)
+ }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ __u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
+ .u_boot_cmd : AT(__u_boot_cmd_lma) {
+ KEEP(*(.u_boot_cmd))
+ }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(8);
+ _edata = .;
+ __edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
+
+ .bss : AT(__edata_lma) {
+ *(.bss)
+ *(.bss.*)
+ }
+ . = ALIGN(8);
+ _end = .;
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#include "cadmus.h"
+
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+
+static void cds_pci_fixup(void *blob)
+{
+ int len;
+ u32 *map;
+ int slot;
+ int i;
+
+ map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
+
+ len /= sizeof(u32);
+
+ slot = get_pci_slot();
+
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+
+ map+=7;
+ }
+}
+#endif
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+
+ cds_pci_fixup(blob);
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pci_dev_t bridge;
+
+ /* Enable USB and IDE functions */
+ pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+ pciauto_config_device(hose, dev);
+
+ /*
+ * Force the backplane P2P bridge to have a window
+ * open from 0x00000000-0x00001fff in PCI I/O space.
+ * This allows legacy I/O (i8259, etc) on the VIA
+ * southbridge to be accessed.
+ */
+ bridge = PCI_BDF(0,17,0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+ /*
+ * Since the P2P window was forced to cover the fixed
+ * legacy I/O addresses, it is necessary to manually
+ * place the base addresses for the IDE and USB functions
+ * within this window.
+ */
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
--- /dev/null
+#ifndef _MPC85xx_VIA_H
+void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+#endif /* _MPC85xx_VIA_H */
COBJS := $(BOARD).o \
../common/cadmus.o \
- ../common/eeprom.o
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
SOBJS := init.o
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#include "../common/cadmus.h"
#include "../common/eeprom.h"
+#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
*/
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
};
-#endif
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc85xxcds_config_table,
+static struct pci_controller hose[] = {
+ { config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
#endif
};
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
- pci_mpc85xx_init(&hose);
+ pci_mpc85xx_init(hose);
#endif
}
COBJS := $(BOARD).o \
../common/cadmus.o \
- ../common/eeprom.o
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
SOBJS := init.o
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
+#include <miiphy.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
+#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
*/
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
};
-#endif
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc85xxcds_config_table,
+static struct pci_controller hose[] = {
+ { config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
#endif
};
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif
}
+
+int last_stage_init(void)
+{
+ unsigned short temp;
+
+ /* Change the resistors for the PHY */
+ /* This is needed to get the RGMII working for the 1.3+
+ * CDS cards */
+ if (get_board_version() == 0x13) {
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 18);
+
+ miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, &temp);
+
+ temp = (temp & 0xf03f);
+ temp |= 2 << 9; /* 36 ohm */
+ temp |= 2 << 6; /* 39 ohm */
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, temp);
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 3);
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, 0x8000);
+ }
+
+ return 0;
+}
COBJS := $(BOARD).o \
../common/cadmus.o \
- ../common/eeprom.o
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
SOBJS := init.o
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#include "../common/cadmus.h"
#include "../common/eeprom.h"
+#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
}
#endif
-#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it
*/
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
};
-#endif
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
+
+static struct pci_controller hose[] = {
+ {
config_table: pci_mpc85xxcds_config_table,
+ },
+#ifdef CONFIG_MPC85XX_PCI2
+ { }
#endif
};
-#endif /* CONFIG_PCI */
+#endif
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
- pci_mpc85xx_init(&hose);
+ pci_mpc85xx_init(hose);
#endif
}
#ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
- vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
- uchar c = 0xFF;
uint psdmr = CFG_PSDMR;
int i;
#include <asm/immap_85xx.h>
#include <spd.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
* Initialize PCI Devices, report devices found.
*/
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
-};
-#endif
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc85xxads_config_table,
-#endif
-};
+static struct pci_controller hose;
#endif /* CONFIG_PCI */
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
#include <spd.h>
#include <miiphy.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+#endif
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pixis.o sys_eeprom.o
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
--- /dev/null
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Jeff Brown
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8641hpcn board
+# default CCSRBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff01000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc86xx.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xf800_0000 0xf80f_ffff CCSRBAR 1M
+ * 0xf810_0000 0xf81f_ffff PIXIS 1M
+ * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ *
+ * Notes:
+ * CCSRBAR don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR1 0
+#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
+#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
+
+#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
+#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
+
+#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
+#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR8 0
+#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ lis r7,CFG_CCSRBAR@h
+ ori r7,r7,CFG_CCSRBAR@l
+
+ addi r4,r7,0
+ addi r5,r7,0
+
+ /* Skip LAWAR0, start at LAWAR1 */
+ lis r6,LAWBAR1@h
+ ori r6,r6,LAWBAR1@l
+ stwu r6, 0xc28(r4)
+
+ lis r6,LAWAR1@h
+ ori r6,r6,LAWAR1@l
+ stwu r6, 0xc30(r5)
+
+ /* LAWBAR2, LAWAR2 */
+ lis r6,LAWBAR2@h
+ ori r6,r6,LAWBAR2@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR2@h
+ ori r6,r6,LAWAR2@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR3, LAWAR3 */
+ lis r6,LAWBAR3@h
+ ori r6,r6,LAWBAR3@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR3@h
+ ori r6,r6,LAWAR3@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR4, LAWAR4 */
+ lis r6,LAWBAR4@h
+ ori r6,r6,LAWBAR4@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR4@h
+ ori r6,r6,LAWAR4@l
+ stwu r6, 0x20(r5)
+ /* LAWBAR5, LAWAR5 */
+ lis r6,LAWBAR5@h
+ ori r6,r6,LAWBAR5@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR5@h
+ ori r6,r6,LAWAR5@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR6, LAWAR6 */
+ lis r6,LAWBAR6@h
+ ori r6,r6,LAWBAR6@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR6@h
+ ori r6,r6,LAWAR6@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR7, LAWAR7 */
+ lis r6,LAWBAR7@h
+ ori r6,r6,LAWBAR7@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR7@h
+ ori r6,r6,LAWAR7@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR8, LAWAR8 */
+ lis r6,LAWBAR8@h
+ ori r6,r6,LAWBAR8@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR8@h
+ ori r6,r6,LAWAR8@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR9, LAWAR9 */
+ lis r6,LAWBAR9@h
+ ori r6,r6,LAWBAR9@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR9@h
+ ori r6,r6,LAWAR9@l
+ stwu r6, 0x20(r5)
+
+ blr
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <spd.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#include "pixis.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
+
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MPC8641HPCN\n");
+
+#ifdef CONFIG_PCI
+
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_pex_t *pex1 = &immap->im_pex1;
+
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+ uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+ uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
+
+ if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+ || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+ debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
+ if (pex1->pme_msg_det) {
+ pex1->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pex1->pme_msg_det);
+ }
+ debug("\n");
+ } else {
+ puts("PCI-EXPRESS 1: Disabled\n");
+ }
+
+#else
+ puts("PCI-EXPRESS1: Disabled\n");
+#endif
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+#if defined(CFG_RAMBOOT)
+ puts(" DDR: ");
+ return dram_size;
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ puts("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+long int
+fixed_sdram(void)
+{
+#if !defined(CFG_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+ ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode_1 = CFG_DDR_MODE_1;
+ ddr->sdram_mode_2 = CFG_DDR_MODE_2;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->sdram_data_init = CFG_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
+ ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
+ ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
+
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000008D;
+ ddr->err_sbe = 0x00ff0000;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+#if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
+#else
+ ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
+ ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+#endif
+ asm("sync; isync");
+
+ udelay(500);
+#endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
+ {}
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc86xxcts_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc86xx_init(struct pci_controller *hose);
+
+ pci_mpc86xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
+
+
+void
+mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ char cmd;
+ ulong val;
+ ulong corepll;
+
+ /*
+ * No args is a simple reset request.
+ */
+ if (argc <= 1) {
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+ /* not reached */
+ }
+
+ cmd = argv[1][1];
+ switch (cmd) {
+ case 'f': /* reset with frequency changed */
+ if (argc < 5)
+ goto my_usage;
+ read_from_px_regs(0);
+
+ val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
+
+ corepll = strfractoint(argv[3]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0 and VCTL\n");
+ read_from_px_regs(1);
+ puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
+ set_px_go();
+ } else
+ goto my_usage;
+
+ while (1) ; /* Not reached */
+
+ case 'l':
+ if (argv[2][1] == 'f') {
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ /* reset with frequency changed */
+ val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
+
+ corepll = strfractoint(argv[4]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[5],
+ NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs(1);
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
+ set_px_go_with_watchdog();
+ } else
+ goto my_usage;
+
+ while (1) ; /* Not reached */
+
+ } else if (argv[2][1] == 'd') {
+ /*
+ * Reset from alternate bank without changing
+ * frequencies but with watchdog timer enabled.
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
+ set_px_go_with_watchdog();
+ while (1) ; /* Not reached */
+
+ } else {
+ /*
+ * Reset from next bank without changing
+ * frequency and without watchdog timer enabled.
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ if (argc > 2)
+ goto my_usage;
+ puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Resetting board to boot from the other bank....\n");
+ set_px_go();
+ }
+
+ default:
+ goto my_usage;
+ }
+
+my_usage:
+ puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
+ puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
+ puts(" reset altbank [wd]\n");
+ puts("For example: reset cf 40 2.5 10\n");
+ puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
+}
+
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i, go_bit, rd_clks;
+ ulong val = 0;
+
+ go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+ go_bit &= 0x01;
+
+ rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ rd_clks &= 0x1C;
+
+ /*
+ * Only if both go bit and the SCLK bit in VCFGEN0 are set
+ * should we be using the AUX register. Remember, we also set the
+ * GO bit to boot from the alternate bank on the on-board flash
+ */
+
+ if (go_bit) {
+ if (rd_clks == 0x1c)
+ i = in8(PIXIS_BASE + PIXIS_AUX);
+ else
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ } else {
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ }
+
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33000000;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66000000;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 134000000;
+ break;
+ case 7:
+ val = 166000000;
+ break;
+ }
+
+ return val;
+}
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <mpc86xx.h>
+
+#include "pixis.h"
+
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+int set_px_sysclk(ulong sysclk)
+{
+ u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+ switch (sysclk) {
+ case 33:
+ sysclk_s = 0x04;
+ sysclk_r = 0x04;
+ sysclk_v = 0x07;
+ sysclk_aux = 0x00;
+ break;
+ case 40:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x20;
+ sysclk_aux = 0x01;
+ break;
+ case 50:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x2A;
+ sysclk_aux = 0x02;
+ break;
+ case 66:
+ sysclk_s = 0x01;
+ sysclk_r = 0x04;
+ sysclk_v = 0x04;
+ sysclk_aux = 0x03;
+ break;
+ case 83:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x04;
+ break;
+ case 100:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x5C;
+ sysclk_aux = 0x05;
+ break;
+ case 134:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x3B;
+ sysclk_aux = 0x06;
+ break;
+ case 166:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x07;
+ break;
+ default:
+ printf("Unsupported SYSCLK frequency.\n");
+ return 0;
+ }
+
+ vclkh = (sysclk_s << 5) | sysclk_r;
+ vclkl = sysclk_v;
+
+ out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
+ out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+
+ out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
+
+ return 1;
+}
+
+
+int set_px_mpxpll(ulong mpxpll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch (mpxpll) {
+ case 2:
+ case 4:
+ case 6:
+ case 8:
+ case 10:
+ case 12:
+ case 14:
+ case 16:
+ val = (u8) mpxpll;
+ break;
+ default:
+ printf("Unsupported MPXPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+ tmp = (tmp & 0xF0) | (val & 0x0F);
+ out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+
+ return 1;
+}
+
+
+int set_px_corepll(ulong corepll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch ((int)corepll) {
+ case 20:
+ val = 0x08;
+ break;
+ case 25:
+ val = 0x0C;
+ break;
+ case 30:
+ val = 0x10;
+ break;
+ case 35:
+ val = 0x1C;
+ break;
+ case 40:
+ val = 0x14;
+ break;
+ case 45:
+ val = 0x0E;
+ break;
+ default:
+ printf("Unsupported COREPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+ tmp = (tmp & 0xE0) | (val & 0x1F);
+ out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+
+ return 1;
+}
+
+
+void read_from_px_regs(int set)
+{
+ u8 mask = 0x1C;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+}
+
+
+void read_from_px_regs_altbank(int set)
+{
+ u8 mask = 0x04;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+}
+
+
+void set_altbank(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+ tmp ^= 0x40;
+
+ out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+}
+
+
+void set_px_go(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x01;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+void set_px_go_with_watchdog(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x09;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ /* setting VCTL[WDEN] to 0 to disable watch dog */
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp &= ~0x08;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ diswd, 1, 0, disable_watchdog,
+ "diswd - Disable watchdog timer \n",
+ NULL);
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+
+ulong strfractoint(uchar *strptr)
+{
+ int i, j, retval;
+ int mulconst;
+ int intarr_len = 0, decarr_len = 0, no_dec = 0;
+ ulong intval = 0, decval = 0;
+ uchar intarr[3], decarr[3];
+
+ /* Assign the integer part to intarr[]
+ * If there is no decimal point i.e.
+ * if the ratio is an integral value
+ * simply create the intarr.
+ */
+ i = 0;
+ while (strptr[i] != 46) {
+ if (strptr[i] == 0) {
+ no_dec = 1;
+ break;
+ }
+ intarr[i] = strptr[i];
+ i++;
+ }
+
+ /* Assign length of integer part to intarr_len. */
+ intarr_len = i;
+ intarr[i] = '\0';
+
+ if (no_dec) {
+ /* Currently needed only for single digit corepll ratios */
+ mulconst = 10;
+ decval = 0;
+ } else {
+ j = 0;
+ i++; /* Skipping the decimal point */
+ while ((strptr[i] > 47) && (strptr[i] < 58)) {
+ decarr[j] = strptr[i];
+ i++;
+ j++;
+ }
+
+ decarr_len = j;
+ decarr[j] = '\0';
+
+ mulconst = 1;
+ for (i = 0; i < decarr_len; i++)
+ mulconst *= 10;
+ decval = simple_strtoul(decarr, NULL, 10);
+ }
+
+ intval = simple_strtoul(intarr, NULL, 10);
+ intval = intval * mulconst;
+
+ retval = intval + decval;
+
+ return retval;
+}
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern int set_px_sysclk(ulong sysclk);
+extern int set_px_mpxpll(ulong mpxpll);
+extern int set_px_corepll(ulong corepll);
+extern void read_from_px_regs(int set);
+extern void read_from_px_regs_altbank(int set);
+extern void set_altbank(void);
+extern void set_px_go(void);
+extern void set_px_go_with_watchdog(void);
+extern int disable_watchdog(cmd_tbl_t *cmdtp,
+ int flag, int argc, char *argv[]);
+extern ulong strfractoint(uchar *strptr);
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CFG_ID_EEPROM
+typedef struct {
+ unsigned char id[4]; /* 0x0000 - 0x0003 */
+ unsigned char sn[12]; /* 0x0004 - 0x000F */
+ unsigned char errata[5]; /* 0x0010 - 0x0014 */
+ unsigned char date[7]; /* 0x0015 - 0x001a */
+ unsigned char res_1[37]; /* 0x001b - 0x003f */
+ unsigned char tab_size; /* 0x0040 */
+ unsigned char tab_flag; /* 0x0041 */
+ unsigned char mac[8][6]; /* 0x0042 - 0x0071 */
+ unsigned char res_2[126]; /* 0x0072 - 0x00ef */
+ unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */
+} EEPROM_data;
+
+static EEPROM_data mac_data;
+
+int mac_show(void)
+{
+ int i;
+ unsigned char ethaddr[8][18];
+
+ printf("ID %c%c%c%c\n",
+ mac_data.id[0],
+ mac_data.id[1],
+ mac_data.id[2],
+ mac_data.id[3]);
+ printf("Errata %c%c%c%c%c\n",
+ mac_data.errata[0],
+ mac_data.errata[1],
+ mac_data.errata[2],
+ mac_data.errata[3],
+ mac_data.errata[4]);
+ printf("Date %c%c%c%c%c%c%c\n",
+ mac_data.date[0],
+ mac_data.date[1],
+ mac_data.date[2],
+ mac_data.date[3],
+ mac_data.date[4],
+ mac_data.date[5],
+ mac_data.date[6]);
+ for (i = 0; i < 8; i++) {
+ sprintf(ethaddr[i],
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac_data.mac[i][0],
+ mac_data.mac[i][1],
+ mac_data.mac[i][2],
+ mac_data.mac[i][3],
+ mac_data.mac[i][4],
+ mac_data.mac[i][5]);
+ printf("MAC %d %s\n", i, ethaddr[i]);
+ }
+
+ setenv("ethaddr", ethaddr[0]);
+ setenv("eth1addr", ethaddr[1]);
+ setenv("eth2addr", ethaddr[2]);
+ setenv("eth3addr", ethaddr[3]);
+
+ return 0;
+}
+
+int mac_read(void)
+{
+ int ret, length;
+ unsigned int crc = 0;
+ unsigned char dev = ID_EEPROM_ADDR, *data;
+
+ length = sizeof(EEPROM_data);
+ ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length);
+ if (ret) {
+ printf("Read failed.\n");
+ return -1;
+ }
+
+ data = (unsigned char *)(&mac_data);
+ printf("Check CRC on reading ...");
+ crc = crc32(crc, data, length - 4);
+ if (crc != mac_data.crc) {
+ printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",
+ mac_data.crc, crc);
+ return -1;
+ } else {
+ printf("CRC OK\n");
+ mac_show();
+ }
+ return 0;
+}
+
+int mac_prog(void)
+{
+ int ret, i, length;
+ unsigned int crc = 0;
+ unsigned char dev = ID_EEPROM_ADDR, *ptr;
+ unsigned char *eeprom_data = (unsigned char *)(&mac_data);
+
+ for (i = 0; i < sizeof(mac_data.res_1); i++)
+ mac_data.res_1[i] = 0;
+ for (i = 0; i < sizeof(mac_data.res_2); i++)
+ mac_data.res_2[i] = 0;
+ length = sizeof(EEPROM_data);
+ crc = crc32(crc, eeprom_data, length - 4);
+ mac_data.crc = crc;
+ for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) {
+ ret =
+ i2c_write(dev, i, 1, ptr,
+ (length - i) < 8 ? (length - i) : 8);
+ udelay(5000); /* 5ms write cycle timing */
+ if (ret)
+ break;
+ }
+ if (ret) {
+ printf("Programming failed.\n");
+ return -1;
+ } else {
+ printf("Programming %d bytes. Reading back ...\n", length);
+ mac_read();
+ }
+ return 0;
+}
+
+int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ char cmd = 's';
+ unsigned long long mac_val;
+
+ if (i2c_probe(ID_EEPROM_ADDR) != 0)
+ return -1;
+
+ if (argc > 1) {
+ cmd = argv[1][0];
+ switch (cmd) {
+ case 'r': /* display */
+ mac_read();
+ break;
+ case 's': /* save */
+ mac_prog();
+ break;
+ case 'i': /* id */
+ for (i = 0; i < 4; i++) {
+ mac_data.id[i] = argv[2][i];
+ }
+ break;
+ case 'n': /* serial number */
+ for (i = 0; i < 12; i++) {
+ mac_data.sn[i] = argv[2][i];
+ }
+ break;
+ case 'e': /* errata */
+ for (i = 0; i < 5; i++) {
+ mac_data.errata[i] = argv[2][i];
+ }
+ break;
+ case 'd': /* date */
+ for (i = 0; i < 7; i++) {
+ mac_data.date[i] = argv[2][i];
+ }
+ break;
+ case 'p': /* number of ports */
+ mac_data.tab_size =
+ (unsigned char)simple_strtoul(argv[2], NULL, 16);
+ break;
+ case '0': /* mac 0 */
+ case '1': /* mac 1 */
+ case '2': /* mac 2 */
+ case '3': /* mac 3 */
+ case '4': /* mac 4 */
+ case '5': /* mac 5 */
+ case '6': /* mac 6 */
+ case '7': /* mac 7 */
+ mac_val = simple_strtoull(argv[2], NULL, 16);
+ for (i = 0; i < 6; i++) {
+ mac_data.mac[cmd - '0'][i] =
+ *((unsigned char *)
+ (((unsigned int)(&mac_val)) + i + 2));
+ }
+ break;
+ case 'h': /* help */
+ default:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ break;
+ }
+ } else {
+ mac_show();
+ }
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ int length, i;
+ unsigned char dev = ID_EEPROM_ADDR;
+ unsigned char *data;
+ unsigned char ethaddr[4][18];
+ unsigned char enetvar[32];
+ unsigned int crc = 0;
+
+ length = sizeof(EEPROM_data);
+ if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) {
+ printf("Read failed.\n");
+ return -1;
+ }
+
+ data = (unsigned char *)(&mac_data);
+ crc = crc32(crc, data, length - 4);
+ if (crc != mac_data.crc) {
+ return -1;
+ } else {
+ for (i = 0; i < 4; i++) {
+ if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) {
+ sprintf(ethaddr[i],
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac_data.mac[i][0],
+ mac_data.mac[i][1],
+ mac_data.mac[i][2],
+ mac_data.mac[i][3],
+ mac_data.mac[i][4],
+ mac_data.mac[i][5]);
+ sprintf(enetvar,
+ i ? "eth%daddr" : "ethaddr",
+ i);
+ setenv(enetvar, ethaddr[i]);
+ }
+ }
+ }
+ return 0;
+}
+#endif /* CFG_ID_EEPROM */
--- /dev/null
+/*
+ * (C) Copyright 2004, Freescale, Inc.
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Jeff Brown
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFF00100 :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFF70000 :
+ {
+ cpu/mpc86xx/start.o (.bootpg)
+ board/mpc8641hpcn/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + 1024;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc86xx/start.o (.text)
+ board/mpc8641hpcn/init.o (.text)
+ cpu/mpc86xx/traps.o (.text)
+ cpu/mpc86xx/interrupts.o (.text)
+ cpu/mpc86xx/cpu_init.o (.text)
+ cpu/mpc86xx/cpu.o (.text)
+ cpu/mpc86xx/speed.o (.text)
+ cpu/mpc86xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o oftree.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
-$(obj)%.dtb: $(src)%.dts
- dtc -f -V 0x10 -I dts -O dtb $< >$@
-
-$(obj)%.c: $(obj)%.dtb
- xxd -i $< \
- | sed -e "s/^unsigned char/const unsigned char/g" \
- | sed -e "s/^unsigned int/const unsigned int/g" > $@
-
#########################################################################
# defines $(obj).depend target
+++ /dev/null
-/ {
- model = "STXXTC V1";
- compatible = "STXXTC";
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- linux,phandle = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- PowerPC,MPC870@0 {
- linux,phandle = <3>;
- name = "PowerPC,MPC870";
- device_type = "cpu";
- reg = <0>;
- clock-frequency = <0>; /* place-holder for runtime fillup */
- timebase-frequency = <0>; /* dido */
- linux,boot-cpu;
- i-cache-size = <2000>;
- d-cache-size = <2000>;
- 32-bit;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <00000000 00000000 00000000 20000000>;
- };
-
- /* copy of the bd_t information (place-holders) */
- bd_t {
- memstart = <0>;
- memsize = <0>;
- flashstart = <0>;
- flashsize = <0>;
- flashoffset = <0>;
- sramstart = <0>;
- sramsize = <0>;
-
- immr_base = <0>;
-
- bootflags = <0>;
- ip_addr = <0>;
- enetaddr = [ 00 00 00 00 00 00 ];
- ethspeed = <0>;
- intfreq = <0>;
- busfreq = <0>;
-
- baudrate = <0>;
- };
-
-};
void pci_init_board (void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init (struct pci_controller *hose);
-
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o ethaddr.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MarelV38B board
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+TEXT_BASE = 0xFF000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+#define GPIO_ENABLE (MPC5XXX_WU_GPIO)
+
+/* Open Drain Emulation Register */
+#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04)
+
+/* Data Direction Register */
+#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08)
+
+/* Data Value Out Register */
+#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C)
+
+/* Interrupt Enable Register */
+#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10)
+
+/* Individual Interrupt Enable Register */
+#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14)
+
+/* Interrupt Type Register */
+#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18)
+
+/* Master Enable Register */
+#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C)
+
+/* Data Input Value Register */
+#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20)
+
+/* Status Register */
+#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24)
+
+#define PSC6_0 0x10000000
+#define WKUP_7 0x80000000
+
+/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */
+#define GPIO_PIN PSC6_0
+
+#define NO_ERROR 0
+#define ERR_NO_NUMBER 1
+#define ERR_BAD_NUMBER 2
+
+typedef volatile unsigned long GPIO_REG;
+typedef GPIO_REG *GPIO_REG_PTR;
+
+static int is_high(void);
+static int check_device(void);
+static void io_out(int value);
+static void io_input(void);
+static void io_output(void);
+static void init_gpio(void);
+static void read_byte(unsigned char *data);
+static void write_byte(unsigned char command);
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr);
+void board_get_enetaddr(uchar *enetaddr);
+
+static int is_high()
+{
+ return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN);
+}
+
+static void io_out(int value)
+{
+ if (value)
+ *((vu_long *) GPIO_DVOR) |= GPIO_PIN;
+ else
+ *((vu_long *) GPIO_DVOR) &= ~GPIO_PIN;
+}
+
+static void io_input()
+{
+ *((vu_long *) GPIO_DDR) &= ~GPIO_PIN;
+ udelay(3); /* allow input to settle */
+}
+
+static void io_output()
+{
+ *((vu_long *) GPIO_DDR) |= GPIO_PIN;
+}
+
+static void init_gpio()
+{
+ *((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */
+}
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr)
+{
+#define NBYTES 28
+ unsigned char crcval, i;
+ unsigned char buf[NBYTES];
+
+ *perr = 0;
+ crcval = 0;
+
+ for (i=0; i<NBYTES; i++)
+
+
+ if (!check_device())
+ *perr = ERR_NO_NUMBER;
+ else {
+ *perr = NO_ERROR;
+ write_byte(0xCC); /* skip ROM (0xCC) */
+ write_byte(0xF0); /* Read memory command 0xF0 */
+ write_byte(0x00); /* Address TA1=0, TA2=0 */
+ write_byte(0x00);
+ read_byte(&crcval); /* Read CRC of address and command */
+
+ for (i=0; i<NBYTES; i++)
+ read_byte( &buf[i] );
+ }
+ if (strncmp((const char*) &buf[11], "MAREL IEEE 802.3", 16)) {
+ *perr = ERR_BAD_NUMBER;
+ psernum[0] = 0x00;
+ psernum[1] = 0xE0;
+ psernum[2] = 0xEE;
+ psernum[3] = 0xFF;
+ psernum[4] = 0xFF;
+ psernum[5] = 0xFF;
+ }
+ else {
+ psernum[0] = 0x00;
+ psernum[1] = 0xE0;
+ psernum[2] = 0xEE;
+ psernum[3] = buf[7];
+ psernum[4] = buf[6];
+ psernum[5] = buf[5];
+ }
+}
+
+static int check_device()
+{
+ int found;
+
+ io_output();
+ io_out(0);
+ udelay(500); /* must be at least 480 us low pulse */
+
+ io_input();
+ udelay(60);
+
+ found = (is_high() == 0) ? 1 : 0;
+ udelay(500); /* must be at least 480 us low pulse */
+
+ return found;
+}
+
+static void write_byte(unsigned char command)
+{
+ char i;
+
+ for (i=0; i<8; i++) {
+ /* 1 us to 15 us low pulse starts bit slot */
+ /* Start with high pulse for 3 us */
+ io_input();
+
+ udelay(3);
+
+ io_out(0);
+ io_output();
+
+ udelay(3);
+
+ if (command & 0x01) {
+ /* 60 us high for 1-bit */
+ io_input();
+ udelay(60);
+ }
+ else {
+ /* 60 us low for 0-bit */
+ udelay(60);
+ }
+ /* Leave pin as input */
+ io_input();
+
+ command = command >> 1;
+ }
+}
+
+static void read_byte(unsigned char *data)
+{
+ unsigned char i, rdat = 0;
+
+ for (i=0; i<8; i++) {
+ /* read one bit from one-wire device */
+
+ /* 1 - 15 us low starts bit slot */
+ io_out(0);
+ io_output();
+ udelay(0);
+
+ /* allow line to be pulled high */
+ io_input();
+
+ /* delay 10 us */
+ udelay(10);
+
+ /* now sample input status */
+ if (is_high())
+ rdat = (rdat >> 1) | 0x80;
+ else
+ rdat = rdat >> 1;
+
+ udelay(60); /* at least 60 us */
+ }
+ /* copy the return value */
+ *data = rdat;
+}
+
+void board_get_enetaddr(uchar *enetaddr)
+{
+ unsigned char sn[6], err=NO_ERROR;
+
+ init_gpio();
+
+ read_2501_memory(sn, &err);
+
+ if (err == NO_ERROR) {
+ sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
+ sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
+ printf("MAC address: %s\n", enetaddr);
+ setenv("ethaddr", enetaddr);
+ }
+ else {
+ sprintf(enetaddr, "00:01:02:03:04:05");
+ printf("Error reading MAC address.\n");
+ printf("Setting default to %s\n", enetaddr);
+ setenv("ethaddr", enetaddr);
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc5xxx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+#ifndef CFG_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif /* !CFG_RAMBOOT */
+
+
+long int initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+
+#ifndef CFG_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0)
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ else
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else
+ dramsize2 = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20))
+ dramsize2 = 0;
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0)
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ else
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+#else /* CFG_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CFG_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+ return dramsize + dramsize2;
+}
+
+
+int checkboard (void)
+{
+ puts("Board: MarelV38B\n");
+ return 0;
+}
+
+
+int board_early_init_r(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write access for detection process.
+ * Note that CS_BOOT cannot be cleared when executing in flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+ return 0;
+}
+
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4 0x01000000UL
+
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ /* Deassert reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+}
+
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(500000);
+ } else
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+
+void led_d4_on(void)
+{
+ /* TIMER7 as GPIO output low */
+ *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24;
+}
+
+
+void led_d4_off(void)
+{
+ /* TIMER7 as GPIO output high */
+ *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34;
+}
+
+
+void hw_watchdog_reset(void)
+{
+/* TODO fill this in */
+}
memsize.o miiphybb.o miiphyutil.o \
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
usb.o usb_kbd.o usb_storage.o \
- virtex2.o xilinx.o crc16.o xyzModem.o
+ virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
U_BOOT_CMD(
- reset, 1, 0, do_reset,
+ reset, CFG_MAXARGS, 1, do_reset,
"reset - Perform RESET of the CPU\n",
NULL
);
"[addr [arg ...]]\n - boot application image stored in memory\n"
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
"\t'arg' can be the address of an initrd image\n"
+#ifdef CONFIG_OF_FLAT_TREE
+ "\tWhen booting a Linux kernel which requires a flat device-tree\n"
+ "\ta third argument is required which is the address of the of the\n"
+ "\tdevice-tree blob. To boot that kernel without an initrd image,\n"
+ "\tuse a '-' for the second argument. If you do not pass a third\n"
+ "\ta bd_info struct will be passed instead\n"
+#endif
);
#ifdef CONFIG_SILENT_CONSOLE
}
#endif /* CONFIG_SILENT_CONSOLE */
-#ifdef CONFIG_OF_FLAT_TREE
-extern const unsigned char oftree_dtb[];
-extern const unsigned int oftree_dtb_len;
-#endif
-
#ifdef CONFIG_PPC
-static void
+static void __attribute__((noinline))
do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
int argc, char *argv[],
ulong addr,
void (*kernel)(bd_t *, ulong, ulong, ulong, ulong);
image_header_t *hdr = &header;
#ifdef CONFIG_OF_FLAT_TREE
- char *of_flat_tree;
+ char *of_flat_tree = NULL;
#endif
if ((s = getenv ("initrd_high")) != NULL) {
/*
* Check if there is an initrd image
*/
+
+#ifdef CONFIG_OF_FLAT_TREE
+ /* Look for a '-' which indicates to ignore the ramdisk argument */
+ if (argc >= 3 && strcmp(argv[2], "-") == 0) {
+ debug ("Skipping initrd\n");
+ len = data = 0;
+ }
+ else
+#endif
if (argc >= 3) {
+ debug ("Not skipping initrd\n");
SHOW_BOOT_PROGRESS (9);
addr = simple_strtoul(argv[2], NULL, 16);
len = data = 0;
}
+#ifdef CONFIG_OF_FLAT_TREE
+ if(argc > 3) {
+ of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
+ hdr = (image_header_t *)of_flat_tree;
+
+ if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
+#ifndef CFG_NO_FLASH
+ if (addr2info((ulong)of_flat_tree) != NULL) {
+ printf ("Cannot modify flat device tree stored in flash\n" \
+ "Copy to memory before using the bootm command\n");
+ return;
+ }
+#endif
+ } else if (ntohl(hdr->ih_magic) == IH_MAGIC) {
+ printf("## Flat Device Tree Image at %08lX\n", hdr);
+ print_image_hdr(hdr);
+
+ if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) &&
+ ((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) {
+ printf ("ERROR: Load address overwrites Flat Device Tree uImage\n");
+ return;
+ }
+
+ printf(" Verifying Checksum ... ");
+ memmove (&header, (char *)hdr, sizeof(image_header_t));
+ checksum = ntohl(header.ih_hcrc);
+ header.ih_hcrc = 0;
+
+ if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) {
+ printf("ERROR: Flat Device Tree header checksum is invalid\n");
+ return;
+ }
+
+ checksum = ntohl(hdr->ih_dcrc);
+ addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t));
+ len = ntohl(hdr->ih_size);
+
+ if(checksum != crc32(0, (uchar *)addr, len)) {
+ printf("ERROR: Flat Device Tree checksum is invalid\n");
+ return;
+ }
+ printf("OK\n");
+
+ if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) {
+ printf ("ERROR: uImage not Flat Device Tree type\n");
+ return;
+ }
+ if (ntohl(hdr->ih_comp) != IH_COMP_NONE) {
+ printf("ERROR: uImage is not uncompressed\n");
+ return;
+ }
+ if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+ printf ("ERROR: uImage data is not a flat device tree\n");
+ return;
+ }
+
+ memmove((void *)ntohl(hdr->ih_load),
+ (void *)(of_flat_tree + sizeof(image_header_t)),
+ ntohl(hdr->ih_size));
+ of_flat_tree = (char *)ntohl(hdr->ih_load);
+ } else {
+ printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree);
+ return;
+ }
+ printf (" Booting using flat device tree at 0x%x\n",
+ of_flat_tree);
+ } else if(getenv("disable_of") == NULL) {
+ printf ("ERROR: bootm needs flat device tree as third argument\n");
+ return;
+ }
+#endif
if (!data) {
debug ("No initrd\n");
}
initrd_end = 0;
}
-#ifdef CONFIG_OF_FLAT_TREE
- if (initrd_start == 0)
- of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE -
- sizeof(bd_t)) & ~0xF);
- else
- of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE -
- sizeof(bd_t)) & ~0xF);
-#endif
-
debug ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)kernel);
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
#else
- ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end);
+ ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
/* ft_dump_blob(of_flat_tree); */
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
if (getenv("disable_of") != NULL)
(*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end,
cmd_start, cmd_end);
- else
+ else {
+ ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
+ /* ft_dump_blob(of_flat_tree); */
(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
-
+ }
+
#endif
}
#endif /* CONFIG_PPC */
case IH_TYPE_MULTI: type = "Multi-File Image"; break;
case IH_TYPE_FIRMWARE: type = "Firmware"; break;
case IH_TYPE_SCRIPT: type = "Script"; break;
+ case IH_TYPE_FLATDT: type = "Flat Device Tree"; break;
default: type = "Unknown Image"; break;
}
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CFG_ID_EEPROM
+
+extern int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+U_BOOT_CMD(
+ mac, 3, 1, do_mac,
+ "mac - display and program the system ID and MAC addresses in EEPROM\n",
+ "[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n"
+ "read\n"
+ " - show content of mac\n"
+ "mac save\n"
+ " - save to the EEPROM\n"
+ "mac id\n"
+ " - program system id\n"
+ "mac num\n"
+ " - program system serial number\n"
+ "mac errata\n"
+ " - program errata data\n"
+ "mac date\n"
+ " - program data date\n"
+ "mac ports\n"
+ " - program the number of ports\n"
+ "mac 0\n"
+ " - program the MAC address for port 0\n"
+ "mac 1\n"
+ " - program the MAC address for port 1\n"
+ "mac 2\n"
+ " - program the MAC address for port 2\n"
+ "mac 3\n"
+ " - program the MAC address for port 3\n"
+ "mac 4\n"
+ " - program the MAC address for port 4\n"
+ "mac 5\n"
+ " - program the MAC address for port 5\n"
+ "mac 6\n"
+ " - program the MAC address for port 6\n"
+ "mac 7\n"
+ " - program the MAC address for port 7\n"
+);
+#endif /* CFG_ID_EEPROM */
printf("Device %d: %s", dev, nand_info[dev].name);
puts("... is now current device\n");
nand_curr_device = dev;
+
+#ifdef CFG_NAND_SELECT_DEVICE
+ /*
+ * Select the chip in the board/cpu specific driver
+ */
+ board_nand_select_device(nand_info[dev].priv, dev);
+#endif
+
return 0;
}
#else
#define SCSI_DEV_ID CONFIG_SCSI_DEV_ID
#endif
+#elif defined CONFIG_SATA_ULI5288
+
+#define SCSI_VEND_ID 0x10b9
+#define SCSI_DEV_ID 0x5288
+
#else
-#error CONFIG_SCSI_SYM53C8XX must be defined
+#error no scsi device defined
#endif
/*
* OF flat tree builder
+ * Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com>
+ * Updated by: Matthew McClintock <msm@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*/
#include <common.h>
#include <ft_build.h>
+#undef DEBUG
+
/* align addr on a size boundary - adjust address up if needed -- Cort */
#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
+#ifndef CONFIG_OF_BOOT_CPU
+#define CONFIG_OF_BOOT_CPU 0
+#endif
+#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64))
static void ft_put_word(struct ft_cxt *cxt, u32 v)
{
- if (cxt->overflow) /* do nothing */
- return;
-
- /* check for overflow */
- if (cxt->p + 4 > cxt->pstr) {
- cxt->overflow = 1;
- return;
- }
+ memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p);
*(u32 *) cxt->p = cpu_to_be32(v);
- cxt->p += 4;
+ cxt->p += sizeof(u32);
+ cxt->p_end += sizeof(u32);
}
static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz)
{
- u8 *p;
+ int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz,
+ sizeof(u32))) - cxt->p;
- if (cxt->overflow) /* do nothing */
- return;
-
- /* next pointer pos */
- p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4);
+ memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p);
- /* check for overflow */
- if (p > cxt->pstr) {
- cxt->overflow = 1;
- return;
- }
+ /* make sure the last bytes are zeroed */
+ memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0,
+ (aligned_size % sizeof(u32)));
memcpy(cxt->p, data, sz);
- if ((sz & 3) != 0)
- memset(cxt->p + sz, 0, 4 - (sz & 3));
- cxt->p = p;
+
+ cxt->p += aligned_size;
+ cxt->p_end += aligned_size;
}
void ft_begin_node(struct ft_cxt *cxt, const char *name)
{
u8 *p;
- p = cxt->pstr;
- while (p < cxt->pstr_begin) {
- if (strcmp(p, name) == 0)
- return p - cxt->p_begin;
- p += strlen(p) + 1;
+ p = cxt->p;
+ while (p < cxt->p_end) {
+ if (strcmp((char *)p, name) == 0)
+ return p - cxt->p;
+ p += strlen((char *)p) + 1;
}
return -1;
void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz)
{
- int len, off;
-
- if (cxt->overflow)
- return;
-
- len = strlen(name) + 1;
+ int off = 0;
off = lookup_string(cxt, name);
if (off == -1) {
- /* check if we have space */
- if (cxt->p + 12 + sz + len > cxt->pstr) {
- cxt->overflow = 1;
- return;
- }
-
- cxt->pstr -= len;
- memcpy(cxt->pstr, name, len);
- off = cxt->pstr - cxt->p_begin;
+ memcpy(cxt->p_end, name, strlen(name) + 1);
+ off = cxt->p_end - cxt->p;
+ cxt->p_end += strlen(name) + 1;
}
/* now put offset from beginning of *STRUCTURE* */
{
u32 v = cpu_to_be32((u32) val);
- ft_prop(cxt, name, &v, 4);
+ ft_prop(cxt, name, &v, sizeof(u32));
}
-/* start construction of the flat OF tree */
-void ft_begin(struct ft_cxt *cxt, void *blob, int max_size)
+/* pick up and start working on a tree in place */
+void ft_init_cxt(struct ft_cxt *cxt, void *blob)
{
struct boot_param_header *bph = blob;
- u32 off;
- /* clear the cxt */
memset(cxt, 0, sizeof(*cxt));
cxt->bph = bph;
- cxt->max_size = max_size;
-
- /* zero everything in the header area */
- memset(bph, 0, sizeof(*bph));
-
- bph->magic = cpu_to_be32(OF_DT_HEADER);
- bph->version = cpu_to_be32(0x10);
- bph->last_comp_version = cpu_to_be32(0x10);
+ bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU;
- /* start pointers */
- cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8);
- cxt->pres = cxt->pres_begin;
-
- off = (unsigned long)cxt->pres_begin - (unsigned long)bph;
- bph->off_mem_rsvmap = cpu_to_be32(off);
-
- ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
- ((u64 *) cxt->pres)[1] = 0;
+ /* find beginning and end of reserve map table (zeros in last entry) */
+ cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap;
+ while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 &&
+ ((uint64_t *)cxt->p_rsvmap)[1] != 0 ) {
+ cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
+ }
- cxt->p_anchor = cxt->pres + 16; /* over the terminator */
+ cxt->p_start = (u8 *)bph + bph->off_dt_struct;
+ cxt->p_end = (u8 *)bph + bph->totalsize;
+ cxt->p = (u8 *)bph + bph->off_dt_strings;
}
/* add a reserver physical area to the rsvmap */
-void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size)
+void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend)
{
- ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
- ((u64 *) cxt->pres)[1] = cpu_to_be64(size);
-
- cxt->pres += 16; /* advance */
-
- ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
- ((u64 *) cxt->pres)[1] = 0;
-
- /* keep track of size */
- cxt->res_size = cxt->pres + 16 - cxt->pres_begin;
-
- cxt->p_anchor = cxt->pres + 16; /* over the terminator */
+ memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap,
+ cxt->p_end - cxt->p_rsvmap);
+
+ ((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart);
+ ((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend);
+ ((u64 *)cxt->p_rsvmap)[2] = 0;
+ ((u64 *)cxt->p_rsvmap)[3] = 0;
+
+ cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
+ cxt->p_start += SIZE_OF_RSVMAP_ENTRY;
+ cxt->p += SIZE_OF_RSVMAP_ENTRY;
+ cxt->p_end += SIZE_OF_RSVMAP_ENTRY;
}
-void ft_begin_tree(struct ft_cxt *cxt)
+void ft_end_tree(struct ft_cxt *cxt)
{
- cxt->p_begin = cxt->p_anchor;
- cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */
-
- cxt->p = cxt->p_begin;
- cxt->pstr = cxt->pstr_begin;
+ ft_put_word(cxt, OF_DT_END);
}
-int ft_end_tree(struct ft_cxt *cxt)
-{
+/* update the boot param header with correct values */
+void ft_finalize_tree(struct ft_cxt *cxt) {
struct boot_param_header *bph = cxt->bph;
- int off, sz, sz1;
- u32 tag, v;
- u8 *p;
-
- ft_put_word(cxt, OF_DT_END);
-
- if (cxt->overflow)
- return -ENOMEM;
-
- /* size of the areas */
- cxt->struct_size = cxt->p - cxt->p_begin;
- cxt->strings_size = cxt->pstr_begin - cxt->pstr;
-
- /* the offset we must move */
- off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size;
-
- /* the new strings start */
- cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
-
- /* move the whole string area */
- memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size);
- /* now perform the fixup of the strings */
- p = cxt->p_begin;
- while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) {
- p += 4;
-
- if (tag == OF_DT_BEGIN_NODE) {
- p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4);
- continue;
- }
-
- if (tag == OF_DT_END_NODE || tag == OF_DT_NOP)
- continue;
-
- if (tag != OF_DT_PROP)
- return -EINVAL;
-
- sz = be32_to_cpu(*(u32 *) p);
- p += 4;
-
- v = be32_to_cpu(*(u32 *) p);
- v -= off;
- *(u32 *) p = cpu_to_be32(v); /* move down */
- p += 4;
-
- p = (u8 *) _ALIGN((unsigned long)p + sz, 4);
- }
-
- /* fix sizes */
- p = (char *)cxt->bph;
- sz = (cxt->pstr_begin + cxt->strings_size) - p;
- sz1 = _ALIGN(sz, 16); /* align at 16 bytes */
- if (sz != sz1)
- memset(p + sz, 0, sz1 - sz);
- bph->totalsize = cpu_to_be32(sz1);
- bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p);
- bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p);
-
- /* the new strings start */
- cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
- cxt->pstr = cxt->pstr_begin + cxt->strings_size;
-
- return 0;
+ bph->totalsize = cxt->p_end - (u8 *)bph;
+ bph->off_dt_struct = cxt->p_start - (u8 *)bph;
+ bph->off_dt_strings = cxt->p - (u8 *)bph;
+ bph->dt_strings_size = cxt->p_end - cxt->p;
}
-/**********************************************************************/
-
static inline int isprint(int c)
{
return c >= 0x20 && c <= 0x7e;
switch (len) {
case 1: /* byte */
- printf(" = <0x%02x>", (*(u8 *) data) & 0xff);
+ printf(" = <%02x>", (*(u8 *) data) & 0xff);
break;
case 2: /* half-word */
- printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
+ printf(" = <%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
break;
case 4: /* word */
- printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
+ printf(" = <%x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
break;
case 8: /* double-word */
- printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data));
+ printf(" = <%qx>", be64_to_cpu(*(uint64_t *) data));
break;
default: /* anything else... hexdump */
printf(" = [");
if (addr == 0 && size == 0)
break;
- printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size);
+ printf("/memreserve/ %qx %qx;\n", addr, size);
}
p = p_struct;
}
if (tag != OF_DT_PROP) {
- fprintf(stderr, "%*s ** Unknown tag 0x%08x\n",
- depth * shift, "", tag);
+ fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n",
+ depth * shift, "", tag, --p);
break;
}
sz = be32_to_cpu(*p++);
void ft_backtrack_node(struct ft_cxt *cxt)
{
- if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
- return; /* XXX only for node */
-
- cxt->p -= 4;
-}
-
-/* note that the root node of the blob is "peeled" off */
-void ft_merge_blob(struct ft_cxt *cxt, void *blob)
-{
- struct boot_param_header *bph = (struct boot_param_header *)blob;
- u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
- u32 *p_strings =
- (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
- u32 tag, *p;
- char *s, *t;
- int depth, sz;
-
- if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
- return; /* XXX only for node */
-
- cxt->p -= 4;
-
- depth = 0;
- p = p_struct;
- while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
-
- /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */
-
- if (tag == OF_DT_BEGIN_NODE) {
- s = (char *)p;
- p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
-
- if (depth++ > 0)
- ft_begin_node(cxt, s);
-
- continue;
- }
-
- if (tag == OF_DT_END_NODE) {
- ft_end_node(cxt);
- if (--depth == 0)
- break;
- continue;
- }
-
- if (tag == OF_DT_NOP)
- continue;
+ int i = 4;
- if (tag != OF_DT_PROP)
- break;
+ while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE)
+ i += 4;
- sz = be32_to_cpu(*p++);
- s = (char *)p_strings + be32_to_cpu(*p++);
- t = (char *)p;
- p = (u32 *) _ALIGN((unsigned long)p + sz, 4);
+ memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p);
- ft_prop(cxt, s, t, sz);
- }
+ cxt->p_end -= i;
+ cxt->p -= i;
}
void *ft_get_prop(void *bphp, const char *propname, int *szp)
/********************************************************************/
-extern unsigned char oftree_dtb[];
-extern unsigned int oftree_dtb_len;
-
/* Function that returns a character from the environment */
extern uchar(*env_get_char) (int);
};
#endif
-void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end)
+void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end)
{
u32 *p;
int len;
return;
}
- ft_begin(&cxt, blob, size);
+#ifdef DEBUG
+ printf ("recieved oftree\n");
+ ft_dump_blob(blob);
+#endif
+
+ ft_init_cxt(&cxt, blob);
if (initrd_start && initrd_end)
ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1);
- ft_begin_tree(&cxt);
-
- ft_begin_node(&cxt, "");
-
- ft_end_node(&cxt);
-
- /* copy RO tree */
- ft_merge_blob(&cxt, oftree_dtb);
-
/* back into root */
ft_backtrack_node(&cxt);
#endif
ft_begin_node(&cxt, "chosen");
-
ft_prop_str(&cxt, "name", "chosen");
+
ft_prop_str(&cxt, "bootargs", getenv("bootargs"));
ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */
if (initrd_start && initrd_end) {
ft_end_node(&cxt); /* end root */
ft_end_tree(&cxt);
-
- /*
- printf("merged OF-tree\n");
- ft_dump_blob(blob);
- */
+ ft_finalize_tree(&cxt);
#ifdef CONFIG_OF_HAS_BD_T
/* paste the bd_t at the end of the flat tree */
ft_board_setup(blob, bd);
#endif
- /*
- printf("final OF-tree\n");
- ft_dump_blob(blob);
- */
+ /* in case the size changed in the platform code */
+ ft_finalize_tree(&cxt);
+#ifdef DEBUG
+ printf("final OF-tree\n");
+ ft_dump_blob(blob);
+#endif
}
-
#endif
*/
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
+#if !defined(CONFIG_MCC200)
ushort *cmap;
+#endif
ushort i, j;
uchar *fb;
bmp_image_t *bmp=(bmp_image_t *)bmp_image;
debug ("Display-bmp: %d x %d with %d colors\n",
(int)width, (int)height, (int)colors);
+#if !defined(CONFIG_MCC200)
+ /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
if (bpix==8) {
#if defined(CONFIG_PXA250)
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
-#elif defined(CONFIG_MCC200)
- /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
#else
# error "Don't know location of color map"
#endif
#endif
}
}
+#endif
/*
* BMP format for Monochrome assumes that the state of a
static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
int j; /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
{
short rdreg; /* register working value */
int j; /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
unsigned char reg, unsigned short value)
{
int j; /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
const unsigned char max_vendor_len = 40;
const unsigned char max_product_len = 20;
if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) {
- strncpy(vendor, "SMSC", max_vendor_len);
- strncpy(product, "Flash Media Cntrller", max_product_len);
+ strncpy ((char *)vendor, "SMSC", max_vendor_len);
+ strncpy ((char *)product, "Flash Media Cntrller", max_product_len);
}
}
#endif /* CONFIG_USB_BIN_FIXUP */
endif
endif
-AFLAGS_DEBUG := -Wa,-gstabs
+AFLAGS_DEBUG := -Wa,-g
# turn jbsr into jsr for m68k
ifeq ($(ARCH),m68k)
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(CPU).a
+
+START := start.o
+SOBJS := entry.o
+COBJS := cpu.o hsdramc.o exception.o cache.o
+COBJS += interrupts.o device.o pm.o pio.o
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(SOC).a
+
+COBJS := hebi.o devices.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "../sm.h"
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+const struct clock_domain chip_clock[] = {
+ [CLOCK_CPU] = {
+ .reg = SM_PM_CPU_MASK,
+ .id = CLOCK_CPU,
+ .bridge = NO_DEVICE,
+ },
+ [CLOCK_HSB] = {
+ .reg = SM_PM_HSB_MASK,
+ .id = CLOCK_HSB,
+ .bridge = NO_DEVICE,
+ },
+ [CLOCK_PBA] = {
+ .reg = SM_PM_PBA_MASK,
+ .id = CLOCK_PBA,
+ .bridge = DEVICE_PBA_BRIDGE,
+ },
+ [CLOCK_PBB] = {
+ .reg = SM_PM_PBB_MASK,
+ .id = CLOCK_PBB,
+ .bridge = DEVICE_PBB_BRIDGE,
+ },
+};
+
+static const struct resource hebi_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 0 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 13 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 14 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 },
+ },
+ },
+};
+static const struct resource pba_bridge_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 1 },
+ }
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ /* HSB-HSB Bridge */
+ .clock = { CLOCK_HSB, 4 },
+ },
+ },
+};
+static const struct resource pbb_bridge_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 2 },
+ },
+ },
+};
+static const struct resource hramc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 3 },
+ },
+ },
+};
+static const struct resource pioa_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 10 },
+ },
+ },
+};
+static const struct resource piob_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 11 },
+ },
+ },
+};
+static const struct resource pioc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 12 },
+ },
+ },
+};
+static const struct resource piod_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 13 },
+ },
+ },
+};
+static const struct resource pioe_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 14 },
+ },
+ },
+};
+static const struct resource sm_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 0 },
+ },
+ },
+};
+static const struct resource intc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 1 },
+ },
+ },
+};
+static const struct resource hmatrix_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 2 },
+ },
+ },
+};
+#if defined(CFG_HPDC)
+static const struct resource hpdc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 16 },
+ },
+ },
+};
+#endif
+#if defined(CFG_MACB0)
+static const struct resource macb0_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 8 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 6 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 },
+ },
+ },
+};
+#endif
+#if defined(CFG_MACB1)
+static const struct resource macb1_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 9 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 7 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 },
+ },
+ },
+};
+#endif
+#if defined(CFG_LCDC)
+static const struct resource lcdc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 7 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART0)
+static const struct resource usart0_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 3 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART1)
+static const struct resource usart1_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 4 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART2)
+static const struct resource usart2_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 5 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART3)
+static const struct resource usart3_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 6 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 },
+ },
+ },
+};
+#endif
+#if defined(CFG_MMCI)
+static const struct resource mmci_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 9 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 },
+ },
+ },
+};
+#endif
+#if defined(CFG_DMAC)
+static const struct resource dmac_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 10 },
+ },
+ },
+};
+#endif
+
+const struct device chip_device[] = {
+ [DEVICE_HEBI] = {
+ .regs = (void *)HSMC_BASE,
+ .nr_resources = ARRAY_SIZE(hebi_resource),
+ .resource = hebi_resource,
+ },
+ [DEVICE_PBA_BRIDGE] = {
+ .nr_resources = ARRAY_SIZE(pba_bridge_resource),
+ .resource = pba_bridge_resource,
+ },
+ [DEVICE_PBB_BRIDGE] = {
+ .nr_resources = ARRAY_SIZE(pbb_bridge_resource),
+ .resource = pbb_bridge_resource,
+ },
+ [DEVICE_HRAMC] = {
+ .nr_resources = ARRAY_SIZE(hramc_resource),
+ .resource = hramc_resource,
+ },
+ [DEVICE_PIOA] = {
+ .regs = (void *)PIOA_BASE,
+ .nr_resources = ARRAY_SIZE(pioa_resource),
+ .resource = pioa_resource,
+ },
+ [DEVICE_PIOB] = {
+ .regs = (void *)PIOB_BASE,
+ .nr_resources = ARRAY_SIZE(piob_resource),
+ .resource = piob_resource,
+ },
+ [DEVICE_PIOC] = {
+ .regs = (void *)PIOC_BASE,
+ .nr_resources = ARRAY_SIZE(pioc_resource),
+ .resource = pioc_resource,
+ },
+ [DEVICE_PIOD] = {
+ .regs = (void *)PIOD_BASE,
+ .nr_resources = ARRAY_SIZE(piod_resource),
+ .resource = piod_resource,
+ },
+ [DEVICE_PIOE] = {
+ .regs = (void *)PIOE_BASE,
+ .nr_resources = ARRAY_SIZE(pioe_resource),
+ .resource = pioe_resource,
+ },
+ [DEVICE_SM] = {
+ .regs = (void *)SM_BASE,
+ .nr_resources = ARRAY_SIZE(sm_resource),
+ .resource = sm_resource,
+ },
+ [DEVICE_INTC] = {
+ .regs = (void *)INTC_BASE,
+ .nr_resources = ARRAY_SIZE(intc_resource),
+ .resource = intc_resource,
+ },
+ [DEVICE_HMATRIX] = {
+ .regs = (void *)HMATRIX_BASE,
+ .nr_resources = ARRAY_SIZE(hmatrix_resource),
+ .resource = hmatrix_resource,
+ },
+#if defined(CFG_HPDC)
+ [DEVICE_HPDC] = {
+ .nr_resources = ARRAY_SIZE(hpdc_resource),
+ .resource = hpdc_resource,
+ },
+#endif
+#if defined(CFG_MACB0)
+ [DEVICE_MACB0] = {
+ .regs = (void *)MACB0_BASE,
+ .nr_resources = ARRAY_SIZE(macb0_resource),
+ .resource = macb0_resource,
+ },
+#endif
+#if defined(CFG_MACB1)
+ [DEVICE_MACB1] = {
+ .regs = (void *)MACB1_BASE,
+ .nr_resources = ARRAY_SIZE(macb1_resource),
+ .resource = macb1_resource,
+ },
+#endif
+#if defined(CFG_LCDC)
+ [DEVICE_LCDC] = {
+ .nr_resources = ARRAY_SIZE(lcdc_resource),
+ .resource = lcdc_resource,
+ },
+#endif
+#if defined(CFG_USART0)
+ [DEVICE_USART0] = {
+ .regs = (void *)USART0_BASE,
+ .nr_resources = ARRAY_SIZE(usart0_resource),
+ .resource = usart0_resource,
+ },
+#endif
+#if defined(CFG_USART1)
+ [DEVICE_USART1] = {
+ .regs = (void *)USART1_BASE,
+ .nr_resources = ARRAY_SIZE(usart1_resource),
+ .resource = usart1_resource,
+ },
+#endif
+#if defined(CFG_USART2)
+ [DEVICE_USART2] = {
+ .regs = (void *)USART2_BASE,
+ .nr_resources = ARRAY_SIZE(usart2_resource),
+ .resource = usart2_resource,
+ },
+#endif
+#if defined(CFG_USART3)
+ [DEVICE_USART3] = {
+ .regs = (void *)USART3_BASE,
+ .nr_resources = ARRAY_SIZE(usart3_resource),
+ .resource = usart3_resource,
+ },
+#endif
+#if defined(CFG_MMCI)
+ [DEVICE_MMCI] = {
+ .regs = (void *)MMCI_BASE,
+ .nr_resources = ARRAY_SIZE(mmci_resource),
+ .resource = mmci_resource,
+ },
+#endif
+#if defined(CFG_DMAC)
+ [DEVICE_DMAC] = {
+ .regs = (void *)DMAC_BASE,
+ .nr_resources = ARRAY_SIZE(dmac_resource),
+ .resource = dmac_resource,
+ },
+#endif
+};
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/hmatrix2.h>
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+void cpu_enable_sdram(void)
+{
+ const struct device *hmatrix;
+
+ hmatrix = get_device(DEVICE_HMATRIX);
+
+ /* Set the SDRAM_ENABLE bit in the HEBI SFR */
+ hmatrix2_writel(hmatrix, SFR4, 1 << 1);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/cacheflush.h>
+
+void dcache_clean_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_DCACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ dcache_clean_line((void *)v);
+
+ sync_write_buffer();
+}
+
+void dcache_invalidate_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_DCACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ dcache_invalidate_line((void *)v);
+}
+
+void dcache_flush_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_DCACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ dcache_flush_line((void *)v);
+
+ sync_write_buffer();
+}
+
+void icache_invalidate_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_ICACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ icache_invalidate_line((void *)v);
+}
+
+/*
+ * This is called after loading something into memory. We need to
+ * make sure that everything that was loaded is actually written to
+ * RAM, and that the icache will look for it. Cleaning the dcache and
+ * invalidating the icache will do the trick.
+ */
+void flush_cache (unsigned long start_addr, unsigned long size)
+{
+ dcache_clean_range((void *)start_addr, size);
+ icache_invalidate_range((void *)start_addr, size);
+}
--- /dev/null
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -mcpu=ap7000
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+
+#include <asm/io.h>
+#include <asm/sections.h>
+#include <asm/sysreg.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "hsmc3.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cpu_init(void)
+{
+ const struct device *hebi;
+ extern void _evba(void);
+ char *p;
+
+ gd->cpu_hz = CFG_OSC0_HZ;
+
+ /* fff03400: 00010001 04030402 00050005 10011103 */
+ hebi = get_device(DEVICE_HEBI);
+ hsmc3_writel(hebi, MODE0, 0x00031103);
+ hsmc3_writel(hebi, CYCLE0, 0x000c000d);
+ hsmc3_writel(hebi, PULSE0, 0x0b0a0906);
+ hsmc3_writel(hebi, SETUP0, 0x00010002);
+
+ pm_init();
+
+ sysreg_write(EVBA, (unsigned long)&_evba);
+ asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
+ gd->console_uart = get_device(CFG_CONSOLE_UART_DEV);
+
+ /* Lock everything that mess with the flash in the icache */
+ for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
+ p += CFG_ICACHE_LINESZ)
+ asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
+
+ return 0;
+}
+
+void prepare_to_boot(void)
+{
+ /* Flush both caches and the write buffer */
+ asm volatile("cache %0[4], 010\n\t"
+ "cache %0[0], 000\n\t"
+ "sync 0" : : "r"(0) : "memory");
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ /* This will reset the CPU core, caches, MMU and all internal busses */
+ __builtin_mtdr(8, 1 << 13); /* set DC:DBE */
+ __builtin_mtdr(8, 1 << 30); /* set DC:RES */
+
+ /* Flush the pipeline before we declare it a failure */
+ asm volatile("sub pc, pc, -4");
+
+ return -1;
+}
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/platform.h>
+
+#include "sm.h"
+
+struct device_state {
+ int refcount;
+};
+
+static struct device_state device_state[NR_DEVICES];
+
+static int claim_resource(const struct resource *res)
+{
+ int ret = 0;
+
+ switch (res->type) {
+ case RESOURCE_GPIO:
+ ret = gpio_set_func(res->u.gpio.gpio_dev,
+ res->u.gpio.start,
+ res->u.gpio.nr_pins,
+ res->u.gpio.func);
+ break;
+ case RESOURCE_CLOCK:
+ ret = pm_enable_clock(res->u.clock.id, res->u.clock.index);
+ break;
+ }
+
+ return ret;
+}
+
+static void free_resource(const struct resource *res)
+{
+ switch (res->type) {
+ case RESOURCE_GPIO:
+ gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start,
+ res->u.gpio.nr_pins);
+ break;
+ case RESOURCE_CLOCK:
+ pm_disable_clock(res->u.clock.id, res->u.clock.index);
+ break;
+ }
+}
+
+static int init_dev(const struct device *dev)
+{
+ unsigned int i;
+ int ret = 0;
+
+ for (i = 0; i < dev->nr_resources; i++) {
+ ret = claim_resource(&dev->resource[i]);
+ if (ret)
+ goto cleanup;
+ }
+
+ return 0;
+
+cleanup:
+ while (i--)
+ free_resource(&dev->resource[i]);
+
+ return ret;
+}
+
+const struct device *get_device(enum device_id devid)
+{
+ struct device_state *devstate;
+ const struct device *dev;
+ unsigned long flags;
+ int initialized = 0;
+ int ret = 0;
+
+ devstate = &device_state[devid];
+ dev = &chip_device[devid];
+
+ flags = disable_interrupts();
+ if (devstate->refcount++)
+ initialized = 1;
+ if (flags)
+ enable_interrupts();
+
+ if (!initialized)
+ ret = init_dev(dev);
+
+ return ret ? NULL : dev;
+}
+
+void put_device(const struct device *dev)
+{
+ struct device_state *devstate;
+ unsigned long devid, flags;
+
+ devid = (unsigned long)(dev - chip_device) / sizeof(struct device);
+ devstate = &device_state[devid];
+
+ flags = disable_interrupts();
+ devstate--;
+ if (!devstate) {
+ unsigned int i;
+ for (i = 0; i < dev->nr_resources; i++)
+ free_resource(&dev->resource[i]);
+ }
+ if (flags)
+ enable_interrupts();
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/sysreg.h>
+#include <asm/ptrace.h>
+
+ .section .text.exception,"ax"
+ .global _evba
+ .type _evba,@function
+ .align 10
+_evba:
+ .irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
+ .align 2
+ rjmp unknown_exception
+ .endr
+
+ .global timer_interrupt_handler
+ .type timer_interrupt_handler,@function
+ .align 2
+timer_interrupt_handler:
+ /*
+ * Increment timer_overflow and re-write COMPARE with 0xffffffff.
+ *
+ * We're running at interrupt level 3, so we don't need to save
+ * r8-r12 or lr to the stack.
+ */
+ mov r8, lo(timer_overflow)
+ orh r8, hi(timer_overflow)
+ ld.w r9, r8[0]
+ mov r10, -1
+ mtsr SYSREG_COMPARE, r10
+ sub r9, -1
+ st.w r8[0], r9
+ rete
+
+ .type unknown_exception, @function
+unknown_exception:
+ pushm r0-r12
+ sub r8, sp, REG_R12 - REG_R0 - 4
+ mov r9, lr
+ mfsr r10, SYSREG_RAR_EX
+ mfsr r11, SYSREG_RSR_EX
+ pushm r8-r11
+ mfsr r12, SYSREG_ECR
+ mov r11, sp
+ rcall do_unknown_exception
+1: rjmp 1b
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+#include <asm/ptrace.h>
+
+static const char * const cpu_modes[8] = {
+ "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
+ "Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
+};
+
+static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
+{
+ unsigned long p;
+ int i;
+
+ printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
+
+ for (p = bottom & ~31; p < top; ) {
+ printf("%04lx: ", p & 0xffff);
+
+ for (i = 0; i < 8; i++, p += 4) {
+ unsigned int val;
+
+ if (p < bottom || p >= top)
+ printf(" ");
+ else {
+ val = *(unsigned long *)p;
+ printf("%08x ", val);
+ }
+ }
+ printf("\n");
+ }
+}
+
+void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
+{
+ unsigned int mode;
+
+ printf("\n *** Unhandled exception %u at PC=0x%08lx\n", ecr, regs->pc);
+
+ switch (ecr) {
+ case ECR_BUS_ERROR_WRITE:
+ case ECR_BUS_ERROR_READ:
+ printf("Bus error at address 0x%08lx\n",
+ sysreg_read(BEAR));
+ break;
+ case ECR_TLB_MULTIPLE:
+ case ECR_ADDR_ALIGN_X:
+ case ECR_PROTECTION_X:
+ case ECR_ADDR_ALIGN_R:
+ case ECR_ADDR_ALIGN_W:
+ case ECR_PROTECTION_R:
+ case ECR_PROTECTION_W:
+ case ECR_DTLB_MODIFIED:
+ case ECR_TLB_MISS_X:
+ case ECR_TLB_MISS_R:
+ case ECR_TLB_MISS_W:
+ printf("MMU exception at address 0x%08lx\n",
+ sysreg_read(TLBEAR));
+ break;
+ }
+
+ printf(" pc: %08lx lr: %08lx sp: %08lx r12: %08lx\n",
+ regs->pc, regs->lr, regs->sp, regs->r12);
+ printf(" r11: %08lx r10: %08lx r9: %08lx r8: %08lx\n",
+ regs->r11, regs->r10, regs->r9, regs->r8);
+ printf(" r7: %08lx r6: %08lx r5: %08lx r4: %08lx\n",
+ regs->r7, regs->r6, regs->r5, regs->r4);
+ printf(" r3: %08lx r2: %08lx r1: %08lx r0: %08lx\n",
+ regs->r3, regs->r2, regs->r1, regs->r0);
+ printf("Flags: %c%c%c%c%c\n",
+ regs->sr & SR_Q ? 'Q' : 'q',
+ regs->sr & SR_V ? 'V' : 'v',
+ regs->sr & SR_N ? 'N' : 'n',
+ regs->sr & SR_Z ? 'Z' : 'z',
+ regs->sr & SR_C ? 'C' : 'c');
+ printf("Mode bits: %c%c%c%c%c%c%c%c%c\n",
+ regs->sr & SR_H ? 'H' : 'h',
+ regs->sr & SR_R ? 'R' : 'r',
+ regs->sr & SR_J ? 'J' : 'j',
+ regs->sr & SR_EM ? 'E' : 'e',
+ regs->sr & SR_I3M ? '3' : '.',
+ regs->sr & SR_I2M ? '2' : '.',
+ regs->sr & SR_I1M ? '1' : '.',
+ regs->sr & SR_I0M ? '0' : '.',
+ regs->sr & SR_GM ? 'G' : 'g');
+ mode = (regs->sr >> SYSREG_M0_OFFSET) & 7;
+ printf("CPU Mode: %s\n", cpu_modes[mode]);
+
+ /* Avoid exception loops */
+ if (regs->sp >= CFG_INIT_SP_ADDR
+ || regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE))
+ printf("\nStack pointer seems bogus, won't do stack dump\n");
+ else
+ dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR);
+
+ panic("Unhandled exception\n");
+}
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CFG_HSDRAMC
+#include <asm/io.h>
+#include <asm/sdram.h>
+
+#include <asm/arch/platform.h>
+
+#include "hsdramc1.h"
+
+struct hsdramc {
+ const struct device *hebi;
+ void *regs;
+};
+
+static struct hsdramc hsdramc;
+
+unsigned long sdram_init(const struct sdram_info *info)
+{
+ unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
+ unsigned long sdram_size;
+ unsigned long tmp;
+ unsigned long bus_hz;
+ unsigned int i;
+
+ hsdramc.hebi = get_device(DEVICE_HEBI);
+ if (!hsdramc.hebi)
+ return 0;
+
+ /* FIXME: Both of these lines are complete hacks */
+ hsdramc.regs = hsdramc.hebi->regs + 0x400;
+ bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id);
+
+ cpu_enable_sdram();
+
+ tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
+ | HSDRAMC1_BF(NR, info->row_bits - 11)
+ | HSDRAMC1_BF(NB, info->bank_bits - 1)
+ | HSDRAMC1_BF(CAS, info->cas)
+ | HSDRAMC1_BF(TWR, info->twr)
+ | HSDRAMC1_BF(TRC, info->trc)
+ | HSDRAMC1_BF(TRP, info->trp)
+ | HSDRAMC1_BF(TRCD, info->trcd)
+ | HSDRAMC1_BF(TRAS, info->tras)
+ | HSDRAMC1_BF(TXSR, info->txsr));
+
+#ifdef CFG_SDRAM_16BIT
+ tmp |= HSDRAMC1_BIT(DBW);
+ sdram_size = 1 << (info->row_bits + info->col_bits
+ + info->bank_bits + 1);
+#else
+ sdram_size = 1 << (info->row_bits + info->col_bits
+ + info->bank_bits + 2);
+#endif
+
+ hsdramc1_writel(&hsdramc, CR, tmp);
+
+ /*
+ * Initialization sequence for SDRAM, from the data sheet:
+ *
+ * 1. A minimum pause of 200 us is provided to precede any
+ * signal toggle.
+ */
+ udelay(200);
+
+ /*
+ * 2. A Precharge All command is issued to the SDRAM
+ */
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
+ hsdramc1_readl(&hsdramc, MR);
+ writel(0, sdram);
+
+ /*
+ * 3. Eight auto-refresh (CBR) cycles are provided
+ */
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH);
+ hsdramc1_readl(&hsdramc, MR);
+ for (i = 0; i < 8; i++)
+ writel(0, sdram);
+
+ /*
+ * 4. A mode register set (MRS) cycle is issued to program
+ * SDRAM parameters, in particular CAS latency and burst
+ * length.
+ *
+ * CAS from info struct, burst length 1, serial burst type
+ */
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE);
+ hsdramc1_readl(&hsdramc, MR);
+ writel(0, sdram + (info->cas << 4));
+
+ /*
+ * 5. A Normal Mode command is provided, 3 clocks after tMRD
+ * is met.
+ *
+ * From the timing diagram, it looks like tMRD is 3
+ * cycles...try a dummy read from the peripheral bus.
+ */
+ hsdramc1_readl(&hsdramc, MR);
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL);
+ hsdramc1_readl(&hsdramc, MR);
+ writel(0, sdram);
+
+ /*
+ * 6. Write refresh rate into SDRAMC refresh timer count
+ * register (refresh rate = timing between refresh cycles).
+ *
+ * 15.6 us is a typical value for a burst of length one
+ */
+ hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000);
+
+ printf("SDRAM: %u MB at address 0x%08lx\n",
+ sdram_size >> 20, info->phys_addr);
+
+ printf("Testing SDRAM...");
+ for (i = 0; i < sdram_size / 4; i++)
+ sdram[i] = i;
+
+ for (i = 0; i < sdram_size / 4; i++) {
+ tmp = sdram[i];
+ if (tmp != i) {
+ printf("FAILED at address 0x%08lx\n",
+ info->phys_addr + i * 4);
+ printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
+ return 0;
+ }
+ }
+
+ puts("OK\n");
+
+ return sdram_size;
+}
+
+#endif /* CFG_HSDRAMC */
--- /dev/null
+/*
+ * Register definitions for SDRAM Controller
+ */
+#ifndef __ASM_AVR32_HSDRAMC1_H__
+#define __ASM_AVR32_HSDRAMC1_H__
+
+/* HSDRAMC1 register offsets */
+#define HSDRAMC1_MR 0x0000
+#define HSDRAMC1_TR 0x0004
+#define HSDRAMC1_CR 0x0008
+#define HSDRAMC1_HSR 0x000c
+#define HSDRAMC1_LPR 0x0010
+#define HSDRAMC1_IER 0x0014
+#define HSDRAMC1_IDR 0x0018
+#define HSDRAMC1_IMR 0x001c
+#define HSDRAMC1_ISR 0x0020
+#define HSDRAMC1_MDR 0x0024
+#define HSDRAMC1_VERSION 0x00fc
+
+/* Bitfields in MR */
+#define HSDRAMC1_MODE_OFFSET 0
+#define HSDRAMC1_MODE_SIZE 3
+
+/* Bitfields in TR */
+#define HSDRAMC1_COUNT_OFFSET 0
+#define HSDRAMC1_COUNT_SIZE 12
+
+/* Bitfields in CR */
+#define HSDRAMC1_NC_OFFSET 0
+#define HSDRAMC1_NC_SIZE 2
+#define HSDRAMC1_NR_OFFSET 2
+#define HSDRAMC1_NR_SIZE 2
+#define HSDRAMC1_NB_OFFSET 4
+#define HSDRAMC1_NB_SIZE 1
+#define HSDRAMC1_CAS_OFFSET 5
+#define HSDRAMC1_CAS_SIZE 2
+#define HSDRAMC1_DBW_OFFSET 7
+#define HSDRAMC1_DBW_SIZE 1
+#define HSDRAMC1_TWR_OFFSET 8
+#define HSDRAMC1_TWR_SIZE 4
+#define HSDRAMC1_TRC_OFFSET 12
+#define HSDRAMC1_TRC_SIZE 4
+#define HSDRAMC1_TRP_OFFSET 16
+#define HSDRAMC1_TRP_SIZE 4
+#define HSDRAMC1_TRCD_OFFSET 20
+#define HSDRAMC1_TRCD_SIZE 4
+#define HSDRAMC1_TRAS_OFFSET 24
+#define HSDRAMC1_TRAS_SIZE 4
+#define HSDRAMC1_TXSR_OFFSET 28
+#define HSDRAMC1_TXSR_SIZE 4
+
+/* Bitfields in HSR */
+#define HSDRAMC1_DA_OFFSET 0
+#define HSDRAMC1_DA_SIZE 1
+
+/* Bitfields in LPR */
+#define HSDRAMC1_LPCB_OFFSET 0
+#define HSDRAMC1_LPCB_SIZE 2
+#define HSDRAMC1_PASR_OFFSET 4
+#define HSDRAMC1_PASR_SIZE 3
+#define HSDRAMC1_TCSR_OFFSET 8
+#define HSDRAMC1_TCSR_SIZE 2
+#define HSDRAMC1_DS_OFFSET 10
+#define HSDRAMC1_DS_SIZE 2
+#define HSDRAMC1_TIMEOUT_OFFSET 12
+#define HSDRAMC1_TIMEOUT_SIZE 2
+
+/* Bitfields in IDR */
+#define HSDRAMC1_RES_OFFSET 0
+#define HSDRAMC1_RES_SIZE 1
+
+/* Bitfields in MDR */
+#define HSDRAMC1_MD_OFFSET 0
+#define HSDRAMC1_MD_SIZE 2
+
+/* Bitfields in VERSION */
+#define HSDRAMC1_VERSION_OFFSET 0
+#define HSDRAMC1_VERSION_SIZE 12
+#define HSDRAMC1_MFN_OFFSET 16
+#define HSDRAMC1_MFN_SIZE 3
+
+/* Constants for MODE */
+#define HSDRAMC1_MODE_NORMAL 0
+#define HSDRAMC1_MODE_NOP 1
+#define HSDRAMC1_MODE_BANKS_PRECHARGE 2
+#define HSDRAMC1_MODE_LOAD_MODE 3
+#define HSDRAMC1_MODE_AUTO_REFRESH 4
+#define HSDRAMC1_MODE_EXT_LOAD_MODE 5
+#define HSDRAMC1_MODE_POWER_DOWN 6
+
+/* Constants for NC */
+#define HSDRAMC1_NC_8_COLUMN_BITS 0
+#define HSDRAMC1_NC_9_COLUMN_BITS 1
+#define HSDRAMC1_NC_10_COLUMN_BITS 2
+#define HSDRAMC1_NC_11_COLUMN_BITS 3
+
+/* Constants for NR */
+#define HSDRAMC1_NR_11_ROW_BITS 0
+#define HSDRAMC1_NR_12_ROW_BITS 1
+#define HSDRAMC1_NR_13_ROW_BITS 2
+
+/* Constants for NB */
+#define HSDRAMC1_NB_TWO_BANKS 0
+#define HSDRAMC1_NB_FOUR_BANKS 1
+
+/* Constants for CAS */
+#define HSDRAMC1_CAS_ONE_CYCLE 1
+#define HSDRAMC1_CAS_TWO_CYCLES 2
+
+/* Constants for DBW */
+#define HSDRAMC1_DBW_32_BITS 0
+#define HSDRAMC1_DBW_16_BITS 1
+
+/* Constants for TIMEOUT */
+#define HSDRAMC1_TIMEOUT_AFTER_END 0
+#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1
+#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2
+
+/* Constants for MD */
+#define HSDRAMC1_MD_SDRAM 0
+#define HSDRAMC1_MD_LOW_POWER_SDRAM 1
+
+/* Bit manipulation macros */
+#define HSDRAMC1_BIT(name) \
+ (1 << HSDRAMC1_##name##_OFFSET)
+#define HSDRAMC1_BF(name,value) \
+ (((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) \
+ << HSDRAMC1_##name##_OFFSET)
+#define HSDRAMC1_BFEXT(name,value) \
+ (((value) >> HSDRAMC1_##name##_OFFSET) \
+ & ((1 << HSDRAMC1_##name##_SIZE) - 1))
+#define HSDRAMC1_BFINS(name,value,old) \
+ (((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) \
+ << HSDRAMC1_##name##_OFFSET)) \
+ | HSDRAMC1_BF(name,value))
+
+/* Register access macros */
+#define hsdramc1_readl(port,reg) \
+ readl((port)->regs + HSDRAMC1_##reg)
+#define hsdramc1_writel(port,reg,value) \
+ writel((value), (port)->regs + HSDRAMC1_##reg)
+
+#endif /* __ASM_AVR32_HSDRAMC1_H__ */
--- /dev/null
+/*
+ * Register definitions for Static Memory Controller
+ */
+#ifndef __CPU_AT32AP_HSMC3_H__
+#define __CPU_AT32AP_HSMC3_H__
+
+/* HSMC3 register offsets */
+#define HSMC3_SETUP0 0x0000
+#define HSMC3_PULSE0 0x0004
+#define HSMC3_CYCLE0 0x0008
+#define HSMC3_MODE0 0x000c
+#define HSMC3_SETUP1 0x0010
+#define HSMC3_PULSE1 0x0014
+#define HSMC3_CYCLE1 0x0018
+#define HSMC3_MODE1 0x001c
+#define HSMC3_SETUP2 0x0020
+#define HSMC3_PULSE2 0x0024
+#define HSMC3_CYCLE2 0x0028
+#define HSMC3_MODE2 0x002c
+#define HSMC3_SETUP3 0x0030
+#define HSMC3_PULSE3 0x0034
+#define HSMC3_CYCLE3 0x0038
+#define HSMC3_MODE3 0x003c
+#define HSMC3_SETUP4 0x0040
+#define HSMC3_PULSE4 0x0044
+#define HSMC3_CYCLE4 0x0048
+#define HSMC3_MODE4 0x004c
+#define HSMC3_SETUP5 0x0050
+#define HSMC3_PULSE5 0x0054
+#define HSMC3_CYCLE5 0x0058
+#define HSMC3_MODE5 0x005c
+
+/* Bitfields in SETUP0 */
+#define HSMC3_NWE_SETUP_OFFSET 0
+#define HSMC3_NWE_SETUP_SIZE 6
+#define HSMC3_NCS_WR_SETUP_OFFSET 8
+#define HSMC3_NCS_WR_SETUP_SIZE 6
+#define HSMC3_NRD_SETUP_OFFSET 16
+#define HSMC3_NRD_SETUP_SIZE 6
+#define HSMC3_NCS_RD_SETUP_OFFSET 24
+#define HSMC3_NCS_RD_SETUP_SIZE 6
+
+/* Bitfields in PULSE0 */
+#define HSMC3_NWE_PULSE_OFFSET 0
+#define HSMC3_NWE_PULSE_SIZE 7
+#define HSMC3_NCS_WR_PULSE_OFFSET 8
+#define HSMC3_NCS_WR_PULSE_SIZE 7
+#define HSMC3_NRD_PULSE_OFFSET 16
+#define HSMC3_NRD_PULSE_SIZE 7
+#define HSMC3_NCS_RD_PULSE_OFFSET 24
+#define HSMC3_NCS_RD_PULSE_SIZE 7
+
+/* Bitfields in CYCLE0 */
+#define HSMC3_NWE_CYCLE_OFFSET 0
+#define HSMC3_NWE_CYCLE_SIZE 9
+#define HSMC3_NRD_CYCLE_OFFSET 16
+#define HSMC3_NRD_CYCLE_SIZE 9
+
+/* Bitfields in MODE0 */
+#define HSMC3_READ_MODE_OFFSET 0
+#define HSMC3_READ_MODE_SIZE 1
+#define HSMC3_WRITE_MODE_OFFSET 1
+#define HSMC3_WRITE_MODE_SIZE 1
+#define HSMC3_EXNW_MODE_OFFSET 4
+#define HSMC3_EXNW_MODE_SIZE 2
+#define HSMC3_BAT_OFFSET 8
+#define HSMC3_BAT_SIZE 1
+#define HSMC3_DBW_OFFSET 12
+#define HSMC3_DBW_SIZE 2
+#define HSMC3_TDF_CYCLES_OFFSET 16
+#define HSMC3_TDF_CYCLES_SIZE 4
+#define HSMC3_TDF_MODE_OFFSET 20
+#define HSMC3_TDF_MODE_SIZE 1
+#define HSMC3_PMEN_OFFSET 24
+#define HSMC3_PMEN_SIZE 1
+#define HSMC3_PS_OFFSET 28
+#define HSMC3_PS_SIZE 2
+
+/* Bitfields in MODE1 */
+#define HSMC3_PD_OFFSET 28
+#define HSMC3_PD_SIZE 2
+
+/* Constants for READ_MODE */
+#define HSMC3_READ_MODE_NCS_CONTROLLED 0
+#define HSMC3_READ_MODE_NRD_CONTROLLED 1
+
+/* Constants for WRITE_MODE */
+#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0
+#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1
+
+/* Constants for EXNW_MODE */
+#define HSMC3_EXNW_MODE_DISABLED 0
+#define HSMC3_EXNW_MODE_RESERVED 1
+#define HSMC3_EXNW_MODE_FROZEN 2
+#define HSMC3_EXNW_MODE_READY 3
+
+/* Constants for BAT */
+#define HSMC3_BAT_BYTE_SELECT 0
+#define HSMC3_BAT_BYTE_WRITE 1
+
+/* Constants for DBW */
+#define HSMC3_DBW_8_BITS 0
+#define HSMC3_DBW_16_BITS 1
+#define HSMC3_DBW_32_BITS 2
+
+/* Bit manipulation macros */
+#define HSMC3_BIT(name) \
+ (1 << HSMC3_##name##_OFFSET)
+#define HSMC3_BF(name,value) \
+ (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \
+ << HSMC3_##name##_OFFSET)
+#define HSMC3_BFEXT(name,value) \
+ (((value) >> HSMC3_##name##_OFFSET) \
+ & ((1 << HSMC3_##name##_SIZE) - 1))
+#define HSMC3_BFINS(name,value,old)\
+ (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \
+ << HSMC3_##name##_OFFSET)) \
+ | HSMC3_BF(name,value))
+
+/* Register access macros */
+#define hsmc3_readl(port,reg) \
+ readl((port)->regs + HSMC3_##reg)
+#define hsmc3_writel(port,reg,value) \
+ writel((value), (port)->regs + HSMC3_##reg)
+
+#endif /* __CPU_AT32AP_HSMC3_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/div64.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/sysreg.h>
+
+#include <asm/arch/platform.h>
+
+#define HANDLER_MASK 0x00ffffff
+#define INTLEV_SHIFT 30
+#define INTLEV_MASK 0x00000003
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */
+volatile unsigned long timer_overflow;
+
+/*
+ * Instead of dividing by get_tbclk(), multiply by this constant and
+ * right-shift the result by 32 bits.
+ */
+static unsigned long tb_factor;
+
+static const struct device *intc_dev;
+
+unsigned long get_tbclk(void)
+{
+ return gd->cpu_hz;
+}
+
+unsigned long long get_ticks(void)
+{
+ unsigned long lo, hi_now, hi_prev;
+
+ do {
+ hi_prev = timer_overflow;
+ lo = sysreg_read(COUNT);
+ hi_now = timer_overflow;
+ } while (hi_prev != hi_now);
+
+ return ((unsigned long long)hi_now << 32) | lo;
+}
+
+void reset_timer(void)
+{
+ sysreg_write(COUNT, 0);
+ cpu_sync_pipeline(); /* process any pending interrupts */
+ timer_overflow = 0;
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ u64 now = get_ticks();
+
+ now *= tb_factor;
+ return (unsigned long)(now >> 32) - base;
+}
+
+void set_timer(unsigned long t)
+{
+ unsigned long long ticks = t;
+ unsigned long lo, hi, hi_new;
+
+ ticks = (ticks * get_tbclk()) / CFG_HZ;
+ hi = ticks >> 32;
+ lo = ticks & 0xffffffffUL;
+
+ do {
+ timer_overflow = hi;
+ sysreg_write(COUNT, lo);
+ hi_new = timer_overflow;
+ } while (hi_new != hi);
+}
+
+/*
+ * For short delays only. It will overflow after a few seconds.
+ */
+void udelay(unsigned long usec)
+{
+ unsigned long now, end;
+
+ now = sysreg_read(COUNT);
+
+ end = ((usec * (get_tbclk() / 10000)) + 50) / 100;
+ end += now;
+
+ while (now > end)
+ now = sysreg_read(COUNT);
+
+ while (now < end)
+ now = sysreg_read(COUNT);
+}
+
+static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
+ unsigned int priority)
+{
+ unsigned long intpr;
+ unsigned long handler_addr = (unsigned long)handler;
+
+ if ((handler_addr & HANDLER_MASK) != handler_addr
+ || (priority & INTLEV_MASK) != priority)
+ return -EINVAL;
+
+ intpr = (handler_addr & HANDLER_MASK);
+ intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
+ writel(intpr, intc_dev->regs + 4 * nr);
+
+ return 0;
+}
+
+void timer_init(void)
+{
+ extern void timer_interrupt_handler(void);
+ u64 tmp;
+
+ sysreg_write(COUNT, 0);
+
+ tmp = (u64)CFG_HZ << 32;
+ tmp += gd->cpu_hz / 2;
+ do_div(tmp, gd->cpu_hz);
+ tb_factor = (u32)tmp;
+
+ intc_dev = get_device(DEVICE_INTC);
+
+ if (!intc_dev
+ || set_interrupt_handler(0, &timer_interrupt_handler, 3))
+ return;
+
+ /* For all practical purposes, this gives us an overflow interrupt */
+ sysreg_write(COMPARE, 0xffffffff);
+}
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+#include "pio2.h"
+
+struct pio_state {
+ const struct device *dev;
+ u32 alloc_mask;
+};
+
+static struct pio_state pio_state[CFG_NR_PIOS];
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins, enum gpio_func func)
+{
+ const struct device *gpio;
+ struct pio_state *state;
+ u32 mask;
+
+ state = &pio_state[gpio_devid - DEVICE_PIOA];
+
+ gpio = get_device(gpio_devid);
+ if (!gpio)
+ return -EBUSY;
+
+ state->dev = gpio;
+ mask = ((1 << nr_pins) - 1) << start;
+
+ if (mask & state->alloc_mask) {
+ put_device(gpio);
+ return -EBUSY;
+ }
+ state->alloc_mask |= mask;
+
+ switch (func) {
+ case GPIO_FUNC_GPIO:
+ /* TODO */
+ return -EINVAL;
+ case GPIO_FUNC_A:
+ pio2_writel(gpio, ASR, mask);
+ pio2_writel(gpio, PDR, mask);
+ pio2_writel(gpio, PUDR, mask);
+ break;
+ case GPIO_FUNC_B:
+ pio2_writel(gpio, BSR, mask);
+ pio2_writel(gpio, PDR, mask);
+ pio2_writel(gpio, PUDR, mask);
+ break;
+ }
+
+ return 0;
+}
+
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins)
+{
+ const struct device *gpio;
+ struct pio_state *state;
+ u32 mask;
+
+ state = &pio_state[gpio_devid - DEVICE_PIOA];
+ gpio = state->dev;
+ mask = ((1 << nr_pins) - 1) << start;
+
+ pio2_writel(gpio, ODR, mask);
+ pio2_writel(gpio, PER, mask);
+
+ state->alloc_mask &= ~mask;
+ put_device(gpio);
+}
--- /dev/null
+/*
+ * Register definitions for Parallel Input/Output Controller
+ */
+#ifndef __CPU_AT32AP_PIO2_H__
+#define __CPU_AT32AP_PIO2_H__
+
+/* PIO2 register offsets */
+#define PIO2_PER 0x0000
+#define PIO2_PDR 0x0004
+#define PIO2_PSR 0x0008
+#define PIO2_OER 0x0010
+#define PIO2_ODR 0x0014
+#define PIO2_OSR 0x0018
+#define PIO2_IFER 0x0020
+#define PIO2_IFDR 0x0024
+#define PIO2_ISFR 0x0028
+#define PIO2_SODR 0x0030
+#define PIO2_CODR 0x0034
+#define PIO2_ODSR 0x0038
+#define PIO2_PDSR 0x003c
+#define PIO2_IER 0x0040
+#define PIO2_IDR 0x0044
+#define PIO2_IMR 0x0048
+#define PIO2_ISR 0x004c
+#define PIO2_MDER 0x0050
+#define PIO2_MDDR 0x0054
+#define PIO2_MDSR 0x0058
+#define PIO2_PUDR 0x0060
+#define PIO2_PUER 0x0064
+#define PIO2_PUSR 0x0068
+#define PIO2_ASR 0x0070
+#define PIO2_BSR 0x0074
+#define PIO2_ABSR 0x0078
+#define PIO2_OWER 0x00a0
+#define PIO2_OWDR 0x00a4
+#define PIO2_OWSR 0x00a8
+
+/* Register access macros */
+#define pio2_readl(port,reg) \
+ readl((port)->regs + PIO2_##reg)
+#define pio2_writel(port,reg,value) \
+ writel((value), (port)->regs + PIO2_##reg)
+
+#endif /* __CPU_AT32AP_PIO2_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CFG_POWER_MANAGER
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "sm.h"
+
+/* Sanity checks */
+#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
+ || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
+ || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
+# error Constraint fCPU >= fHSB >= fPB{A,B} violated
+#endif
+#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
+# error Invalid PLL multiplier and/or divider
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clock_domain_state {
+ const struct device *bridge;
+ unsigned long freq;
+ u32 mask;
+};
+static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS];
+
+int pm_enable_clock(enum clock_domain_id id, unsigned int index)
+{
+ const struct clock_domain *ckd = &chip_clock[id];
+ struct clock_domain_state *state = &ckd_state[id];
+
+ if (ckd->bridge != NO_DEVICE) {
+ state->bridge = get_device(ckd->bridge);
+ if (!state->bridge)
+ return -EBUSY;
+ }
+
+ state->mask |= 1 << index;
+ if (gd->sm)
+ writel(state->mask, gd->sm->regs + ckd->reg);
+
+ return 0;
+}
+
+void pm_disable_clock(enum clock_domain_id id, unsigned int index)
+{
+ const struct clock_domain *ckd = &chip_clock[id];
+ struct clock_domain_state *state = &ckd_state[id];
+
+ state->mask &= ~(1 << index);
+ if (gd->sm)
+ writel(state->mask, gd->sm->regs + ckd->reg);
+
+ if (ckd->bridge)
+ put_device(state->bridge);
+}
+
+unsigned long pm_get_clock_freq(enum clock_domain_id domain)
+{
+ return ckd_state[domain].freq;
+}
+
+void pm_init(void)
+{
+ uint32_t cksel = 0;
+ unsigned long main_clock;
+
+ /* Make sure we don't disable any device we're already using */
+ get_device(DEVICE_HRAMC);
+ get_device(DEVICE_HEBI);
+
+ /* Enable the PICO as well */
+ ckd_state[CLOCK_CPU].mask |= 1;
+
+ gd->sm = get_device(DEVICE_SM);
+ if (!gd->sm)
+ panic("Unable to claim system manager device!\n");
+
+ /* Disable any devices that haven't been explicitly claimed */
+ sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask);
+ sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask);
+ sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask);
+ sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask);
+
+#ifdef CONFIG_PLL
+ /* Initialize the PLL */
+ main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL;
+
+ sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
+ | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
+ | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
+ | SM_BF(PLLOPT, CFG_PLL0_OPT)
+ | SM_BF(PLLOSC, 0)
+ | SM_BIT(PLLEN)));
+
+ /* Wait for lock */
+ while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ;
+#else
+ main_clock = CFG_OSC0_HZ;
+#endif
+
+ /* Set up clocks for the CPU and all peripheral buses */
+ if (CFG_CLKDIV_CPU) {
+ cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
+ ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU);
+ } else {
+ ckd_state[CLOCK_CPU].freq = main_clock;
+ }
+ if (CFG_CLKDIV_HSB) {
+ cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
+ ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB);
+ } else {
+ ckd_state[CLOCK_HSB].freq = main_clock;
+ }
+ if (CFG_CLKDIV_PBA) {
+ cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
+ ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA);
+ } else {
+ ckd_state[CLOCK_PBA].freq = main_clock;
+ }
+ if (CFG_CLKDIV_PBB) {
+ cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+ ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB);
+ } else {
+ ckd_state[CLOCK_PBB].freq = main_clock;
+ }
+ sm_writel(gd->sm, PM_CKSEL, cksel);
+
+ /* CFG_HZ currently depends on cpu_hz */
+ gd->cpu_hz = ckd_state[CLOCK_CPU].freq;
+
+#ifdef CONFIG_PLL
+ /* Use PLL0 as main clock */
+ sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL));
+#endif
+}
+
+#endif /* CFG_POWER_MANAGER */
--- /dev/null
+/*
+ * Register definitions for System Manager
+ */
+#ifndef __CPU_AT32AP_SM_H__
+#define __CPU_AT32AP_SM_H__
+
+/* SM register offsets */
+#define SM_PM_MCCTRL 0x0000
+#define SM_PM_CKSEL 0x0004
+#define SM_PM_CPU_MASK 0x0008
+#define SM_PM_HSB_MASK 0x000c
+#define SM_PM_PBA_MASK 0x0010
+#define SM_PM_PBB_MASK 0x0014
+#define SM_PM_PLL0 0x0020
+#define SM_PM_PLL1 0x0024
+#define SM_PM_VCTRL 0x0030
+#define SM_PM_VMREF 0x0034
+#define SM_PM_VMV 0x0038
+#define SM_PM_IER 0x0040
+#define SM_PM_IDR 0x0044
+#define SM_PM_IMR 0x0048
+#define SM_PM_ISR 0x004c
+#define SM_PM_ICR 0x0050
+#define SM_PM_GCCTRL 0x0060
+#define SM_RTC_CTRL 0x0080
+#define SM_RTC_VAL 0x0084
+#define SM_RTC_TOP 0x0088
+#define SM_RTC_IER 0x0090
+#define SM_RTC_IDR 0x0094
+#define SM_RTC_IMR 0x0098
+#define SM_RTC_ISR 0x009c
+#define SM_RTC_ICR 0x00a0
+#define SM_WDT_CTRL 0x00b0
+#define SM_WDT_CLR 0x00b4
+#define SM_WDT_EXT 0x00b8
+#define SM_RC_RCAUSE 0x00c0
+#define SM_EIM_IER 0x0100
+#define SM_EIM_IDR 0x0104
+#define SM_EIM_IMR 0x0108
+#define SM_EIM_ISR 0x010c
+#define SM_EIM_ICR 0x0110
+#define SM_EIM_MODE 0x0114
+#define SM_EIM_EDGE 0x0118
+#define SM_EIM_LEVEL 0x011c
+#define SM_EIM_TEST 0x0120
+#define SM_EIM_NMIC 0x0124
+
+/* Bitfields in PM_CKSEL */
+#define SM_CPUSEL_OFFSET 0
+#define SM_CPUSEL_SIZE 3
+#define SM_CPUDIV_OFFSET 7
+#define SM_CPUDIV_SIZE 1
+#define SM_HSBSEL_OFFSET 8
+#define SM_HSBSEL_SIZE 3
+#define SM_HSBDIV_OFFSET 15
+#define SM_HSBDIV_SIZE 1
+#define SM_PBASEL_OFFSET 16
+#define SM_PBASEL_SIZE 3
+#define SM_PBADIV_OFFSET 23
+#define SM_PBADIV_SIZE 1
+#define SM_PBBSEL_OFFSET 24
+#define SM_PBBSEL_SIZE 3
+#define SM_PBBDIV_OFFSET 31
+#define SM_PBBDIV_SIZE 1
+
+/* Bitfields in PM_PLL0 */
+#define SM_PLLEN_OFFSET 0
+#define SM_PLLEN_SIZE 1
+#define SM_PLLOSC_OFFSET 1
+#define SM_PLLOSC_SIZE 1
+#define SM_PLLOPT_OFFSET 2
+#define SM_PLLOPT_SIZE 3
+#define SM_PLLDIV_OFFSET 8
+#define SM_PLLDIV_SIZE 8
+#define SM_PLLMUL_OFFSET 16
+#define SM_PLLMUL_SIZE 8
+#define SM_PLLCOUNT_OFFSET 24
+#define SM_PLLCOUNT_SIZE 6
+#define SM_PLLTEST_OFFSET 31
+#define SM_PLLTEST_SIZE 1
+
+/* Bitfields in PM_VCTRL */
+#define SM_VAUTO_OFFSET 0
+#define SM_VAUTO_SIZE 1
+#define SM_PM_VCTRL_VAL_OFFSET 8
+#define SM_PM_VCTRL_VAL_SIZE 7
+
+/* Bitfields in PM_VMREF */
+#define SM_REFSEL_OFFSET 0
+#define SM_REFSEL_SIZE 4
+
+/* Bitfields in PM_VMV */
+#define SM_PM_VMV_VAL_OFFSET 0
+#define SM_PM_VMV_VAL_SIZE 8
+
+/* Bitfields in PM_ICR */
+#define SM_LOCK0_OFFSET 0
+#define SM_LOCK0_SIZE 1
+#define SM_LOCK1_OFFSET 1
+#define SM_LOCK1_SIZE 1
+#define SM_WAKE_OFFSET 2
+#define SM_WAKE_SIZE 1
+#define SM_VOK_OFFSET 3
+#define SM_VOK_SIZE 1
+#define SM_VMRDY_OFFSET 4
+#define SM_VMRDY_SIZE 1
+#define SM_CKRDY_OFFSET 5
+#define SM_CKRDY_SIZE 1
+
+/* Bitfields in PM_GCCTRL */
+#define SM_OSCSEL_OFFSET 0
+#define SM_OSCSEL_SIZE 1
+#define SM_PLLSEL_OFFSET 1
+#define SM_PLLSEL_SIZE 1
+#define SM_CEN_OFFSET 2
+#define SM_CEN_SIZE 1
+#define SM_CPC_OFFSET 3
+#define SM_CPC_SIZE 1
+#define SM_DIVEN_OFFSET 4
+#define SM_DIVEN_SIZE 1
+#define SM_DIV_OFFSET 8
+#define SM_DIV_SIZE 8
+
+/* Bitfields in RTC_CTRL */
+#define SM_PCLR_OFFSET 1
+#define SM_PCLR_SIZE 1
+#define SM_TOPEN_OFFSET 2
+#define SM_TOPEN_SIZE 1
+#define SM_CLKEN_OFFSET 3
+#define SM_CLKEN_SIZE 1
+#define SM_PSEL_OFFSET 8
+#define SM_PSEL_SIZE 16
+
+/* Bitfields in RTC_VAL */
+#define SM_RTC_VAL_VAL_OFFSET 0
+#define SM_RTC_VAL_VAL_SIZE 31
+
+/* Bitfields in RTC_TOP */
+#define SM_RTC_TOP_VAL_OFFSET 0
+#define SM_RTC_TOP_VAL_SIZE 32
+
+/* Bitfields in RTC_ICR */
+#define SM_TOPI_OFFSET 0
+#define SM_TOPI_SIZE 1
+
+/* Bitfields in WDT_CTRL */
+#define SM_KEY_OFFSET 24
+#define SM_KEY_SIZE 8
+
+/* Bitfields in RC_RCAUSE */
+#define SM_POR_OFFSET 0
+#define SM_POR_SIZE 1
+#define SM_BOD_OFFSET 1
+#define SM_BOD_SIZE 1
+#define SM_EXT_OFFSET 2
+#define SM_EXT_SIZE 1
+#define SM_WDT_OFFSET 3
+#define SM_WDT_SIZE 1
+#define SM_NTAE_OFFSET 4
+#define SM_NTAE_SIZE 1
+#define SM_SERP_OFFSET 5
+#define SM_SERP_SIZE 1
+
+/* Bitfields in EIM_EDGE */
+#define SM_INT0_OFFSET 0
+#define SM_INT0_SIZE 1
+#define SM_INT1_OFFSET 1
+#define SM_INT1_SIZE 1
+#define SM_INT2_OFFSET 2
+#define SM_INT2_SIZE 1
+#define SM_INT3_OFFSET 3
+#define SM_INT3_SIZE 1
+
+/* Bitfields in EIM_LEVEL */
+
+/* Bitfields in EIM_TEST */
+#define SM_TESTEN_OFFSET 31
+#define SM_TESTEN_SIZE 1
+
+/* Bitfields in EIM_NMIC */
+#define SM_EN_OFFSET 0
+#define SM_EN_SIZE 1
+
+/* Bit manipulation macros */
+#define SM_BIT(name) \
+ (1 << SM_##name##_OFFSET)
+#define SM_BF(name,value) \
+ (((value) & ((1 << SM_##name##_SIZE) - 1)) \
+ << SM_##name##_OFFSET)
+#define SM_BFEXT(name,value) \
+ (((value) >> SM_##name##_OFFSET) \
+ & ((1 << SM_##name##_SIZE) - 1))
+#define SM_BFINS(name,value,old) \
+ (((old) & ~(((1 << SM_##name##_SIZE) - 1) \
+ << SM_##name##_OFFSET)) \
+ | SM_BF(name,value))
+
+/* Register access macros */
+#define sm_readl(port,reg) \
+ readl((port)->regs + SM_##reg)
+#define sm_writel(port,reg,value) \
+ writel((value), (port)->regs + SM_##reg)
+
+#endif /* __CPU_AT32AP_SM_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <asm/sysreg.h>
+
+#ifndef PART_SPECIFIC_BOOTSTRAP
+# define PART_SPECIFIC_BOOTSTRAP
+#endif
+
+#define SYSREG_MMUCR_I_OFFSET 2
+#define SYSREG_MMUCR_S_OFFSET 4
+
+#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
+#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \
+ | SYSREG_BIT(FE) | SYSREG_BIT(RE) \
+ | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
+
+ .text
+ .global _start
+_start:
+ PART_SPECIFIC_BOOTSTRAP
+
+ /* Reset the Status Register */
+ mov r0, lo(SR_INIT)
+ orh r0, hi(SR_INIT)
+ mtsr SYSREG_SR, r0
+
+ /* Reset CPUCR and invalidate the BTB */
+ mov r2, CPUCR_INIT
+ mtsr SYSREG_CPUCR, r2
+
+ /* Flush the caches */
+ mov r1, 0
+ cache r1[4], 8
+ cache r1[0], 0
+ sync 0
+
+ /* Reset the MMU to default settings */
+ mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
+ mtsr SYSREG_MMUCR, r0
+
+ /* Internal RAM should not need any initialization. We might
+ have to initialize external RAM here if the part doesn't
+ have internal RAM (or we may use the data cache) */
+
+ /* Jump to cacheable segment */
+ lddpc pc, 1f
+
+ .align 2
+1: .long 2f
+
+2: lddpc sp, sp_init
+
+ /*
+ * Relocate the data section and initialize .bss. Everything
+ * is guaranteed to be at least doubleword aligned by the
+ * linker script.
+ */
+ lddpc r12, .Ldata_vma
+ lddpc r11, .Ldata_lma
+ lddpc r10, .Ldata_end
+ sub r10, r12
+4: ld.d r8, r11++
+ sub r10, 8
+ st.d r12++, r8
+ brne 4b
+
+ mov r8, 0
+ mov r9, 0
+ lddpc r10, .Lbss_end
+ sub r10, r12
+4: sub r10, 8
+ st.d r12++, r8
+ brne 4b
+
+ /* Initialize the GOT pointer */
+ lddpc r6, got_init
+3: rsub r6, pc
+ ld.w pc, r6[start_u_boot@got]
+
+ .align 2
+ .type sp_init,@object
+sp_init:
+ .long CFG_INIT_SP_ADDR
+got_init:
+ .long 3b - _GLOBAL_OFFSET_TABLE_
+.Ldata_lma:
+ .long __data_lma
+.Ldata_vma:
+ .long _data
+.Ldata_end:
+ .long _edata
+.Lbss_end:
+ .long _end
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
- defined(CONFIG_TQM5200)
+ defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else
START = start.o resetvec.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o
+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#include <command.h>
#include <asm/cache.h>
-/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
int checkcpu (void)
{
return dma_check();
}
#endif
+
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_cpu_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ ulong clock;
+ int len;
+
+ clock = bd->bi_busfreq;
+ p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+#if defined(CONFIG_MPC85XX_TSEC1)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+ memcpy(p, bd->bi_enetaddr, 6);
+#endif
+
+#if defined(CONFIG_HAS_ETH1)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+ memcpy(p, bd->bi_enet1addr, 6);
+#endif
+
+#if defined(CONFIG_HAS_ETH2)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
+ memcpy(p, bd->bi_enet2addr, 6);
+#endif
+
+#if defined(CONFIG_HAS_ETH3)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
+ memcpy(p, bd->bi_enet3addr, 6);
+#endif
+
+}
+#endif
DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_CPM2
static void config_8560_ioports (volatile immap_t * immr)
{
+++ /dev/null
-/*
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao <x.xiao@motorola.com>
- * Adapted for Motorola 85xx chip.
- *
- * (C) Copyright 2003
- * Gleb Natapov <gnatapov@mrv.com>
- * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
- *
- * Hardware I2C driver for MPC107 PCI bridge.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_HARD_I2C
-#include <i2c.h>
-
-#define TIMEOUT (CFG_HZ/4)
-
-#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000))
-
-#define I2CADR &I2C_Addr[0]
-#define I2CFDR &I2C_Addr[4]
-#define I2CCCR &I2C_Addr[8]
-#define I2CCSR &I2C_Addr[12]
-#define I2CCDR &I2C_Addr[16]
-#define I2CDFSRR &I2C_Addr[20]
-
-#define I2C_READ 1
-#define I2C_WRITE 0
-
-void
-i2c_init(int speed, int slaveadd)
-{
- /* stop I2C controller */
- writeb(0x0, I2CCCR);
-
- /* set clock */
- writeb(0x3f, I2CFDR);
-
- /* set default filter */
- writeb(0x10,I2CDFSRR);
-
- /* write slave address */
- writeb(slaveadd, I2CADR);
-
- /* clear status register */
- writeb(0x0, I2CCSR);
-
- /* start I2C controller */
- writeb(MPC85xx_I2CCR_MEN, I2CCCR);
-}
-
-static __inline__ int
-i2c_wait4bus (void)
-{
- ulong timeval = get_timer (0);
-
- while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) {
- if (get_timer (timeval) > TIMEOUT) {
- return -1;
- }
- }
-
- return 0;
-}
-
-static __inline__ int
-i2c_wait (int write)
-{
- u32 csr;
- ulong timeval = get_timer (0);
-
- do {
- csr = readb(I2CCSR);
-
- if (!(csr & MPC85xx_I2CSR_MIF))
- continue;
-
- writeb(0x0, I2CCSR);
-
- if (csr & MPC85xx_I2CSR_MAL) {
- debug("i2c_wait: MAL\n");
- return -1;
- }
-
- if (!(csr & MPC85xx_I2CSR_MCF)) {
- debug("i2c_wait: unfinished\n");
- return -1;
- }
-
- if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) {
- debug("i2c_wait: No RXACK\n");
- return -1;
- }
-
- return 0;
- } while (get_timer (timeval) < TIMEOUT);
-
- debug("i2c_wait: timed out\n");
- return -1;
-}
-
-static __inline__ int
-i2c_write_addr (u8 dev, u8 dir, int rsta)
-{
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX |
- (rsta?MPC85xx_I2CCR_RSTA:0),
- I2CCCR);
-
- writeb((dev << 1) | dir, I2CCDR);
-
- if (i2c_wait (I2C_WRITE) < 0)
- return 0;
-
- return 1;
-}
-
-static __inline__ int
-__i2c_write (u8 *data, int length)
-{
- int i;
-
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX,
- I2CCCR);
-
- for (i=0; i < length; i++) {
- writeb(data[i], I2CCDR);
-
- if (i2c_wait (I2C_WRITE) < 0)
- break;
- }
-
- return i;
-}
-
-static __inline__ int
-__i2c_read (u8 *data, int length)
-{
- int i;
-
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
- ((length == 1) ? MPC85xx_I2CCR_TXAK : 0),
- I2CCCR);
-
- /* dummy read */
- readb(I2CCDR);
-
- for (i=0; i < length; i++) {
- if (i2c_wait (I2C_READ) < 0)
- break;
-
- /* Generate ack on last next to last byte */
- if (i == length - 2)
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
- MPC85xx_I2CCR_TXAK,
- I2CCCR);
-
- /* Generate stop on last byte */
- if (i == length - 1)
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR);
-
- data[i] = readb(I2CCDR);
- }
-
- return i;
-}
-
-int
-i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
-{
- int i = 0;
- u8 *a = (u8*)&addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_READ, 1) == 0)
- goto exit;
-
- i = __i2c_read (data, length);
-
- exit:
- writeb(MPC85xx_I2CCR_MEN, I2CCCR);
-
- return !(i == length);
-}
-
-int
-i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
-{
- int i = 0;
- u8 *a = (u8*)&addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- i = __i2c_write (data, length);
-
- exit:
- writeb(MPC85xx_I2CCR_MEN, I2CCCR);
-
- return !(i == length);
-}
-
-int i2c_probe (uchar chip)
-{
- int tmp;
-
- /*
- * Try to read the first location of the chip. The underlying
- * driver doesn't appear to support sending just the chip address
- * and looking for an <ACK> back.
- */
- udelay(10000);
- return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
-}
-
-uchar i2c_reg_read (uchar i2c_addr, uchar reg)
-{
- uchar buf[1];
-
- i2c_read (i2c_addr, reg, 1, buf, 1);
-
- return (buf[0]);
-}
-
-void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
-{
- i2c_write (i2c_addr, reg, 1, &val, 1);
-}
-
-#endif /* CONFIG_HARD_I2C */
#include <asm/cpm_85xx.h>
#include <pci.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
#if defined(CONFIG_PCI)
+static struct pci_controller *pci_hose;
+
void
-pci_mpc85xx_init(struct pci_controller *hose)
+pci_mpc85xx_init(struct pci_controller *board_hose)
{
+ u16 reg16;
+ u32 dev;
+
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+#ifdef CONFIG_MPC85XX_PCI2
+ volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
+#endif
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ struct pci_controller * hose;
- u16 reg16;
+ pci_hose = board_hose;
+
+ hose = &pci_hose[0];
hose->first_busno = 0;
hose->last_busno = 0xff;
- pci_set_region(hose->regions + 0,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose->regions + 1,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 2;
-
pci_setup_indirect(hose,
(CFG_IMMR+0x8000),
(CFG_IMMR+0x8004));
+ /*
+ * Hose scan.
+ */
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+
+ if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
+ }
+
pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
- pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
- pcix->powar1 = 0x8004401c; /* 512M MEM space */
+ pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
+ POWAR_MEM_WRITE | POWAR_MEM_512M);
- pcix->potar2 = 0x00000000;
+ pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
- pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+ pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
pcix->powbear2 = 0x00000000;
- pcix->powar2 = 0x80088017; /* 16M IO space */
+ pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
+ POWAR_IO_WRITE | POWAR_IO_1M);
pcix->pitar1 = 0x00000000;
pcix->piwbar1 = 0x00000000;
- pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
- * Snoop R/W, 2G */
+ pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
- /*
- * Hose scan.
- */
- pci_register_hose(hose);
+ pcix->powar3 = 0;
+ pcix->powar4 = 0;
+ pcix->piwar2 = 0;
+ pcix->piwar3 = 0;
- pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+ pci_set_region(hose->regions + 0,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
- /*
- * Clear non-reserved bits in status register.
- */
- pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
- pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 2;
+
+ pci_register_hose(hose);
#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
/*
#endif
hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC85XX_PCI2
+ hose = &pci_hose[1];
+
+ hose->first_busno = pci_hose[0].last_busno + 1;
+ hose->last_busno = 0xff;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMR+0x9000),
+ (CFG_IMMR+0x9004));
+
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+
+ pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
+ pcix2->potear1 = 0x00000000;
+ pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
+ pcix2->powbear1 = 0x00000000;
+ pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
+ POWAR_MEM_WRITE | POWAR_MEM_512M);
+
+ pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
+ pcix2->potear2 = 0x00000000;
+ pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
+ pcix2->powbear2 = 0x00000000;
+ pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
+ POWAR_IO_WRITE | POWAR_IO_1M);
+
+ pcix2->pitar1 = 0x00000000;
+ pcix2->piwbar1 = 0x00000000;
+ pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
+
+ pcix2->powar3 = 0;
+ pcix2->powar4 = 0;
+ pcix2->piwar2 = 0;
+ pcix2->piwar3 = 0;
+
+ pci_set_region(hose->regions + 0,
+ CFG_PCI2_MEM_BASE,
+ CFG_PCI2_MEM_PHYS,
+ CFG_PCI2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ pci_set_region(hose->regions + 1,
+ CFG_PCI2_IO_BASE,
+ CFG_PCI2_IO_PHYS,
+ CFG_PCI2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 2;
+
+ /*
+ * Hose scan.
+ */
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+#endif
}
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[0].first_busno;
+ p[1] = pci_hose[0].last_busno;
+ }
+
+#ifdef CONFIG_MPC85XX_PCI2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[1].first_busno;
+ p[1] = pci_hose[1].last_busno;
+ }
+#endif
+}
+#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_PCI */
800,
900,
250,
- 330, /* FIXME: Is 333 better/valid? */
- 660, /* FIXME: Is 667 better/valid? */
+ 330,
+ 660,
750,
0, /* undefined */
0 /* undefined */
}
+/*
+ * Determine Refresh Rate. Ignore self refresh bit on DDR I.
+ * Table from SPD Spec, Byte 12, converted to picoseconds and
+ * filled in with "default" normal values.
+ */
+unsigned int determine_refresh_rate(unsigned int spd_refresh)
+{
+ unsigned int refresh_time_ns[8] = {
+ 15625000, /* 0 Normal 1.00x */
+ 3900000, /* 1 Reduced .25x */
+ 7800000, /* 2 Extended .50x */
+ 31300000, /* 3 Extended 2.00x */
+ 62500000, /* 4 Extended 4.00x */
+ 125000000, /* 5 Extended 8.00x */
+ 15625000, /* 6 Normal 1.00x filler */
+ 15625000, /* 7 Normal 1.00x filler */
+ };
+
+ return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
+}
+
+
long int
spd_sdram(void)
{
unsigned int rank_density;
unsigned int odt_rd_cfg, odt_wr_cfg;
unsigned int odt_cfg, mode_odt_enable;
+ unsigned int refresh_clk;
+#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
+ unsigned char clk_adjust;
+#endif
unsigned int dqs_cfg;
unsigned char twr_clk, twtr_clk, twr_auto_clk;
unsigned int tCKmin_ps, tCKmax_ps;
ddr->sdram_mode_2 = 0;
debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
-
/*
- * Determine Refresh Rate. Ignore self refresh bit on DDR I.
- * Table from SPD Spec, Byte 12, converted to picoseconds and
- * filled in with "default" normal values.
+ * Determine Refresh Rate.
*/
- {
- unsigned int refresh_clk;
- unsigned int refresh_time_ns[8] = {
- 15625000, /* 0 Normal 1.00x */
- 3900000, /* 1 Reduced .25x */
- 7800000, /* 2 Extended .50x */
- 31300000, /* 3 Extended 2.00x */
- 62500000, /* 4 Extended 4.00x */
- 125000000, /* 5 Extended 8.00x */
- 15625000, /* 6 Normal 1.00x filler */
- 15625000, /* 7 Normal 1.00x filler */
- };
-
- refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
+ refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
- /*
- * Set BSTOPRE to 0x100 for page mode
- * If auto-charge is used, set BSTOPRE = 0
- */
- ddr->sdram_interval =
- (0
- | (refresh_clk & 0x3fff) << 16
- | 0x100
- );
- debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
- }
+ /*
+ * Set BSTOPRE to 0x100 for page mode
+ * If auto-charge is used, set BSTOPRE = 0
+ */
+ ddr->sdram_interval =
+ (0
+ | (refresh_clk & 0x3fff) << 16
+ | 0x100
+ );
+ debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
/*
* Is this an ECC DDR chip?
#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
- {
- unsigned char clk_adjust;
-
- /*
- * Setup the clock control.
- * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
- * SDRAM_CLK_CNTL[5-7] = Clock Adjust
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- clk_adjust = 0x6;
- } else {
- clk_adjust = 0x7;
- }
+ /*
+ * Setup the clock control.
+ * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+ * SDRAM_CLK_CNTL[5-7] = Clock Adjust
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ clk_adjust = 0x6;
+ else
+ clk_adjust = 0x7;
- ddr->sdram_clk_cntl = (0
+ ddr->sdram_clk_cntl = (0
| 0x80000000
| (clk_adjust << 23)
);
- debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
- }
+ debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
#endif
/*
}
}
- /* 8K */
- dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
- /* 16K */
- dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
- /* 32K */
- dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
- /* 64K */
- dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
- /* 128k */
- dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
- /* 256k */
- dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
- /* 512k */
- dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
- /* 1M */
- dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
- /* 2M */
- dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
- /* 4M */
- dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
+ dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
+ dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
+ dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
+ dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
+ dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
+ dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
+ dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
+ dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+ dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+ dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
--- /dev/null
+#
+# (C) Copyright 2002,2003 Motorola Inc.
+# Xianghua Xiao,X.Xiao@motorola.com
+#
+# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
+# Jeff Brown
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o #resetvec.o
+SOBJS = cache.o
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
+ pci.o pcie_indirect.o spd_sdram.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(ASOBJS) $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef CACHE_LINE_SIZE
+# define CACHE_LINE_SIZE L1_CACHE_BYTES
+#endif
+
+#if CACHE_LINE_SIZE == 128
+#define LG_CACHE_LINE_SIZE 7
+#elif CACHE_LINE_SIZE == 32
+#define LG_CACHE_LINE_SIZE 5
+#elif CACHE_LINE_SIZE == 16
+#define LG_CACHE_LINE_SIZE 4
+#elif CACHE_LINE_SIZE == 8
+#define LG_CACHE_LINE_SIZE 3
+#else
+# error "Invalid cache line size!"
+#endif
+
+/*
+ * Most of this code is taken from 74xx_7xx/cache.S
+ * and then cleaned up a bit
+ */
+
+/*
+ * Invalidate L1 instruction cache.
+ */
+_GLOBAL(invalidate_l1_instruction_cache)
+ /* use invalidate-all bit in HID0 */
+ mfspr r3,HID0
+ ori r3,r3,HID0_ICFI
+ mtspr HID0,r3
+ isync
+ blr
+
+/*
+ * Invalidate L1 data cache.
+ */
+_GLOBAL(invalidate_l1_data_cache)
+ mfspr r3,HID0
+ ori r3,r3,HID0_DCFI
+ mtspr HID0,r3
+ isync
+ blr
+
+/*
+ * Flush data cache.
+ */
+_GLOBAL(flush_data_cache)
+ lis r3,0
+ lis r5,CACHE_LINE_SIZE
+flush:
+ cmp 0,1,r3,r5
+ bge done
+ lwz r5,0(r3)
+ lis r5,CACHE_LINE_SIZE
+ addi r3,r3,0x4
+ b flush
+done:
+ blr
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ * This is a no-op on the 601.
+ *
+ * flush_icache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_icache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,LG_CACHE_LINE_SIZE
+ beqlr
+ mtctr r4
+ mr r6,r3
+1: dcbst 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ mtctr r4
+2: icbi 0,r6
+ addi r6,r6,CACHE_LINE_SIZE
+ bdnz 2b
+ sync /* additional sync needed on g4 */
+ isync
+ blr
+/*
+ * Write any modified data cache blocks out to memory.
+ * Does not invalidate the corresponding cache lines (especially for
+ * any corresponding instruction cache).
+ *
+ * clean_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(clean_dcache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5 /* align r3 down to cache line */
+ subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
+ add r4,r4,r5 /* r4 += cache_line_size-1 */
+ srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
+ beqlr /* if r4 == 0 return */
+ mtctr r4 /* ctr = r4 */
+
+ sync
+1: dcbst 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ blr
+
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ *
+ * flush_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_dcache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,LG_CACHE_LINE_SIZE
+ beqlr
+ mtctr r4
+
+ sync
+1: dcbf 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbf's to get to ram */
+ blr
+
+/*
+ * Like above, but invalidate the D-cache. This is used by the 8xx
+ * to invalidate the cache so the PPC core doesn't get stale data
+ * from the CPM (no cache snooping here :-).
+ *
+ * invalidate_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(invalidate_dcache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,LG_CACHE_LINE_SIZE
+ beqlr
+ mtctr r4
+
+ sync
+1: dcbi 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbi's to get to ram */
+ blr
+
+/*
+ * Flush a particular page from the data cache to RAM.
+ * Note: this is necessary because the instruction cache does *not*
+ * snoop from the data cache.
+ *
+ * void __flush_page_to_ram(void *page)
+ */
+_GLOBAL(__flush_page_to_ram)
+ rlwinm r3,r3,0,0,19 /* Get page base address */
+ li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
+ mtctr r4
+ mr r6,r3
+0: dcbst 0,r3 /* Write line to ram */
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 0b
+ sync
+ mtctr r4
+1: icbi 0,r6
+ addi r6,r6,CACHE_LINE_SIZE
+ bdnz 1b
+ sync
+ isync
+ blr
+
+/*
+ * Flush a particular page from the instruction cache.
+ * Note: this is necessary because the instruction cache does *not*
+ * snoop from the data cache.
+ *
+ * void __flush_icache_page(void *page)
+ */
+_GLOBAL(__flush_icache_page)
+ li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
+ mtctr r4
+1: icbi 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync
+ isync
+ blr
+
+/*
+ * Clear a page using the dcbz instruction, which doesn't cause any
+ * memory traffic (except to write out any cache lines which get
+ * displaced). This only works on cacheable memory.
+ */
+_GLOBAL(clear_page)
+ li r0,4096/CACHE_LINE_SIZE
+ mtctr r0
+1: dcbz 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ blr
+
+/*
+ * Enable L1 Instruction cache
+ */
+_GLOBAL(icache_enable)
+ mfspr r3, HID0
+ li r5, HID0_ICFI|HID0_ILOCK
+ andc r3, r3, r5
+ ori r3, r3, HID0_ICE
+ ori r5, r3, HID0_ICFI
+ mtspr HID0, r5
+ mtspr HID0, r3
+ isync
+ blr
+
+/*
+ * Disable L1 Instruction cache
+ */
+_GLOBAL(icache_disable)
+ mfspr r3, HID0
+ li r5, 0
+ ori r5, r5, HID0_ICE
+ andc r3, r3, r5
+ mtspr HID0, r3
+ isync
+ blr
+
+/*
+ * Is instruction cache enabled?
+ */
+_GLOBAL(icache_status)
+ mfspr r3, HID0
+ andi. r3, r3, HID0_ICE
+ blr
+
+
+_GLOBAL(l1dcache_enable)
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ ori r3, r3, HID0_DCE
+ ori r5, r3, HID0_DCFI
+ mtspr HID0, r5 /* enable + invalidate */
+ mtspr HID0, r3 /* enable */
+ sync
+ blr
+
+/*
+ * Enable data cache(s) - L1 and optionally L2
+ * Calls l2cache_enable. LR saved in r5
+ */
+_GLOBAL(dcache_enable)
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ ori r3, r3, HID0_DCE
+ ori r5, r3, HID0_DCFI
+ mtspr HID0, r5 /* enable + invalidate */
+ mtspr HID0, r3 /* enable */
+ sync
+#ifdef CFG_L2
+ mflr r5
+ bl l2cache_enable /* uses r3 and r4 */
+ sync
+ mtlr r5
+#endif
+ blr
+
+
+/*
+ * Disable data cache(s) - L1 and optionally L2
+ * Calls flush_data_cache and l2cache_disable_no_flush.
+ * LR saved in r4
+ */
+_GLOBAL(dcache_disable)
+ mflr r4 /* save link register */
+ bl flush_data_cache /* uses r3 and r5 */
+ sync
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ li r5, HID0_DCE|HID0_DCFI
+ andc r3, r3, r5 /* no enable, no invalidate */
+ mtspr HID0, r3
+ sync
+#ifdef CFG_L2
+ bl l2cache_disable_no_flush /* uses r3 */
+#endif
+ mtlr r4 /* restore link register */
+ blr
+
+/*
+ * Is data cache enabled?
+ */
+_GLOBAL(dcache_status)
+ mfspr r3, HID0
+ andi. r3, r3, HID0_DCE
+ blr
+
+/*
+ * Invalidate L2 cache using L2I, assume L2 is enabled
+ */
+_GLOBAL(l2cache_invalidate)
+ mfspr r3, l2cr
+ rlwinm. r3, r3, 0, 0, 0
+ beq 1f
+
+ mfspr r3, l2cr
+ rlwinm r3, r3, 0, 1, 31
+
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ sync
+ mtspr l2cr, r3
+ sync
+1: mfspr r3, l2cr
+ oris r3, r3, L2CR_L2I@h
+ mtspr l2cr, r3
+
+invl2:
+ mfspr r3, l2cr
+ andi. r3, r3, L2CR_L2I@h
+ bne invl2
+ blr
+
+/*
+ * Enable L2 cache
+ * Calls l2cache_invalidate. LR is saved in r4
+ */
+_GLOBAL(l2cache_enable)
+ mflr r4 /* save link register */
+ bl l2cache_invalidate /* uses r3 */
+ sync
+ lis r3, L2_ENABLE@h
+ ori r3, r3, L2_ENABLE@l
+ mtspr l2cr, r3
+ isync
+ mtlr r4 /* restore link register */
+ blr
+
+/*
+ * Disable L2 cache
+ * Calls flush_data_cache. LR is saved in r4
+ */
+_GLOBAL(l2cache_disable)
+ mflr r4 /* save link register */
+ bl flush_data_cache /* uses r3 and r5 */
+ sync
+ mtlr r4 /* restore link register */
+l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
+ lis r3, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ mtspr l2cr, r3
+ isync
+ blr
--- /dev/null
+#
+# (C) Copyright 2004 Freescale Semiconductor.
+# Jeff Brown
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <mpc86xx.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+#ifdef CONFIG_MPC8641HPCN
+extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[]);
+#endif
+
+
+int
+checkcpu(void)
+{
+ sys_info_t sysinfo;
+ uint pvr, svr;
+ uint ver;
+ uint major, minor;
+ uint lcrr; /* local bus clock ratio register */
+ uint clkdiv; /* clock divider portion of lcrr */
+
+ puts("Freescale PowerPC\n");
+
+ pvr = get_pvr();
+ ver = PVR_VER(pvr);
+ major = PVR_MAJ(pvr);
+ minor = PVR_MIN(pvr);
+
+ puts("CPU:\n");
+ puts(" Core: ");
+
+ switch (ver) {
+ case PVR_VER(PVR_86xx):
+ puts("E600");
+ break;
+ default:
+ puts("Unknown");
+ break;
+ }
+ printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
+
+ svr = get_svr();
+ ver = SVR_VER(svr);
+ major = SVR_MAJ(svr);
+ minor = SVR_MIN(svr);
+
+ puts(" System: ");
+ switch (ver) {
+ case SVR_8641:
+ if (SVR_SUBVER(svr) == 1) {
+ puts("8641D");
+ } else {
+ puts("8641");
+ }
+ break;
+ default:
+ puts("Unknown");
+ break;
+ }
+ printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
+
+ get_sys_info(&sysinfo);
+
+ puts(" Clocks: ");
+ printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
+ printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
+ printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+
+#if defined(CFG_LBC_LCRR)
+ lcrr = CFG_LBC_LCRR;
+#else
+ {
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+ lcrr = lbc->lcrr;
+ }
+#endif
+ clkdiv = lcrr & 0x0f;
+ if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+ printf("LBC:%4lu MHz\n",
+ sysinfo.freqSystemBus / 1000000 / clkdiv);
+ } else {
+ printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
+ }
+
+ puts(" L2: ");
+ if (get_l2cr() & 0x80000000)
+ puts("Enabled\n");
+ else
+ puts("Disabled\n");
+
+ return 0;
+}
+
+
+static inline void
+soft_restart(unsigned long addr)
+{
+#ifndef CONFIG_MPC8641HPCN
+
+ /*
+ * SRR0 has system reset vector, SRR1 has default MSR value
+ * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
+ */
+
+ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
+ __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
+ __asm__ __volatile__ ("mtspr 27, 4");
+ __asm__ __volatile__ ("rfi");
+
+#else /* CONFIG_MPC8641HPCN */
+
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+
+#endif /* !CONFIG_MPC8641HPCN */
+
+ while (1) ; /* not reached */
+}
+
+
+/*
+ * No generic way to do board reset. Simply call soft_reset.
+ */
+void
+do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#ifndef CONFIG_MPC8641HPCN
+
+#ifdef CFG_RESET_ADDRESS
+ ulong addr = CFG_RESET_ADDRESS;
+#else
+ /*
+ * note: when CFG_MONITOR_BASE points to a RAM address,
+ * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+ * address. Better pick an address known to be invalid on your
+ * system and assign it to CFG_RESET_ADDRESS.
+ */
+ ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
+#endif
+
+ /* flush and disable I/D cache */
+ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
+ __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
+ __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
+ __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 4");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 5");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+
+ soft_restart(addr);
+
+#else /* CONFIG_MPC8641HPCN */
+
+ mpc8641_reset_board(cmdtp, flag, argc, argv);
+
+#endif /* !CONFIG_MPC8641HPCN */
+
+ while (1) ; /* not reached */
+}
+
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long
+get_tbclk(void)
+{
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+ return (sys_info.freqSystemBus + 3L) / 4L;
+}
+
+
+#if defined(CONFIG_WATCHDOG)
+void
+watchdog_reset(void)
+{
+}
+#endif /* CONFIG_WATCHDOG */
+
+
+#if defined(CONFIG_DDR_ECC)
+void
+dma_init(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+
+ dma->satr0 = 0x00040000;
+ dma->datr0 = 0x00040000;
+ asm("sync; isync");
+}
+
+uint
+dma_check(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile uint status = dma->sr0;
+
+ /* While the channel is busy, spin */
+ while ((status & 4) == 4) {
+ status = dma->sr0;
+ }
+
+ if (status != 0) {
+ printf("DMA Error: status = %x\n", status);
+ }
+ return status;
+}
+
+int
+dma_xfer(void *dest, uint count, void *src)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+
+ dma->dar0 = (uint) dest;
+ dma->sar0 = (uint) src;
+ dma->bcr0 = count;
+ dma->mr0 = 0xf000004;
+ asm("sync;isync");
+ dma->mr0 = 0xf000005;
+ asm("sync;isync");
+ return dma_check();
+}
+
+#endif /* CONFIG_DDR_ECC */
+
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_cpu_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ ulong clock;
+ int len;
+
+ clock = bd->bi_busfreq;
+ p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+#if defined(CONFIG_MPC86XX_TSEC1)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+ memcpy(p, bd->bi_enetaddr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC2)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+ memcpy(p, bd->bi_enet1addr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC3)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
+ memcpy(p, bd->bi_enet2addr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC4)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
+ memcpy(p, bd->bi_enet3addr, 6);
+#endif
+
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpu_init.c - low level cpu init
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map
+ * initialize a bunch of registers
+ */
+
+void cpu_init_f(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset ((void *) gd, 0, sizeof (gd_t));
+
+ /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+ * addresses - these have to be modified later when FLASH size
+ * has been determined
+ */
+
+#if defined(CFG_OR0_REMAP)
+ memctl->or0 = CFG_OR0_REMAP;
+#endif
+#if defined(CFG_OR1_REMAP)
+ memctl->or1 = CFG_OR1_REMAP;
+#endif
+
+ /* now restrict to preliminary range */
+#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
+ memctl->br0 = CFG_BR0_PRELIM;
+ memctl->or0 = CFG_OR0_PRELIM;
+#endif
+
+#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
+ memctl->or1 = CFG_OR1_PRELIM;
+ memctl->br1 = CFG_BR1_PRELIM;
+#endif
+
+#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
+ memctl->or2 = CFG_OR2_PRELIM;
+ memctl->br2 = CFG_BR2_PRELIM;
+#endif
+
+#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
+ memctl->or3 = CFG_OR3_PRELIM;
+ memctl->br3 = CFG_BR3_PRELIM;
+#endif
+
+#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
+ memctl->or4 = CFG_OR4_PRELIM;
+ memctl->br4 = CFG_BR4_PRELIM;
+#endif
+
+#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
+ memctl->or5 = CFG_OR5_PRELIM;
+ memctl->br5 = CFG_BR5_PRELIM;
+#endif
+
+#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
+ memctl->or6 = CFG_OR6_PRELIM;
+ memctl->br6 = CFG_BR6_PRELIM;
+#endif
+
+#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
+ memctl->or7 = CFG_OR7_PRELIM;
+ memctl->br7 = CFG_BR7_PRELIM;
+#endif
+
+ /* enable the timebase bit in HID0 */
+ set_hid0(get_hid0() | 0x4000000);
+
+ /* enable SYNCBE | ABE bits in HID1 */
+ set_hid1(get_hid1() | 0x00000C00);
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 (440 port)
+ * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
+ *
+ * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port)
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <ppc_asm.tmpl>
+
+unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */
+unsigned long timestamp;
+
+
+static __inline__ unsigned long get_msr(void)
+{
+ unsigned long msr;
+
+ asm volatile ("mfmsr %0":"=r" (msr):);
+
+ return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+ asm volatile ("mtmsr %0"::"r" (msr));
+}
+
+static __inline__ unsigned long get_dec(void)
+{
+ unsigned long val;
+
+ asm volatile ("mfdec %0":"=r" (val):);
+
+ return val;
+}
+
+static __inline__ void set_dec(unsigned long val)
+{
+ if (val)
+ asm volatile ("mtdec %0"::"r" (val));
+}
+
+/* interrupt is not supported yet */
+int interrupt_init_cpu(unsigned *decrementer_count)
+{
+ return 0;
+}
+
+int interrupt_init(void)
+{
+ int ret;
+
+ /* call cpu specific function from $(CPU)/interrupts.c */
+ ret = interrupt_init_cpu(&decrementer_count);
+
+ if (ret)
+ return ret;
+
+ decrementer_count = get_tbclk() / CFG_HZ;
+ debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n",
+ (get_tbclk() / 1000000),
+ decrementer_count);
+
+ set_dec(decrementer_count);
+
+ set_msr(get_msr() | MSR_EE);
+
+ debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n",
+ get_msr(),
+ get_dec());
+
+ return 0;
+}
+
+void enable_interrupts(void)
+{
+ set_msr(get_msr() | MSR_EE);
+}
+
+/* returns flag if MSR_EE was set before */
+int disable_interrupts(void)
+{
+ ulong msr = get_msr();
+
+ set_msr(msr & ~MSR_EE);
+ return (msr & MSR_EE) != 0;
+}
+
+void increment_timestamp(void)
+{
+ timestamp++;
+}
+
+/*
+ * timer_interrupt - gets called when the decrementer overflows,
+ * with interrupts disabled.
+ * Trivial implementation - no need to be really accurate.
+ */
+void timer_interrupt_cpu(struct pt_regs *regs)
+{
+ /* nothing to do here */
+}
+
+void timer_interrupt(struct pt_regs *regs)
+{
+ /* call cpu specific function from $(CPU)/interrupts.c */
+ timer_interrupt_cpu(regs);
+
+ timestamp++;
+
+ ppcDcbf(×tamp);
+
+ /* Restore Decrementer Count */
+ set_dec(decrementer_count);
+
+#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
+ if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0)
+ WATCHDOG_RESET();
+#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_STATUS_LED
+ status_led_tick(timestamp);
+#endif /* CONFIG_STATUS_LED */
+
+#ifdef CONFIG_SHOW_ACTIVITY
+ board_show_activity(timestamp);
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+}
+
+void reset_timer(void)
+{
+ timestamp = 0;
+}
+
+ulong get_timer(ulong base)
+{
+ return timestamp - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+/*
+ * Install and free a interrupt handler. Not implemented yet.
+ */
+
+void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+}
+
+void irq_free_handler(int vec)
+{
+}
+
+/*
+ * irqinfo - print information about PCI devices,not implemented.
+ */
+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf("\nInterrupt-unsupported:\n");
+
+ return 0;
+}
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt(struct pt_regs *regs)
+{
+ puts("external_interrupt (oops!)\n");
+}
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor,Inc.
+ * 2005, 2006. All rights reserved.
+ *
+ * Ed Swarthout (ed.swarthout@freescale.com)
+ * Jason Jin (Jason.jin@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCIE Configuration space access support for PCIE Bridge
+ */
+#include <common.h>
+#include <pci.h>
+
+#if defined(CONFIG_PCI)
+void
+pci_mpc86xx_init(struct pci_controller *hose)
+{
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_pex_t *pcie1 = &immap->im_pex1;
+ u16 temp16;
+ u32 temp32;
+
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+ uint pcie1_host = (host1_agent == 2) || (host1_agent == 3);
+ uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1);
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+
+ if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 ||
+ io_sel == 7 || io_sel == 0xf)
+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ printf("PCI-EXPRESS 1: Configured as %s \n",
+ pcie1_agent ? "Agent" : "Host");
+ if (pcie1_agent)
+ return; /*Don't scan bus when configured as agent */
+ printf(" Scanning PCIE bus");
+ debug("0x%08x=0x%08x ",
+ &pcie1->pme_msg_det,
+ pcie1->pme_msg_det);
+ if (pcie1->pme_msg_det) {
+ pcie1->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pcie1->pme_msg_det);
+ }
+ debug("\n");
+ } else {
+ printf("PCI-EXPRESS 1 disabled!\n");
+ return;
+ }
+
+ /*
+ * Set first_bus=0 only skipped B0:D0:F0 which is
+ * a reserved device in M1575, but make it easy for
+ * most of the scan process.
+ */
+ hose->first_busno = 0x00;
+ hose->last_busno = 0xfe;
+
+ pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
+
+ pci_hose_read_config_word(hose,
+ PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16);
+ temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_hose_write_config_word(hose,
+ PCI_BDF(0, 0, 0), PCI_COMMAND, temp16);
+
+ pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose,
+ PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80);
+
+ pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
+ &temp32);
+ temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+ pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
+ temp32);
+
+ pcie1->powar1 = 0;
+ pcie1->powar2 = 0;
+ pcie1->piwar1 = 0;
+ pcie1->piwar1 = 0;
+
+ pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcie1->powar1 = 0x8004401c; /* 512M MEM space */
+ pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcie1->potear1 = 0x00000000;
+
+ pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+ pcie1->powar2 = 0x80088017; /* 16M IO space */
+ pcie1->potar2 = 0x00000000;
+ pcie1->potear2 = 0x00000000;
+
+ pcie1->pitar1 = 0x00000000;
+ pcie1->piwbar1 = 0x00000000;
+ /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */
+ pcie1->piwar1 = 0xa0f5501e;
+
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+ debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno);
+ debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno);
+
+ printf("....PCIE1 scan & enumeration done\n");
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+/*
+ * Support for indirect PCI bridges.
+ *
+ * Copyright (c) Freescale Semiconductor, Inc.
+ * 2006. All rights reserved.
+ *
+ * Jason Jin <Jason.jin@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * partly derived from
+ * arch/powerpc/platforms/86xx/mpc86xx_pcie.c
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define PCI_CFG_OUT out_be32
+#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
+
+static int
+indirect_read_config_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ int len,
+ u32 *val)
+{
+ int bus = PCI_BUS(dev);
+
+ volatile unsigned char *cfg_data;
+ u32 temp;
+
+ PEX_FIX;
+ if (bus == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000001);
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000000);
+ }
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ PEX_FIX;
+ temp = in_le32((u32 *) cfg_data);
+ switch (len) {
+ case 1:
+ *val = (temp >> (((offset & 3)) * 8)) & 0xff;
+ break;
+ case 2:
+ *val = (temp >> (((offset & 3)) * 8)) & 0xffff;
+ break;
+ default:
+ *val = temp;
+ break;
+ }
+
+ return 0;
+}
+
+static int
+indirect_write_config_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ int len,
+ u32 val)
+{
+ int bus = PCI_BUS(dev);
+ volatile unsigned char *cfg_data;
+ u32 temp;
+
+ PEX_FIX;
+ if (bus == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000001);
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000000);
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ switch (len) {
+ case 1:
+ PEX_FIX;
+ temp = in_le32((u32 *) cfg_data);
+ temp = (temp & ~(0xff << ((offset & 3) * 8))) |
+ (val << ((offset & 3) * 8));
+ PEX_FIX;
+ out_le32((u32 *) cfg_data, temp);
+ break;
+ case 2:
+ PEX_FIX;
+ temp = in_le32((u32 *) cfg_data);
+ temp = (temp & ~(0xffff << ((offset & 3) * 8)));
+ temp |= (val << ((offset & 3) * 8));
+ PEX_FIX;
+ out_le32((u32 *) cfg_data, temp);
+ break;
+ default:
+ PEX_FIX;
+ out_le32((u32 *) cfg_data, val);
+ break;
+ }
+ PEX_FIX;
+ return 0;
+}
+
+static int
+indirect_read_config_byte_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u8 *val)
+{
+ u32 val32;
+ indirect_read_config_pcie(hose, dev, offset, 1, &val32);
+ *val = (u8) val32;
+ return 0;
+}
+
+static int
+indirect_read_config_word_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u16 *val)
+{
+ u32 val32;
+ indirect_read_config_pcie(hose, dev, offset, 2, &val32);
+ *val = (u16) val32;
+ return 0;
+}
+
+static int
+indirect_read_config_dword_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u32 *val)
+{
+ return indirect_read_config_pcie(hose, dev, offset, 4, val);
+}
+
+static int
+indirect_write_config_byte_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u8 val)
+{
+ return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val);
+}
+
+static int
+indirect_write_config_word_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ unsigned short val)
+{
+ return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val);
+}
+
+static int
+indirect_write_config_dword_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u32 val)
+{
+ return indirect_write_config_pcie(hose, dev, offset, 4, val);
+}
+
+void
+pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
+{
+ pci_set_ops(hose,
+ indirect_read_config_byte_pcie,
+ indirect_read_config_word_pcie,
+ indirect_read_config_dword_pcie,
+ indirect_write_config_byte_pcie,
+ indirect_write_config_word_pcie,
+ indirect_write_config_dword_pcie);
+
+ hose->cfg_addr = (unsigned int *)cfg_addr;
+ hose->cfg_data = (unsigned char *)cfg_data;
+}
+
+#endif /* CONFIG_PCI */
--- /dev/null
+ .section .resetvec,"ax"
+ b _start
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <spd.h>
+#include <asm/mmu.h>
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void dma_init(void);
+extern uint dma_check(void);
+extern int dma_xfer(void *dest, uint count, void *src);
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+
+#ifndef CFG_READ_SPD
+#define CFG_READ_SPD i2c_read
+#endif
+
+/*
+ * Only one of the following three should be 1; others should be 0
+ * By default the cache line interleaving is selected if
+ * the CONFIG_DDR_INTERLEAVE flag is defined
+ */
+#define CFG_PAGE_INTERLEAVING 0
+#define CFG_BANK_INTERLEAVING 0
+#define CFG_SUPER_BANK_INTERLEAVING 0
+
+/*
+ * Convert picoseconds into clock cycles (rounding up if needed).
+ */
+
+int
+picos_to_clk(int picos)
+{
+ int clks;
+
+ clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
+ if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+ clks++;
+ }
+
+ return clks;
+}
+
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Study these table from Byte 31 of JEDEC SPD Spec.
+ *
+ * DDR I DDR II
+ * Bit Size Size
+ * --- ----- ------
+ * 7 high 512MB 512MB
+ * 6 256MB 256MB
+ * 5 128MB 128MB
+ * 4 64MB 16GB
+ * 3 32MB 8GB
+ * 2 16MB 4GB
+ * 1 2GB 2GB
+ * 0 low 1GB 1GB
+ *
+ * Reorder Table to be linear by stripping the bottom
+ * 2 or 5 bits off and shifting them up to the top.
+ */
+
+unsigned int
+compute_banksize(unsigned int mem_type, unsigned char row_dens)
+{
+ unsigned int bsize;
+
+ if (mem_type == SPD_MEMTYPE_DDR) {
+ /* Bottom 2 bits up to the top. */
+ bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+ debug("DDR: DDR I rank density = 0x%08x\n", bsize);
+ } else {
+ /* Bottom 5 bits up to the top. */
+ bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
+ debug("DDR: DDR II rank density = 0x%08x\n", bsize);
+ }
+ return bsize;
+}
+
+
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II. No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+
+unsigned int
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
+{
+ /*
+ * Table look up the lower nibble, allow DDR I & II.
+ */
+ unsigned int tenths_ps[16] = {
+ 0,
+ 100,
+ 200,
+ 300,
+ 400,
+ 500,
+ 600,
+ 700,
+ 800,
+ 900,
+ 250,
+ 330,
+ 660,
+ 750,
+ 0, /* undefined */
+ 0 /* undefined */
+ };
+
+ unsigned int whole_ns = (spd_val & 0xF0) >> 4;
+ unsigned int tenth_ns = spd_val & 0x0F;
+ unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
+
+ return ps;
+}
+
+
+/*
+ * Determine Refresh Rate. Ignore self refresh bit on DDR I.
+ * Table from SPD Spec, Byte 12, converted to picoseconds and
+ * filled in with "default" normal values.
+ */
+unsigned int determine_refresh_rate(unsigned int spd_refresh)
+{
+ unsigned int refresh_time_ns[8] = {
+ 15625000, /* 0 Normal 1.00x */
+ 3900000, /* 1 Reduced .25x */
+ 7800000, /* 2 Extended .50x */
+ 31300000, /* 3 Extended 2.00x */
+ 62500000, /* 4 Extended 4.00x */
+ 125000000, /* 5 Extended 8.00x */
+ 15625000, /* 6 Normal 1.00x filler */
+ 15625000, /* 7 Normal 1.00x filler */
+ };
+
+ return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
+}
+
+
+long int
+spd_init(unsigned char i2c_address, unsigned int ddr_num,
+ unsigned int dimm_num, unsigned int start_addr)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ spd_eeprom_t spd;
+ unsigned int n_ranks;
+ unsigned int rank_density;
+ unsigned int odt_rd_cfg, odt_wr_cfg;
+ unsigned int odt_cfg, mode_odt_enable;
+ unsigned int refresh_clk;
+#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
+ unsigned char clk_adjust;
+#endif
+ unsigned int dqs_cfg;
+ unsigned char twr_clk, twtr_clk, twr_auto_clk;
+ unsigned int tCKmin_ps, tCKmax_ps;
+ unsigned int max_data_rate;
+ unsigned int busfreq;
+ unsigned sdram_cfg_1;
+ unsigned int memsize;
+ unsigned char caslat, caslat_ctrl;
+ unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+ unsigned int trcd_clk;
+ unsigned int trtp_clk;
+ unsigned char cke_min_clk;
+ unsigned char add_lat;
+ unsigned char wr_lat;
+ unsigned char wr_data_delay;
+ unsigned char four_act;
+ unsigned char cpo;
+ unsigned char burst_len;
+ unsigned int mode_caslat;
+ unsigned char sdram_type;
+ unsigned char d_init;
+ unsigned int law_size;
+ volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+ unsigned int tCycle_ps, modfreq;
+
+ if (ddr_num == 1)
+ ddr = &immap->im_ddr1;
+ else
+ ddr = &immap->im_ddr2;
+
+ /*
+ * Read SPD information.
+ */
+ debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
+ memset((void *)&spd, 0, sizeof(spd));
+ CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
+
+ /*
+ * Check for supported memory module types.
+ */
+ if (spd.mem_type != SPD_MEMTYPE_DDR &&
+ spd.mem_type != SPD_MEMTYPE_DDR2) {
+ debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
+ " Fundamental memory type is 0x%0x\n",
+ dimm_num,
+ ddr_num,
+ spd.mem_type);
+ return 0;
+ }
+
+ debug("\nFound memory of type 0x%02lx ", spd.mem_type);
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ debug("DDR I\n");
+ else
+ debug("DDR II\n");
+
+ /*
+ * These test gloss over DDR I and II differences in interpretation
+ * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
+ * are not supported on DDR I; and not encoded on DDR II.
+ *
+ * Also note that the 8548 controller can support:
+ * 12 <= nrow <= 16
+ * and
+ * 8 <= ncol <= 11 (still, for DDR)
+ * 6 <= ncol <= 9 (for FCRAM)
+ */
+ if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+ printf("DDR: Unsupported number of Row Addr lines: %d.\n",
+ spd.nrow_addr);
+ return 0;
+ }
+ if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+ printf("DDR: Unsupported number of Column Addr lines: %d.\n",
+ spd.ncol_addr);
+ return 0;
+ }
+
+ /*
+ * Determine the number of physical banks controlled by
+ * different Chip Select signals. This is not quite the
+ * same as the number of DIMM modules on the board. Feh.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ n_ranks = spd.nrows;
+ } else {
+ n_ranks = (spd.nrows & 0x7) + 1;
+ }
+
+ debug("DDR: number of ranks = %d\n", n_ranks);
+
+ if (n_ranks > 2) {
+ printf("DDR: Only 2 chip selects are supported: %d\n",
+ n_ranks);
+ return 0;
+ }
+
+ /*
+ * Adjust DDR II IO voltage biasing. It just makes it work.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ gur->ddrioovcr = (0
+ | 0x80000000 /* Enable */
+ | 0x10000000 /* VSEL to 1.8V */
+ );
+ }
+
+ /*
+ * Determine the size of each Rank in bytes.
+ */
+ rank_density = compute_banksize(spd.mem_type, spd.row_dens);
+
+ debug("Start address for this controller is 0x%08lx\n", start_addr);
+
+ /*
+ * ODT configuration recommendation from DDR Controller Chapter.
+ */
+ odt_rd_cfg = 0; /* Never assert ODT */
+ odt_wr_cfg = 0; /* Never assert ODT */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
+ }
+
+#ifdef CONFIG_DDR_INTERLEAVE
+
+ if (dimm_num != 1) {
+ printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
+ return 0;
+ } else {
+ /*
+ * Since interleaved memory only uses CS0, the
+ * memory sticks have to be identical in size and quantity
+ * of ranks. That essentially gives double the size on
+ * one rank, i.e on CS0 for both controllers put together.
+ * Confirm this???
+ */
+ rank_density *= 2;
+
+ /*
+ * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
+ */
+ start_addr = 0;
+ ddr->cs0_bnds = (start_addr >> 8)
+ | (((start_addr + rank_density - 1) >> 24));
+ /*
+ * Default interleaving mode to cache-line interleaving.
+ */
+ ddr->cs0_config = ( 1 << 31
+#if (CFG_PAGE_INTERLEAVING == 1)
+ | (PAGE_INTERLEAVING)
+#elif (CFG_BANK_INTERLEAVING == 1)
+ | (BANK_INTERLEAVING)
+#elif (CFG_SUPER_BANK_INTERLEAVING == 1)
+ | (SUPER_BANK_INTERLEAVING)
+#else
+ | (CACHE_LINE_INTERLEAVING)
+#endif
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+
+ debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
+ debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
+
+ /*
+ * Adjustment for dual rank memory to get correct memory
+ * size (return value of this function).
+ */
+ if (n_ranks == 2) {
+ n_ranks = 1;
+ rank_density /= 2;
+ } else {
+ rank_density /= 2;
+ }
+ }
+#else /* CONFIG_DDR_INTERLEAVE */
+
+ if (dimm_num == 1) {
+ /*
+ * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
+ */
+ ddr->cs0_bnds = (start_addr >> 8)
+ | (((start_addr + rank_density - 1) >> 24));
+
+ ddr->cs0_config = ( 1 << 31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+
+ debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
+ debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
+
+ if (n_ranks == 2) {
+ /*
+ * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
+ * second 256 Meg
+ */
+ ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
+ | (( start_addr + 2*rank_density - 1)
+ >> 24));
+ ddr->cs1_config = ( 1<<31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+ debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
+ debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
+ }
+
+ } else {
+ /*
+ * This is the 2nd DIMM slot for this controller
+ */
+ /*
+ * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
+ */
+ ddr->cs2_bnds = (start_addr >> 8)
+ | (((start_addr + rank_density - 1) >> 24));
+
+ ddr->cs2_config = ( 1 << 31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+
+ debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
+ debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
+
+ if (n_ranks == 2) {
+ /*
+ * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
+ * second 256 Meg
+ */
+ ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
+ | (( start_addr + 2*rank_density - 1)
+ >> 24));
+ ddr->cs3_config = ( 1<<31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+ debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
+ debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
+ }
+ }
+#endif /* CONFIG_DDR_INTERLEAVE */
+
+ /*
+ * Find the largest CAS by locating the highest 1 bit
+ * in the spd.cas_lat field. Translate it to a DDR
+ * controller field value:
+ *
+ * CAS Lat DDR I DDR II Ctrl
+ * Clocks SPD Bit SPD Bit Value
+ * ------- ------- ------- -----
+ * 1.0 0 0001
+ * 1.5 1 0010
+ * 2.0 2 2 0011
+ * 2.5 3 0100
+ * 3.0 4 3 0101
+ * 3.5 5 0110
+ * 4.0 4 0111
+ * 4.5 1000
+ * 5.0 5 1001
+ */
+ caslat = __ilog2(spd.cas_lat);
+ if ((spd.mem_type == SPD_MEMTYPE_DDR)
+ && (caslat > 5)) {
+ printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+ return 0;
+
+ } else if (spd.mem_type == SPD_MEMTYPE_DDR2
+ && (caslat < 2 || caslat > 5)) {
+ printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+ spd.cas_lat);
+ return 0;
+ }
+ debug("DDR: caslat SPD bit is %d\n", caslat);
+
+ /*
+ * Calculate the Maximum Data Rate based on the Minimum Cycle time.
+ * The SPD clk_cycle field (tCKmin) is measured in tenths of
+ * nanoseconds and represented as BCD.
+ */
+ tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
+ debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
+
+ /*
+ * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
+ */
+ max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
+ debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
+
+
+ /*
+ * Adjust the CAS Latency to allow for bus speeds that
+ * are slower than the DDR module.
+ */
+ busfreq = get_bus_freq(0) / 1000000; /* MHz */
+ tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3);
+ modfreq = 2 * 1000 * 1000 / tCycle_ps;
+
+ if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
+ printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
+ return 0;
+ } else if (busfreq < 90) {
+ printf("DDR: platform frequency too low for correct DDR1 operation\n");
+ return 0;
+ }
+
+ if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
+ caslat -= 2;
+ } else {
+ tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
+ modfreq = 2 * 1000 * 1000 / tCycle_ps;
+ if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
+ caslat -= 1;
+ else if (busfreq > max_data_rate) {
+ printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
+ busfreq, max_data_rate);
+ return 0;
+ }
+ }
+
+ /*
+ * Empirically set ~MCAS-to-preamble override for DDR 2.
+ * Your milage will vary.
+ */
+ cpo = 0;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ if (busfreq <= 333) {
+ cpo = 0x7;
+ } else if (busfreq <= 400) {
+ cpo = 0x9;
+ } else {
+ cpo = 0xa;
+ }
+ }
+
+ /*
+ * Convert caslat clocks to DDR controller value.
+ * Force caslat_ctrl to be DDR Controller field-sized.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ caslat_ctrl = (caslat + 1) & 0x07;
+ } else {
+ caslat_ctrl = (2 * caslat - 1) & 0x0f;
+ }
+
+ debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+ caslat, caslat_ctrl);
+
+ /*
+ * Timing Config 0.
+ * Avoid writing for DDR I. The new PQ38 DDR controller
+ * dreams up non-zero default values to be backwards compatible.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ unsigned char taxpd_clk = 8; /* By the book. */
+ unsigned char tmrd_clk = 2; /* By the book. */
+ unsigned char act_pd_exit = 2; /* Empirical? */
+ unsigned char pre_pd_exit = 6; /* Empirical? */
+
+ ddr->timing_cfg_0 = (0
+ | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
+ | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
+ | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
+ | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
+ );
+ debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+
+ }
+
+
+ /*
+ * Some Timing Config 1 values now.
+ * Sneak Extended Refresh Recovery in here too.
+ */
+
+ /*
+ * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+ * use conservative value.
+ * For DDR II, they are bytes 36 and 37, in quarter nanos.
+ */
+
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ twr_clk = 3; /* Clocks */
+ twtr_clk = 1; /* Clocks */
+ } else {
+ twr_clk = picos_to_clk(spd.twr * 250);
+ twtr_clk = picos_to_clk(spd.twtr * 250);
+ }
+
+ /*
+ * Calculate Trfc, in picos.
+ * DDR I: Byte 42 straight up in ns.
+ * DDR II: Byte 40 and 42 swizzled some, in ns.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ trfc = spd.trfc * 1000; /* up to ps */
+ } else {
+ unsigned int byte40_table_ps[8] = {
+ 0,
+ 250,
+ 330,
+ 500,
+ 660,
+ 750,
+ 0,
+ 0
+ };
+
+ trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+ + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+ }
+ trfc_clk = picos_to_clk(trfc);
+
+ /*
+ * Trcd, Byte 29, from quarter nanos to ps and clocks.
+ */
+ trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+ /*
+ * Convert trfc_clk to DDR controller fields. DDR I should
+ * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+ * 8548 controller has an extended REFREC field of three bits.
+ * The controller automatically adds 8 clocks to this value,
+ * so preadjust it down 8 first before splitting it up.
+ */
+ trfc_low = (trfc_clk - 8) & 0xf;
+ trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
+
+ /*
+ * Sneak in some Extended Refresh Recovery.
+ */
+ ddr->ext_refrec = (trfc_high << 16);
+ debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+
+ ddr->timing_cfg_1 =
+ (0
+ | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
+ | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
+ | (trcd_clk << 20) /* ACTTORW */
+ | (caslat_ctrl << 16) /* CASLAT */
+ | (trfc_low << 12) /* REFEC */
+ | ((twr_clk & 0x07) << 8) /* WRRREC */
+ | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
+ | ((twtr_clk & 0x07) << 0) /* WRTORD */
+ );
+
+ debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
+
+
+ /*
+ * Timing_Config_2
+ * Was: 0x00000800;
+ */
+
+ /*
+ * Additive Latency
+ * For DDR I, 0.
+ * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+ * which comes from Trcd, and also note that:
+ * add_lat + caslat must be >= 4
+ */
+ add_lat = 0;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2
+ && (odt_wr_cfg || odt_rd_cfg)
+ && (caslat < 4)) {
+ add_lat = 4 - caslat;
+ if (add_lat >= trcd_clk) {
+ add_lat = trcd_clk - 1;
+ }
+ }
+
+ /*
+ * Write Data Delay
+ * Historically 0x2 == 4/8 clock delay.
+ * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+ */
+ wr_data_delay = 3;
+
+ /*
+ * Write Latency
+ * Read to Precharge
+ * Minimum CKE Pulse Width.
+ * Four Activate Window
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ /*
+ * This is a lie. It should really be 1, but if it is
+ * set to 1, bits overlap into the old controller's
+ * otherwise unused ACSM field. If we leave it 0, then
+ * the HW will magically treat it as 1 for DDR 1. Oh Yea.
+ */
+ wr_lat = 0;
+
+ trtp_clk = 2; /* By the book. */
+ cke_min_clk = 1; /* By the book. */
+ four_act = 1; /* By the book. */
+
+ } else {
+ wr_lat = caslat - 1;
+
+ /* Convert SPD value from quarter nanos to picos. */
+ trtp_clk = picos_to_clk(spd.trtp * 250);
+
+ cke_min_clk = 3; /* By the book. */
+ four_act = picos_to_clk(37500); /* By the book. 1k pages? */
+ }
+
+ ddr->timing_cfg_2 = (0
+ | ((add_lat & 0x7) << 28) /* ADD_LAT */
+ | ((cpo & 0x1f) << 23) /* CPO */
+ | ((wr_lat & 0x7) << 19) /* WR_LAT */
+ | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
+ | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
+ | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
+ | ((four_act & 0x1f) << 0) /* FOUR_ACT */
+ );
+
+ debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
+
+
+ /*
+ * Determine the Mode Register Set.
+ *
+ * This is nominally part specific, but it appears to be
+ * consistent for all DDR I devices, and for all DDR II devices.
+ *
+ * caslat must be programmed
+ * burst length is always 4
+ * burst type is sequential
+ *
+ * For DDR I:
+ * operating mode is "normal"
+ *
+ * For DDR II:
+ * other stuff
+ */
+
+ mode_caslat = 0;
+
+ /*
+ * Table lookup from DDR I or II Device Operation Specs.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ if (1 <= caslat && caslat <= 4) {
+ unsigned char mode_caslat_table[4] = {
+ 0x5, /* 1.5 clocks */
+ 0x2, /* 2.0 clocks */
+ 0x6, /* 2.5 clocks */
+ 0x3 /* 3.0 clocks */
+ };
+ mode_caslat = mode_caslat_table[caslat - 1];
+ } else {
+ puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
+ "2.5 and 3.0 clocks are supported.\n");
+ return 0;
+ }
+
+ } else {
+ if (2 <= caslat && caslat <= 5) {
+ mode_caslat = caslat;
+ } else {
+ puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
+ "4.0 and 5.0 clocks are supported.\n");
+ return 0;
+ }
+ }
+
+ /*
+ * Encoded Burst Length of 4.
+ */
+ burst_len = 2; /* Fiat. */
+
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ twr_auto_clk = 0; /* Historical */
+ } else {
+ /*
+ * Determine tCK max in picos. Grab tWR and convert to picos.
+ * Auto-precharge write recovery is:
+ * WR = roundup(tWR_ns/tCKmax_ns).
+ *
+ * Ponder: Is twr_auto_clk different than twr_clk?
+ */
+ tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
+ twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
+ }
+
+ /*
+ * Mode Reg in bits 16 ~ 31,
+ * Extended Mode Reg 1 in bits 0 ~ 15.
+ */
+ mode_odt_enable = 0x0; /* Default disabled */
+ if (odt_wr_cfg || odt_rd_cfg) {
+ /*
+ * Bits 6 and 2 in Extended MRS(1)
+ * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+ * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+ */
+ mode_odt_enable = 0x40; /* 150 Ohm */
+ }
+
+ ddr->sdram_mode_1 =
+ (0
+ | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
+ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
+ | (twr_auto_clk << 9) /* Write Recovery Autopre */
+ | (mode_caslat << 4) /* caslat */
+ | (burst_len << 0) /* Burst length */
+ );
+
+ debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
+
+ /*
+ * Clear EMRS2 and EMRS3.
+ */
+ ddr->sdram_mode_2 = 0;
+ debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
+
+ /*
+ * Determine Refresh Rate.
+ */
+ refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
+
+ /*
+ * Set BSTOPRE to 0x100 for page mode
+ * If auto-charge is used, set BSTOPRE = 0
+ */
+ ddr->sdram_interval =
+ (0
+ | (refresh_clk & 0x3fff) << 16
+ | 0x100
+ );
+ debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
+
+
+ /*
+ * Is this an ECC DDR chip?
+ * But don't mess with it if the DDR controller will init mem.
+ */
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ if (spd.config == 0x02) {
+ ddr->err_disable = 0x0000000d;
+ ddr->err_sbe = 0x00ff0000;
+ }
+ debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
+ debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
+#endif
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /*
+ * SDRAM Cfg 2
+ */
+
+ /*
+ * When ODT is enabled, Chap 9 suggests asserting ODT to
+ * internal IOs only during reads.
+ */
+ odt_cfg = 0;
+ if (odt_rd_cfg | odt_wr_cfg) {
+ odt_cfg = 0x2; /* ODT to IOs during reads */
+ }
+
+ /*
+ * Try to use differential DQS with DDR II.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ dqs_cfg = 0; /* No Differential DQS for DDR I */
+ } else {
+ dqs_cfg = 0x1; /* Differential DQS for DDR II */
+ }
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Use the DDR controller to auto initialize memory.
+ */
+ d_init = 1;
+ ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
+ debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
+#else
+ /*
+ * Memory will be initialized via DMA, or not at all.
+ */
+ d_init = 0;
+#endif
+
+ ddr->sdram_cfg_2 = (0
+ | (dqs_cfg << 26) /* Differential DQS */
+ | (odt_cfg << 21) /* ODT */
+ | (d_init << 4) /* D_INIT auto init DDR */
+ );
+
+ debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
+
+
+#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
+ /*
+ * Setup the clock control.
+ * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+ * SDRAM_CLK_CNTL[5-7] = Clock Adjust
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ clk_adjust = 0x6;
+ else
+ clk_adjust = 0x7;
+
+ ddr->sdram_clk_cntl = (0
+ | 0x80000000
+ | (clk_adjust << 23)
+ );
+ debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
+#endif
+
+ /*
+ * Figure out memory size in Megabytes.
+ */
+ debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
+ memsize = n_ranks * rank_density / 0x100000;
+ return memsize;
+}
+
+
+unsigned int enable_ddr(unsigned int ddr_num)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ spd_eeprom_t spd1,spd2;
+ volatile ccsr_ddr_t *ddr;
+ unsigned sdram_cfg_1;
+ unsigned char sdram_type, mem_type, config, mod_attr;
+ unsigned char d_init;
+ unsigned int no_dimm1=0, no_dimm2=0;
+
+ /* Set up pointer to enable the current ddr controller */
+ if (ddr_num == 1)
+ ddr = &immap->im_ddr1;
+ else
+ ddr = &immap->im_ddr2;
+
+ /*
+ * Read both dimm slots and decide whether
+ * or not to enable this controller.
+ */
+ memset((void *)&spd1,0,sizeof(spd1));
+ memset((void *)&spd2,0,sizeof(spd2));
+
+ if (ddr_num == 1) {
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
+ 0, 1, (uchar *) &spd1, sizeof(spd1));
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
+ 0, 1, (uchar *) &spd2, sizeof(spd2));
+ } else {
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
+ 0, 1, (uchar *) &spd1, sizeof(spd1));
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
+ 0, 1, (uchar *) &spd2, sizeof(spd2));
+ }
+
+ /*
+ * Check for supported memory module types.
+ */
+ if (spd1.mem_type != SPD_MEMTYPE_DDR
+ && spd1.mem_type != SPD_MEMTYPE_DDR2) {
+ no_dimm1 = 1;
+ } else {
+ debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
+ if (spd1.mem_type == SPD_MEMTYPE_DDR)
+ debug("DDR I\n");
+ else
+ debug("DDR II\n");
+ }
+
+ if (spd2.mem_type != SPD_MEMTYPE_DDR &&
+ spd2.mem_type != SPD_MEMTYPE_DDR2) {
+ no_dimm2 = 1;
+ } else {
+ debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
+ if (spd2.mem_type == SPD_MEMTYPE_DDR)
+ debug("DDR I\n");
+ else
+ debug("DDR II\n");
+ }
+
+#ifdef CONFIG_DDR_INTERLEAVE
+ if (no_dimm1) {
+ printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
+ return 0;
+ }
+#endif
+
+ /*
+ * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
+ */
+ if (no_dimm1 && no_dimm2) {
+ printf("No memory modules found for DDR controller %d!!\n", ddr_num);
+ return 0;
+ } else {
+ mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
+
+ /*
+ * Figure out the settings for the sdram_cfg register.
+ * Build up the entire register in 'sdram_cfg' before
+ * writing since the write into the register will
+ * actually enable the memory controller; all settings
+ * must be done before enabling.
+ *
+ * sdram_cfg[0] = 1 (ddr sdram logic enable)
+ * sdram_cfg[1] = 1 (self-refresh-enable)
+ * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+ * 010 DDR 1 SDRAM
+ * 011 DDR 2 SDRAM
+ */
+ sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
+ sdram_cfg_1 = (0
+ | (1 << 31) /* Enable */
+ | (1 << 30) /* Self refresh */
+ | (sdram_type << 24) /* SDRAM type */
+ );
+
+ /*
+ * sdram_cfg[3] = RD_EN - registered DIMM enable
+ * A value of 0x26 indicates micron registered
+ * DIMMS (micron.com)
+ */
+ mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
+ if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
+ sdram_cfg_1 |= 0x10000000; /* RD_EN */
+ }
+
+#if defined(CONFIG_DDR_ECC)
+
+ config = no_dimm2 ? spd1.config : spd2.config;
+
+ /*
+ * If the user wanted ECC (enabled via sdram_cfg[2])
+ */
+ if (config == 0x02) {
+ ddr->err_disable = 0x00000000;
+ asm volatile("sync;isync;");
+ ddr->err_sbe = 0x00ff0000;
+ ddr->err_int_en = 0x0000000d;
+ sdram_cfg_1 |= 0x20000000; /* ECC_EN */
+ }
+#endif
+
+ /*
+ * Set 1T or 2T timing based on 1 or 2 modules
+ */
+ {
+ if (!(no_dimm1 || no_dimm2)) {
+ /*
+ * 2T timing,because both DIMMS are present.
+ * Enable 2T timing by setting sdram_cfg[16].
+ */
+ sdram_cfg_1 |= 0x8000; /* 2T_EN */
+ }
+ }
+
+ /*
+ * 200 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ */
+ udelay(200);
+
+ /*
+ * Go!
+ */
+ ddr->sdram_cfg_1 = sdram_cfg_1;
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR: memory initializing\n");
+
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+#endif
+
+ debug("Enabled DDR Controller %d\n", ddr_num);
+ return 1;
+ }
+}
+
+
+long int
+spd_sdram(void)
+{
+ int memsize_ddr1_dimm1 = 0;
+ int memsize_ddr1_dimm2 = 0;
+ int memsize_ddr2_dimm1 = 0;
+ int memsize_ddr2_dimm2 = 0;
+ int memsize_total = 0;
+ int memsize_ddr1 = 0;
+ int memsize_ddr2 = 0;
+ unsigned int ddr1_enabled = 0;
+ unsigned int ddr2_enabled = 0;
+ unsigned int law_size_ddr1;
+ unsigned int law_size_ddr2;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+ volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
+ volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+
+#ifdef CONFIG_DDR_INTERLEAVE
+ unsigned int law_size_interleaved;
+
+ memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
+ 1, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr1_dimm1;
+
+ memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
+ 2, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr2_dimm1;
+
+ if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
+ if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
+ memsize_total -= memsize_ddr1_dimm1;
+ else
+ memsize_total -= memsize_ddr2_dimm1;
+ debug("Total memory available for interleaving 0x%08lx\n",
+ memsize_total * 1024 * 1024);
+ debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
+ ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
+ ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
+ debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
+ debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
+ }
+
+ ddr1_enabled = enable_ddr(1);
+ ddr2_enabled = enable_ddr(2);
+
+ /*
+ * Both controllers need to be enabled for interleaving.
+ */
+ if (ddr1_enabled && ddr2_enabled) {
+ law_size_interleaved = 19 + __ilog2(memsize_total);
+
+ /*
+ * Set up LAWBAR for DDR 1 space.
+ */
+ mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+ mcm->lawar1 = (LAWAR_EN
+ | LAWAR_TRGT_IF_DDR_INTERLEAVED
+ | (LAWAR_SIZE & law_size_interleaved));
+ debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
+ debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+ debug("Interleaved memory size is 0x%08lx\n", memsize_total);
+
+#ifdef CONFIG_DDR_INTERLEAVE
+#if (CFG_PAGE_INTERLEAVING == 1)
+ printf("Page ");
+#elif (CFG_BANK_INTERLEAVING == 1)
+ printf("Bank ");
+#elif (CFG_SUPER_BANK_INTERLEAVING == 1)
+ printf("Super-bank ");
+#else
+ printf("Cache-line ");
+#endif
+#endif
+ printf("Interleaved");
+ return memsize_total * 1024 * 1024;
+ } else {
+ printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
+ return 0;
+ }
+
+#else
+ /*
+ * Call spd_sdram() routine to init ddr1 - pass I2c address,
+ * controller number, dimm number, and starting address.
+ */
+ memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
+ 1, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr1_dimm1;
+
+ memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
+ 1, 2,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr1_dimm2;
+
+ /*
+ * Enable the DDR controller - pass ddr controller number.
+ */
+ ddr1_enabled = enable_ddr(1);
+
+ /* Keep track of memory to be addressed by DDR1 */
+ memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
+
+ /*
+ * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
+ */
+ if (ddr1_enabled) {
+ law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
+
+ /*
+ * Set up LAWBAR for DDR 1 space.
+ */
+ mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+ mcm->lawar1 = (LAWAR_EN
+ | LAWAR_TRGT_IF_DDR1
+ | (LAWAR_SIZE & law_size_ddr1));
+ debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
+ debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+ }
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
+ 2, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr2_dimm1;
+
+ memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
+ 2, 2,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr2_dimm2;
+
+ ddr2_enabled = enable_ddr(2);
+
+ /* Keep track of memory to be addressed by DDR2 */
+ memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
+
+ if (ddr2_enabled) {
+ law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
+
+ /*
+ * Set up LAWBAR for DDR 2 space.
+ */
+ if (ddr1_enabled)
+ mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
+ & 0xfffff);
+ else
+ mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+
+ mcm->lawar8 = (LAWAR_EN
+ | LAWAR_TRGT_IF_DDR2
+ | (LAWAR_SIZE & law_size_ddr2));
+ debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
+ debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
+ }
+#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
+
+ debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
+ memsize_ddr1, memsize_ddr2);
+
+ /*
+ * If neither DDR controller is enabled return 0.
+ */
+ if (!ddr1_enabled && !ddr2_enabled)
+ return 0;
+
+ printf("Non-interleaved");
+ return memsize_total * 1024 * 1024;
+
+#endif /* CONFIG_DDR_INTERLEAVE */
+}
+
+
+#endif /* CONFIG_SPD_EEPROM */
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
+
+ dma_init();
+
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) {
+ ppcDcbz((unsigned long) p);
+ }
+ *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
+ if (((unsigned int)p & 0x1c) == 0x1c) {
+ ppcDcbf((unsigned long) p);
+ }
+ }
+
+ dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
+ dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
+ dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
+ dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
+ dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
+ dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
+ dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
+ dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+ dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+ dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
+ }
+
+ /*
+ * Enable errors for ECC.
+ */
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
+ ddr1->err_disable = 0x00000000;
+ asm volatile("sync;isync");
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
+}
+
+#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+#include <asm/processor.h>
+
+
+void get_sys_info(sys_info_t *sysInfo)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint plat_ratio, e600_ratio;
+
+ plat_ratio = (gur->porpllsr) & 0x0000003e;
+ plat_ratio >>= 1;
+
+ switch (plat_ratio) {
+ case 0x0:
+ sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
+ break;
+ case 0x02:
+ case 0x03:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x08:
+ case 0x09:
+ case 0x0a:
+ case 0x0c:
+ case 0x10:
+ sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ break;
+ default:
+ sysInfo->freqSystemBus = 0;
+ break;
+ }
+
+ e600_ratio = (gur->porpllsr) & 0x003f0000;
+ e600_ratio >>= 16;
+
+ switch (e600_ratio) {
+ case 0x10:
+ sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
+ break;
+ case 0x19:
+ sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2;
+ break;
+ case 0x20:
+ sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
+ break;
+ case 0x39:
+ sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2;
+ break;
+ case 0x28:
+ sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
+ break;
+ case 0x1d:
+ sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2;
+ break;
+ default:
+ sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
+ break;
+ }
+}
+
+
+/*
+ * Measure CPU clock speed (core clock GCLK1, GCLK2)
+ * (Approx. GCLK frequency in Hz)
+ */
+
+int get_clocks(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+ gd->cpu_clk = sys_info.freqProcessor;
+ gd->bus_clk = sys_info.freqSystemBus;
+
+ if (gd->cpu_clk != 0)
+ return 0;
+ else
+ return 1;
+}
+
+
+/*
+ * get_bus_freq
+ * Return system bus freq in Hz
+ */
+
+ulong get_bus_freq(ulong dummy)
+{
+ ulong val;
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+ val = sys_info.freqSystemBus;
+
+ return val;
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
+ *
+ *
+ * The processor starts at 0xfff00100 and the code is executed
+ * from flash. The code is organized to be at an other address
+ * in memory, but as long we don't jump around before relocating.
+ * board_init lies at a quite high address and when the cpu has
+ * jumped there, everything is ok.
+ */
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+/* We don't want the MMU yet.
+*/
+#undef MSR_KERNEL
+/* Machine Check and Recoverable Interr. */
+#define MSR_KERNEL ( MSR_ME | MSR_RI )
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+ START_GOT
+ GOT_ENTRY(_GOT2_TABLE_)
+ GOT_ENTRY(_FIXUP_TABLE_)
+
+ GOT_ENTRY(_start)
+ GOT_ENTRY(_start_of_vectors)
+ GOT_ENTRY(_end_of_vectors)
+ GOT_ENTRY(transfer_to_handler)
+
+ GOT_ENTRY(__init_end)
+ GOT_ENTRY(_end)
+ GOT_ENTRY(__bss_start)
+ END_GOT
+
+/*
+ * r3 - 1st arg to board_init(): IMMP pointer
+ * r4 - 2nd arg to board_init(): boot flag
+ */
+ .text
+ .long 0x27051956 /* U-Boot Magic Number */
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+
+ . = EXC_OFF_SYS_RESET
+ .globl _start
+_start:
+ li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
+ b boot_cold
+ sync
+
+ . = EXC_OFF_SYS_RESET + 0x10
+
+ .globl _start_warm
+_start_warm:
+ li r21, BOOTFLAG_WARM /* Software reboot */
+ b boot_warm
+ sync
+
+ /* the boot code is located below the exception table */
+
+ .globl _start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+ STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+ STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+ STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+ STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+ . = 0x600
+Alignment:
+ EXCEPTION_PROLOG
+ mfspr r4,DAR
+ stw r4,_DAR(r21)
+ mfspr r5,DSISR
+ stw r5,_DSISR(r21)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_Alignment:
+ .long AlignmentException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+/* Program check exception */
+ . = 0x700
+ProgramCheck:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_ProgramCheck:
+ .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+ STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+ /* I guess we could implement decrementer, and may have
+ * to someday for timekeeping.
+ */
+ STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+ STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+ STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+ STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+ STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+ STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+ STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+ STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
+ STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
+ STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
+ STD_EXCEPTION(0x1500, Reserved5, UnknownException)
+ STD_EXCEPTION(0x1600, Reserved6, UnknownException)
+ STD_EXCEPTION(0x1700, Reserved7, UnknownException)
+ STD_EXCEPTION(0x1800, Reserved8, UnknownException)
+ STD_EXCEPTION(0x1900, Reserved9, UnknownException)
+ STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
+ STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
+ STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
+
+ .globl _end_of_vectors
+_end_of_vectors:
+
+ . = 0x2000
+
+boot_cold:
+boot_warm:
+
+ /* if this is a multi-core system we need to check which cpu
+ * this is, if it is not cpu 0 send the cpu to the linux reset
+ * vector */
+#if (CONFIG_NUM_CPUS > 1)
+ mfspr r0, MSSCR0
+ andi. r0, r0, 0x0020
+ rlwinm r0,r0,27,31,31
+ mtspr PIR, r0
+ beq 1f
+
+ bl secondary_cpu_setup
+#endif
+
+ /* disable everything */
+1: li r0, 0
+ mtspr HID0, r0
+ sync
+ mtmsr 0
+ bl invalidate_bats
+ sync
+
+#ifdef CFG_L2
+ /* init the L2 cache */
+ addis r3, r0, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ mtspr l2cr, r3
+ /* invalidate the L2 cache */
+ bl l2cache_invalidate
+ sync
+#endif
+
+ /*
+ * Calculate absolute address in FLASH and jump there
+ *------------------------------------------------------*/
+ lis r3, CFG_MONITOR_BASE@h
+ ori r3, r3, CFG_MONITOR_BASE@l
+ addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+ mtlr r3
+ blr
+
+in_flash:
+ /* let the C-code set up the rest */
+ /* */
+ /* Be careful to keep code relocatable ! */
+ /*------------------------------------------------------*/
+ /* perform low-level init */
+
+ /* enable extended addressing */
+ bl enable_ext_addr
+
+ /* setup the bats */
+ bl setup_bats
+ sync
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /* setup ccsrbar */
+ bl setup_ccsrbar
+#endif
+
+ /* Fix for SMP linux - Changing arbitration to round-robin */
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x1000
+ xor r4, r4, r4
+ li r4, 0x1000
+ stw r4, 0(r3)
+
+ /* setup the law entries */
+ bl law_entry
+ sync
+
+ /* Don't use this feature due to bug in 8641D PD4 */
+ /* Disable ERD_DIS */
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x1008
+ lwz r4, 0(r3)
+ oris r4, r4, 0x4000
+ stw r4, 0(r3)
+ sync
+
+#if (EMULATOR_RUN == 1)
+ /* On the emulator we want to adjust these ASAP */
+ /* otherwise things are sloooow */
+ /* Setup OR0 (LALE FIX)*/
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x5004
+ li r4, 0x0FF3
+ stw r4, 0(r3)
+ sync
+
+ /* Setup LCRR */
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x50D4
+ lis r4, 0x8000
+ ori r4, r4, 0x0002
+ stw r4, 0(r3)
+ sync
+#endif
+#if 1
+ /* make sure timer enabled in guts register too */
+ lis r3, CFG_CCSRBAR@h
+ oris r3,r3, 0xE
+ ori r3,r3,0x0070
+ lwz r4, 0(r3)
+ lis r5,0xFFFC
+ ori r5,r5,0x5FFF
+ and r4,r4,r5
+ stw r4,0(r3)
+#endif
+ /*
+ * Cache must be enabled here for stack-in-cache trick.
+ * This means we need to enable the BATS.
+ * Cache should be turned on after BATs, since by default
+ * everything is write-through.
+ */
+
+ /* enable address translation */
+ bl enable_addr_trans
+ sync
+
+ /* enable and invalidate the data cache */
+/* bl l1dcache_enable */
+ bl dcache_enable
+ sync
+
+#if 1
+ bl icache_enable
+#endif
+
+#ifdef CFG_INIT_RAM_LOCK
+ bl lock_ram_in_cache
+ sync
+#endif
+
+ /* set up the stack pointer in our newly created
+ * cache-ram (r1) */
+ lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+
+ li r0, 0 /* Make room for stack frame header and */
+ stwu r0, -4(r1) /* clear final stack frame so that */
+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+
+ GET_GOT /* initialize GOT access */
+
+ /* run low-level CPU init code (from Flash) */
+ bl cpu_init_f
+ sync
+
+#ifdef RUN_DIAG
+
+ /* Sri: Code to run the diagnostic automatically */
+
+ /* Load PX_AUX register address in r4 */
+ lis r4, 0xf810
+ ori r4, r4, 0x6
+ /* Load contents of PX_AUX in r3 bits 24 to 31*/
+ lbz r3, 0(r4)
+
+ /* Mask and obtain the bit in r3 */
+ rlwinm. r3, r3, 0, 24, 24
+ /* If not zero, jump and continue with u-boot */
+ bne diag_done
+
+ /* Load back contents of PX_AUX in r3 bits 24 to 31 */
+ lbz r3, 0(r4)
+ /* Set the MSB of the register value */
+ ori r3, r3, 0x80
+ /* Write value in r3 back to PX_AUX */
+ stb r3, 0(r4)
+
+ /* Get the address to jump to in r3*/
+ lis r3, CFG_DIAG_ADDR@h
+ ori r3, r3, CFG_DIAG_ADDR@l
+
+ /* Load the LR with the branch address */
+ mtlr r3
+
+ /* Branch to diagnostic */
+ blr
+
+diag_done:
+#endif
+
+/* bl l2cache_enable */
+ mr r3, r21
+
+ /* r3: BOOTFLAG */
+ /* run 1st part of board init code (from Flash) */
+ bl board_init_f
+ sync
+
+ /* NOTREACHED */
+
+ .globl invalidate_bats
+invalidate_bats:
+
+ /* invalidate BATs */
+ mtspr IBAT0U, r0
+ mtspr IBAT1U, r0
+ mtspr IBAT2U, r0
+ mtspr IBAT3U, r0
+ mtspr IBAT4U, r0
+ mtspr IBAT5U, r0
+ mtspr IBAT6U, r0
+ mtspr IBAT7U, r0
+
+ isync
+ mtspr DBAT0U, r0
+ mtspr DBAT1U, r0
+ mtspr DBAT2U, r0
+ mtspr DBAT3U, r0
+ mtspr DBAT4U, r0
+ mtspr DBAT5U, r0
+ mtspr DBAT6U, r0
+ mtspr DBAT7U, r0
+
+ isync
+ sync
+ blr
+
+
+ /* setup_bats - set them up to some initial state */
+ .globl setup_bats
+setup_bats:
+
+ addis r0, r0, 0x0000
+
+ /* IBAT 0 */
+ addis r4, r0, CFG_IBAT0L@h
+ ori r4, r4, CFG_IBAT0L@l
+ addis r3, r0, CFG_IBAT0U@h
+ ori r3, r3, CFG_IBAT0U@l
+ mtspr IBAT0L, r4
+ mtspr IBAT0U, r3
+ isync
+
+ /* DBAT 0 */
+ addis r4, r0, CFG_DBAT0L@h
+ ori r4, r4, CFG_DBAT0L@l
+ addis r3, r0, CFG_DBAT0U@h
+ ori r3, r3, CFG_DBAT0U@l
+ mtspr DBAT0L, r4
+ mtspr DBAT0U, r3
+ isync
+
+ /* IBAT 1 */
+ addis r4, r0, CFG_IBAT1L@h
+ ori r4, r4, CFG_IBAT1L@l
+ addis r3, r0, CFG_IBAT1U@h
+ ori r3, r3, CFG_IBAT1U@l
+ mtspr IBAT1L, r4
+ mtspr IBAT1U, r3
+ isync
+
+ /* DBAT 1 */
+ addis r4, r0, CFG_DBAT1L@h
+ ori r4, r4, CFG_DBAT1L@l
+ addis r3, r0, CFG_DBAT1U@h
+ ori r3, r3, CFG_DBAT1U@l
+ mtspr DBAT1L, r4
+ mtspr DBAT1U, r3
+ isync
+
+ /* IBAT 2 */
+ addis r4, r0, CFG_IBAT2L@h
+ ori r4, r4, CFG_IBAT2L@l
+ addis r3, r0, CFG_IBAT2U@h
+ ori r3, r3, CFG_IBAT2U@l
+ mtspr IBAT2L, r4
+ mtspr IBAT2U, r3
+ isync
+
+ /* DBAT 2 */
+ addis r4, r0, CFG_DBAT2L@h
+ ori r4, r4, CFG_DBAT2L@l
+ addis r3, r0, CFG_DBAT2U@h
+ ori r3, r3, CFG_DBAT2U@l
+ mtspr DBAT2L, r4
+ mtspr DBAT2U, r3
+ isync
+
+ /* IBAT 3 */
+ addis r4, r0, CFG_IBAT3L@h
+ ori r4, r4, CFG_IBAT3L@l
+ addis r3, r0, CFG_IBAT3U@h
+ ori r3, r3, CFG_IBAT3U@l
+ mtspr IBAT3L, r4
+ mtspr IBAT3U, r3
+ isync
+
+ /* DBAT 3 */
+ addis r4, r0, CFG_DBAT3L@h
+ ori r4, r4, CFG_DBAT3L@l
+ addis r3, r0, CFG_DBAT3U@h
+ ori r3, r3, CFG_DBAT3U@l
+ mtspr DBAT3L, r4
+ mtspr DBAT3U, r3
+ isync
+
+ /* IBAT 4 */
+ addis r4, r0, CFG_IBAT4L@h
+ ori r4, r4, CFG_IBAT4L@l
+ addis r3, r0, CFG_IBAT4U@h
+ ori r3, r3, CFG_IBAT4U@l
+ mtspr IBAT4L, r4
+ mtspr IBAT4U, r3
+ isync
+
+ /* DBAT 4 */
+ addis r4, r0, CFG_DBAT4L@h
+ ori r4, r4, CFG_DBAT4L@l
+ addis r3, r0, CFG_DBAT4U@h
+ ori r3, r3, CFG_DBAT4U@l
+ mtspr DBAT4L, r4
+ mtspr DBAT4U, r3
+ isync
+
+ /* IBAT 5 */
+ addis r4, r0, CFG_IBAT5L@h
+ ori r4, r4, CFG_IBAT5L@l
+ addis r3, r0, CFG_IBAT5U@h
+ ori r3, r3, CFG_IBAT5U@l
+ mtspr IBAT5L, r4
+ mtspr IBAT5U, r3
+ isync
+
+ /* DBAT 5 */
+ addis r4, r0, CFG_DBAT5L@h
+ ori r4, r4, CFG_DBAT5L@l
+ addis r3, r0, CFG_DBAT5U@h
+ ori r3, r3, CFG_DBAT5U@l
+ mtspr DBAT5L, r4
+ mtspr DBAT5U, r3
+ isync
+
+ /* IBAT 6 */
+ addis r4, r0, CFG_IBAT6L@h
+ ori r4, r4, CFG_IBAT6L@l
+ addis r3, r0, CFG_IBAT6U@h
+ ori r3, r3, CFG_IBAT6U@l
+ mtspr IBAT6L, r4
+ mtspr IBAT6U, r3
+ isync
+
+ /* DBAT 6 */
+ addis r4, r0, CFG_DBAT6L@h
+ ori r4, r4, CFG_DBAT6L@l
+ addis r3, r0, CFG_DBAT6U@h
+ ori r3, r3, CFG_DBAT6U@l
+ mtspr DBAT6L, r4
+ mtspr DBAT6U, r3
+ isync
+
+ /* IBAT 7 */
+ addis r4, r0, CFG_IBAT7L@h
+ ori r4, r4, CFG_IBAT7L@l
+ addis r3, r0, CFG_IBAT7U@h
+ ori r3, r3, CFG_IBAT7U@l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
+
+ /* DBAT 7 */
+ addis r4, r0, CFG_DBAT7L@h
+ ori r4, r4, CFG_DBAT7L@l
+ addis r3, r0, CFG_DBAT7U@h
+ ori r3, r3, CFG_DBAT7U@l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
+
+1:
+ addis r3, 0, 0x0000
+ addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
+ isync
+
+tlblp:
+ tlbie r3
+ sync
+ addi r3, r3, 0x1000
+ cmp 0, 0, r3, r5
+ blt tlblp
+
+ blr
+
+ .globl enable_addr_trans
+enable_addr_trans:
+ /* enable address translation */
+ mfmsr r5
+ ori r5, r5, (MSR_IR | MSR_DR)
+ mtmsr r5
+ isync
+ blr
+
+ .globl disable_addr_trans
+disable_addr_trans:
+ /* disable address translation */
+ mflr r4
+ mfmsr r3
+ andi. r0, r3, (MSR_IR | MSR_DR)
+ beqlr
+ andc r3, r3, r0
+ mtspr SRR0, r4
+ mtspr SRR1, r3
+ rfi
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+ .globl transfer_to_handler
+transfer_to_handler:
+ stw r22,_NIP(r21)
+ lis r22,MSR_POW@h
+ andc r23,r23,r22
+ stw r23,_MSR(r21)
+ SAVE_GPR(7, r21)
+ SAVE_4GPRS(8, r21)
+ SAVE_8GPRS(12, r21)
+ SAVE_8GPRS(24, r21)
+ mflr r23
+ andi. r24,r23,0x3f00 /* get vector offset */
+ stw r24,TRAP(r21)
+ li r22,0
+ stw r22,RESULT(r21)
+ mtspr SPRG2,r22 /* r1 is now kernel sp */
+ lwz r24,0(r23) /* virtual address of handler */
+ lwz r23,4(r23) /* where to go when done */
+ mtspr SRR0,r24
+ mtspr SRR1,r20
+ mtlr r23
+ SYNC
+ rfi /* jump to handler, enable MMU */
+
+int_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SRR0,r2
+ mtspr SRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfi
+
+ .globl dc_read
+dc_read:
+ blr
+
+ .globl get_pvr
+get_pvr:
+ mfspr r3, PVR
+ blr
+
+ .globl get_svr
+get_svr:
+ mfspr r3, SVR
+ blr
+
+
+/*
+ * Function: in8
+ * Description: Input 8 bits
+ */
+ .globl in8
+in8:
+ lbz r3,0x0000(r3)
+ blr
+
+/*
+ * Function: out8
+ * Description: Output 8 bits
+ */
+ .globl out8
+out8:
+ stb r4,0x0000(r3)
+ blr
+
+/*
+ * Function: out16
+ * Description: Output 16 bits
+ */
+ .globl out16
+out16:
+ sth r4,0x0000(r3)
+ blr
+
+/*
+ * Function: out16r
+ * Description: Byte reverse and output 16 bits
+ */
+ .globl out16r
+out16r:
+ sthbrx r4,r0,r3
+ blr
+
+/*
+ * Function: out32
+ * Description: Output 32 bits
+ */
+ .globl out32
+out32:
+ stw r4,0x0000(r3)
+ blr
+
+/*
+ * Function: out32r
+ * Description: Byte reverse and output 32 bits
+ */
+ .globl out32r
+out32r:
+ stwbrx r4,r0,r3
+ blr
+
+/*
+ * Function: in16
+ * Description: Input 16 bits
+ */
+ .globl in16
+in16:
+ lhz r3,0x0000(r3)
+ blr
+
+/*
+ * Function: in16r
+ * Description: Input 16 bits and byte reverse
+ */
+ .globl in16r
+in16r:
+ lhbrx r3,r0,r3
+ blr
+
+/*
+ * Function: in32
+ * Description: Input 32 bits
+ */
+ .globl in32
+in32:
+ lwz 3,0x0000(3)
+ blr
+
+/*
+ * Function: in32r
+ * Description: Input 32 bits and byte reverse
+ */
+ .globl in32r
+in32r:
+ lwbrx r3,r0,r3
+ blr
+
+/*
+ * Function: ppcDcbf
+ * Description: Data Cache block flush
+ * Input: r3 = effective address
+ * Output: none.
+ */
+ .globl ppcDcbf
+ppcDcbf:
+ dcbf r0,r3
+ blr
+
+/*
+ * Function: ppcDcbi
+ * Description: Data Cache block Invalidate
+ * Input: r3 = effective address
+ * Output: none.
+ */
+ .globl ppcDcbi
+ppcDcbi:
+ dcbi r0,r3
+ blr
+
+/*
+ * Function: ppcDcbz
+ * Description: Data Cache block zero.
+ * Input: r3 = effective address
+ * Output: none.
+ */
+ .globl ppcDcbz
+ppcDcbz:
+ dcbz r0,r3
+ blr
+
+/*
+ * Function: ppcSync
+ * Description: Processor Synchronize
+ * Input: none.
+ * Output: none.
+ */
+ .globl ppcSync
+ppcSync:
+ sync
+ blr
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+
+ mr r1, r3 /* Set new stack pointer */
+ mr r9, r4 /* Save copy of Global Data pointer */
+ mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
+ mr r10, r5 /* Save copy of Destination Address */
+
+ mr r3, r5 /* Destination Address */
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r5, GOT(__init_end)
+ sub r5, r5, r4
+ li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ *
+ * Offset:
+ */
+ sub r15, r10, r4
+
+ /* First our own GOT */
+ add r14, r14, r15
+ /* then the one used by the C code */
+ add r30, r30, r15
+
+ /*
+ * Now relocate code
+ */
+#ifdef CONFIG_ECC
+ bl board_relocate_rom
+ sync
+ mr r3, r10 /* Destination Address */
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r5, GOT(__init_end)
+ sub r5, r5, r4
+ li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+#else
+ cmplw cr1,r3,r4
+ addi r0,r5,3
+ srwi. r0,r0,2
+ beq cr1,4f /* In place copy is not necessary */
+ beq 7f /* Protect against 0 count */
+ mtctr r0
+ bge cr1,2f
+
+ la r8,-4(r4)
+ la r7,-4(r3)
+1: lwzu r0,4(r8)
+ stwu r0,4(r7)
+ bdnz 1b
+ b 4f
+
+2: slwi r0,r0,2
+ add r8,r4,r0
+ add r7,r3,r0
+3: lwzu r0,-4(r8)
+ stwu r0,-4(r7)
+ bdnz 3b
+#endif
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4: cmpwi r6,0
+ add r5,r3,r5
+ beq 7f /* Always flush prefetch queue in any case */
+ subi r0,r6,1
+ andc r3,r3,r0
+ mr r4,r3
+5: dcbst 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 5b
+ sync /* Wait for all dcbst to complete on bus */
+ mr r4,r3
+6: icbi 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 6b
+7: sync /* Wait for all icbi to complete on bus */
+ isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+ mtlr r0
+ blr
+
+in_ram:
+#ifdef CONFIG_ECC
+ bl board_init_ecc
+#endif
+ /*
+ * Relocation Function, r14 point to got2+0x8000
+ *
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
+ */
+ li r0,__got2_entries@sectoff@l
+ la r3,GOT(_GOT2_TABLE_)
+ lwz r11,GOT(_GOT2_TABLE_)
+ mtctr r0
+ sub r11,r3,r11
+ addi r3,r3,-4
+1: lwzu r0,4(r3)
+ add r0,r0,r11
+ stw r0,0(r3)
+ bdnz 1b
+
+ /*
+ * Now adjust the fixups and the pointers to the fixups
+ * in case we need to move ourselves again.
+ */
+2: li r0,__fixup_entries@sectoff@l
+ lwz r3,GOT(_FIXUP_TABLE_)
+ cmpwi r0,0
+ mtctr r0
+ addi r3,r3,-4
+ beq 4f
+3: lwzu r4,4(r3)
+ lwzux r0,r4,r11
+ add r0,r0,r11
+ stw r10,0(r3)
+ stw r0,0(r4)
+ bdnz 3b
+4:
+/* clear_bss: */
+ /*
+ * Now clear BSS segment
+ */
+ lwz r3,GOT(__bss_start)
+ lwz r4,GOT(_end)
+
+ cmplw 0, r3, r4
+ beq 6f
+
+ li r0, 0
+5:
+ stw r0, 0(r3)
+ addi r3, r3, 4
+ cmplw 0, r3, r4
+ bne 5b
+6:
+ mr r3, r9 /* Init Date pointer */
+ mr r4, r10 /* Destination Address */
+ bl board_init_r
+
+ /* not reached - end relocate_code */
+/*-----------------------------------------------------------------------*/
+
+ /*
+ * Copy exception vector code to low memory
+ *
+ * r3: dest_addr
+ * r7: source address, r8: end address, r9: target address
+ */
+ .globl trap_init
+trap_init:
+ lwz r7, GOT(_start)
+ lwz r8, GOT(_end_of_vectors)
+
+ li r9, 0x100 /* reset vector always at 0x100 */
+
+ cmplw 0, r7, r8
+ bgelr /* return if r7>=r8 - just in case */
+
+ mflr r4 /* save link register */
+1:
+ lwz r0, 0(r7)
+ stw r0, 0(r9)
+ addi r7, r7, 4
+ addi r9, r9, 4
+ cmplw 0, r7, r8
+ bne 1b
+
+ /*
+ * relocate `hdlr' and `int_return' entries
+ */
+ li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+ li r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 2b
+
+ li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+ li r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 3b
+
+ li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+ li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 4b
+
+ /* enable execptions from RAM vectors */
+ mfmsr r7
+ li r8,MSR_IP
+ andc r7,r7,r8
+ mtmsr r7
+
+ mtlr r4 /* restore link register */
+ blr
+
+ /*
+ * Function: relocate entries for one exception vector
+ */
+trap_reloc:
+ lwz r0, 0(r7) /* hdlr ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 0(r7)
+
+ lwz r0, 4(r7) /* int_return ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 4(r7)
+
+ sync
+ isync
+
+ blr
+
+.globl enable_ext_addr
+enable_ext_addr:
+ mfspr r0, HID0
+ lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
+ ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
+ mtspr HID0, r0
+ sync
+ isync
+ blr
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+.globl setup_ccsrbar
+setup_ccsrbar:
+ /* Special sequence needed to update CCSRBAR itself */
+ lis r4, CFG_CCSRBAR_DEFAULT@h
+ ori r4, r4, CFG_CCSRBAR_DEFAULT@l
+
+ lis r5, CFG_CCSRBAR@h
+ ori r5, r5, CFG_CCSRBAR@l
+ srwi r6,r5,12
+ stw r6, 0(r4)
+ isync
+
+ lis r5, 0xffff
+ ori r5,r5,0xf000
+ lwz r5, 0(r5)
+ isync
+
+ lis r3, CFG_CCSRBAR@h
+ lwz r5, CFG_CCSRBAR@l(r3)
+ isync
+
+ blr
+#endif
+
+#ifdef CFG_INIT_RAM_LOCK
+lock_ram_in_cache:
+ /* Allocate Initial RAM in data cache.
+ */
+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+ li r2, ((CFG_INIT_RAM_END & ~31) + \
+ (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r2
+1:
+ dcbz r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+#if 1
+/* Lock the data cache */
+ mfspr r0, HID0
+ ori r0, r0, 0x1000
+ sync
+ mtspr HID0, r0
+ sync
+ blr
+#endif
+#if 0
+ /* Lock the first way of the data cache */
+ mfspr r0, LDSTCR
+ ori r0, r0, 0x0080
+#if defined(CONFIG_ALTIVEC)
+ dssall
+#endif
+ sync
+ mtspr LDSTCR, r0
+ sync
+ isync
+ blr
+#endif
+
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+ /* invalidate the INIT_RAM section */
+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+ li r2, ((CFG_INIT_RAM_END & ~31) + \
+ (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r2
+1: icbi r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+ sync /* Wait for all icbi to complete on bus */
+ isync
+#if 1
+/* Unlock the data cache and invalidate it */
+ mfspr r0, HID0
+ li r3,0x1000
+ andc r0,r0,r3
+ li r3,0x0400
+ or r0,r0,r3
+ sync
+ mtspr HID0, r0
+ sync
+ blr
+#endif
+#if 0
+ /* Unlock the first way of the data cache */
+ mfspr r0, LDSTCR
+ li r3,0x0080
+ andc r0,r0,r3
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ sync
+ mtspr LDSTCR, r0
+ sync
+ isync
+ li r3,0x0400
+ or r0,r0,r3
+ sync
+ mtspr HID0, r0
+ sync
+ blr
+#endif
+#endif
+
+/* If this is a multi-cpu system then we need to handle the
+ * 2nd cpu. The assumption is that the 2nd cpu is being
+ * held in boot holdoff mode until the 1st cpu unlocks it
+ * from Linux. We'll do some basic cpu init and then pass
+ * it to the Linux Reset Vector.
+ * Sri: Much of this initialization is not required. Linux
+ * rewrites the bats, and the sprs and also enables the L1 cache.
+ */
+#if (CONFIG_NUM_CPUS > 1)
+.globl secondary_cpu_setup
+secondary_cpu_setup:
+ /* Do only core setup on all cores except cpu0 */
+ bl invalidate_bats
+ sync
+ bl enable_ext_addr
+
+#ifdef CFG_L2
+ /* init the L2 cache */
+ addis r3, r0, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ sync
+ mtspr l2cr, r3
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ /* invalidate the L2 cache */
+ bl l2cache_invalidate
+ sync
+#endif
+
+ /* enable and invalidate the data cache */
+ bl dcache_enable
+ sync
+
+ /* enable and invalidate the instruction cache*/
+ bl icache_enable
+ sync
+
+ /* TBEN in HID0 */
+ mfspr r4, HID0
+ oris r4, r4, 0x0400
+ mtspr HID0, r4
+ sync
+ isync
+
+ /*SYNCBE|ABE in HID1*/
+ mfspr r4, HID1
+ ori r4, r4, 0x0C00
+ mtspr HID1, r4
+ sync
+ isync
+
+ lis r3, CONFIG_LINUX_RESET_VEC@h
+ ori r3, r3, CONFIG_LINUX_RESET_VEC@l
+ mtlr r3
+ blr
+
+ /* Never Returns, Running in Linux Now */
+#endif
--- /dev/null
+/*
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+int (*debugger_exception_handler)(struct pt_regs *) = 0;
+#endif
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern unsigned long search_exception_table(unsigned long);
+
+#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+
+/*
+ * Trap & Exception support
+ */
+
+void
+print_backtrace(unsigned long *sp)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int cnt = 0;
+ unsigned long i;
+
+ printf("Call backtrace: ");
+ while (sp) {
+ if ((uint) sp > END_OF_MEM)
+ break;
+
+ i = sp[1];
+ if (cnt++ % 7 == 0)
+ printf("\n");
+ printf("%08lX ", i);
+ if (cnt > 32)
+ break;
+ sp = (unsigned long *)*sp;
+ }
+ printf("\n");
+}
+
+void
+show_regs(struct pt_regs *regs)
+{
+ int i;
+
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS:"
+ " %p TRAP: %04lx DAR: %08lX\n",
+ regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+ printf("MSR: %08lx EE: %01x PR: %01x FP:"
+ " %01x ME: %01x IR/DR: %01x%01x\n",
+ regs->msr, regs->msr & MSR_EE ? 1 : 0,
+ regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
+ regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
+ regs->msr & MSR_DR ? 1 : 0);
+
+ printf("\n");
+ for (i = 0; i < 32; i++) {
+ if ((i % 8) == 0) {
+ printf("GPR%02d: ", i);
+ }
+
+ printf("%08lX ", regs->gpr[i]);
+ if ((i % 8) == 7) {
+ printf("\n");
+ }
+ }
+}
+
+
+void
+_exception(int signr, struct pt_regs *regs)
+{
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
+}
+
+void
+MachineCheckException(struct pt_regs *regs)
+{
+ unsigned long fixup;
+
+ /* Probing PCI using config cycles cause this exception
+ * when a device is not present. Catch it and return to
+ * the PCI exception handler.
+ */
+ if ((fixup = search_exception_table(regs->nip)) != 0) {
+ regs->nip = fixup;
+ return;
+ }
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+
+ printf("Machine check in kernel mode.\n");
+ printf("Caused by (from msr): ");
+ printf("regs %p ", regs);
+ switch (regs->msr & 0x000F0000) {
+ case (0x80000000 >> 12):
+ printf("Machine check signal - probably due to mm fault\n"
+ "with mmu off\n");
+ break;
+ case (0x80000000 >> 13):
+ printf("Transfer error ack signal\n");
+ break;
+ case (0x80000000 >> 14):
+ printf("Data parity signal\n");
+ break;
+ case (0x80000000 >> 15):
+ printf("Address parity signal\n");
+ break;
+ default:
+ printf("Unknown values in msr\n");
+ }
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("machine check");
+}
+
+void
+AlignmentException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Alignment Exception");
+}
+
+void
+ProgramCheckException(struct pt_regs *regs)
+{
+ unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
+ int i, j;
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ show_regs(regs);
+
+ p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0);
+ p -= 32;
+ for (i = 0; i < 256; i += 16) {
+ printf("%08x: ", (unsigned int)p + i);
+ for (j = 0; j < 16; j++) {
+ printf("%02x ", p[i + j]);
+ }
+ printf("\n");
+ }
+
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Program Check Exception");
+}
+
+void
+SoftEmuException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Software Emulation Exception");
+}
+
+void
+UnknownException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ regs->nip, regs->msr, regs->trap);
+ _exception(0, regs);
+}
+
+/*
+ * Probe an address by reading.
+ * If not present, return -1,
+ * otherwise return 0.
+ */
+int
+addr_probe(uint *addr)
+{
+ return 0;
+}
char buf[32];
#if !defined(CONFIG_IOP480)
+ char addstr[64] = "";
sys_info_t sys_info;
puts ("CPU: ");
#endif /* CONFIG_440 */
case PVR_440EPX1_RA:
- puts("EPx Rev. A - Security/Kasumi support");
+ puts("EPx Rev. A");
+ strcpy(addstr, "Security/Kasumi support");
break;
case PVR_440EPX2_RA:
- puts("EPx Rev. A - No Security/Kasumi support");
+ puts("EPx Rev. A");
+ strcpy(addstr, "No Security/Kasumi support");
break;
case PVR_440GRX1_RA:
- puts("GRx Rev. A - Security/Kasumi support");
+ puts("GRx Rev. A");
+ strcpy(addstr, "Security/Kasumi support");
break;
case PVR_440GRX2_RA:
- puts("GRx Rev. A - No Security/Kasumi support");
+ puts("GRx Rev. A");
+ strcpy(addstr, "No Security/Kasumi support");
break;
case PVR_440SP_RA:
sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
FREQ_EBC / 1000000);
+ if (addstr[0] != 0)
+ printf(" %s\n", addstr);
+
#if defined(I2C_BOOTROM)
printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#if defined(SDR0_PINSTP_SHIFT)
printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
-#endif
-#endif
+#endif /* SDR0_PINSTP_SHIFT */
+#endif /* I2C_BOOTROM */
#if defined(CONFIG_PCI)
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
if (hwctl & 0x1)
out8(base + NDFC_CMD, byte);
static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
return (in8(base + NDFC_DATA));
}
static int ndfc_dev_ready(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
;
static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
uint32_t *p = (uint32_t *) buf;
- for(;len > 0; len -= 4)
+ for (;len > 0; len -= 4)
*p++ = in32(base + NDFC_DATA);
}
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
uint32_t *p = (uint32_t *) buf;
- for(; len > 0; len -= 4)
+ for (; len > 0; len -= 4)
out32(base + NDFC_DATA, *p++);
}
static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
uint32_t *p = (uint32_t *) buf;
- for(; len > 0; len -= 4)
+ for (; len > 0; len -= 4)
if (*p++ != in32(base + NDFC_DATA))
return -1;
}
#endif /* #ifndef CONFIG_NAND_SPL */
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+ /*
+ * Don't use "chip" to address the NAND device,
+ * generate the cs from the address where it is encoded.
+ */
+ int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
+ ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
+
+ /* Set NandFlash Core Configuration Register */
+ /* 1col x 2 rows */
+ out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
+}
+
void board_nand_init(struct nand_chip *nand)
{
+ int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
+ ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
+
nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = ndfc_hwcontrol;
mtebc(pb0ap, CFG_EBC_PB0AP);
#endif
- /* Set NandFlash Core Configuration Register */
- /* Chip select 3, 1col x 2 rows */
- out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24));
- out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222);
+ /*
+ * Select required NAND chip in NDFC
+ */
+ board_nand_select_device(nand, cs);
+ out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
}
#endif
--- /dev/null
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed, 30 Aug 2006 17:01:46 +0200
+Subject: [PATCH] AVR32 architecture support
+
+This patch adds common infrastructure code for the Atmel AVR32
+architecture.
+
+AVR32 is a new high-performance 32-bit RISC microprocessor core,
+designed for cost-sensitive embedded applications, with particular
+emphasis on low power consumption and high code density. The AVR32
+architecture is not binary compatible with earlier 8-bit AVR
+architectures.
+
+The AVR32 architecture, including the instruction set, is described
+by the AVR32 Architecture Manual, available from
+
+http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
+
+A GNU toolchain with support for AVR32 is included with the ATSTK1000
+BSP, which can be downloaded as an ISO image from
+
+http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
+
+Alternatively, you can build it yourself by following the
+Getting Started guide at avr32linux.org, which also provides links
+to the necessary sources and patches you need to download:
+
+http://avr32linux.org/twiki/bin/view/Main/GettingStarted
+
+The AVR32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Atmel Corporation.
+
+Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
+ In order to use PCI-X (only in the first PCI slot. The one with
+ the RIO connector), you need to set SW1[4] (config) to 1 (off).
+ Also, configure the board to run PCI at 66 MHz.
2. MEMORY MAP TO WORK WITH LINUX KERNEL
--- /dev/null
+Freescale MPC8641HPCN board
+===========================
+
+Created 05/24/2006 Haiying Wang
+-------------------------------
+
+1. Building U-Boot
+------------------
+The 86xx HPCN code base is known to compile using:
+ Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+
+ $ make MPC8641HPCN_config
+ Configuring for MPC8641HPCN board...
+
+ $ make
+
+
+2. Switch and Jumper Setting
+----------------------------
+Jumpers:
+ J14 Pins 1-2 (near plcc32 socket)
+
+Switches:
+ SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1
+ 01100 :: CORE = 2.5:1
+ 10000 :: CORE = 3:1
+ 11100 :: CORE = 3.5:1
+ 10100 :: CORE = 4:1
+ 01110 :: CORE = 4.5:1
+ SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz
+ 001 :: SYSCLK = 40MHz
+
+ SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X
+ 0100 :: 4X
+ 0110 :: 6X
+ 1000 :: 8X
+ 1010 :: 10X
+ 1100 :: 12X
+ 1110 :: 14X
+ 0000 :: 16X
+ SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus
+
+ SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V
+ 0100000 :: VCORE = 1.11V
+ SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
+ 1 :: VCC_PLAT = 1.0V
+
+ SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root
+ SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq
+ SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX
+
+ SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash
+ 0 :: boot from PromJet
+ SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower
+ halves (virtual banks)
+ 0 :: normal
+ SW5(3) = 0 CFG_FLASHWP = 0 :: not protected
+ SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4
+ 1:1 for PD6
+ SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined
+ SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined
+
+ SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff
+ SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation
+ SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ
+ SW6(6) = 1 CFG_SERROM_ADDR= 1 ::
+ SW6(7) = 1 CFG_MEMDEBUG = 1 ::
+ SW6(8) = 1 CFG_DDRDEBUG = 1 ::
+
+ SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
+ SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
+ SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
+ SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
+ SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
+ SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
+ SW8(7) = 1 ACPWR = 1 :: non-battery
+ SW8(8) = 0 CFG_IDWP = 0 :: write enable
+
+
+3. Flash U-Boot
+---------------
+The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
+It is possible to use either half to boot using u-boot. Switch 5 bit 2
+is used for this purpose.
+
+0xFF800000 to 0xFFBFFFFF - 4MB
+0xFFC00000 to 0xFFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xFFF00000.
+When this bit is 1, U-Boot is at 0xFFB00000.
+
+Use the above mentioned flash commands to program the other half, and
+use switch 5, bit 2 to alternate between the halves. Note: The booting
+version of U-Boot will always be at 0xFFF00000.
+
+To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase fff00000 ffffffff
+ cp.b 1000000 fff00100 80000
+
+To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
+
+ tftp 1000000 u-boot.bin
+ erase ffb00000 ffbfffff
+ cp.b 1000000 ffb00100 80000
+
+
+4. Memory Map
+-------------
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
+ 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
+ 0xf800_0000 0xf80f_ffff CCSR 1M
+ 0xf810_0000 0xf81f_ffff PIXIS 1M
+ 0xf840_0000 0xf840_3fff Stack space 32K
+ 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M
+ 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
+ 0xfe00_0000 0xfeff_ffff Flash(alternate)16M
+ 0xff00_0000 0xffff_ffff Flash(boot bank)16M
NAND FLASH commands and notes
-
See NOTE below!!!
-
# (C) Copyright 2003
# Dave Ellis, SIXNET, dge@sixnetio.com
#
with DoC will break).
-
Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
JFFS2 related commands:
LIB = $(obj)libdrivers.a
-COBJS = 3c589.o 5701rls.o ali512x.o \
+COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o \
serial.o serial_max3100.o \
serial_pl010.o serial_pl011.o serial_xuartlite.o \
sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
- status_led.o sym53c8xx.o \
+ status_led.o sym53c8xx.o ahci.o \
ti_pci1410a.o tigon3.o tsec.o \
usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
videomodes.o w83c553f.o \
ks8695eth.o \
pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
- rpx_pcmcia.o
+ rpx_pcmcia.o \
+ fsl_i2c.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ * Zhang Wei<wei.zhang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * with the reference on libata and ahci drvier in kernel
+ *
+ */
+#include <common.h>
+
+#ifdef CONFIG_SCSI_AHCI
+
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <scsi.h>
+#include <ata.h>
+#include <linux/ctype.h>
+#include <ahci.h>
+
+struct ahci_probe_ent *probe_ent = NULL;
+hd_driveid_t *ataid[AHCI_MAX_PORTS];
+
+#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
+
+
+static inline u32 ahci_port_base(u32 base, u32 port)
+{
+ return base + 0x100 + (port * 0x80);
+}
+
+
+static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
+ unsigned int port_idx)
+{
+ base = ahci_port_base(base, port_idx);
+
+ port->cmd_addr = base;
+ port->scr_addr = base + PORT_SCR;
+}
+
+
+#define msleep(a) udelay(a * 1000)
+#define ssleep(a) msleep(a * 1000)
+
+static int waiting_for_cmd_completed(volatile u8 *offset,
+ int timeout_msec,
+ u32 sign)
+{
+ int i;
+ u32 status;
+
+ for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
+ msleep(1);
+
+ return (i < timeout_msec) ? 0 : -1;
+}
+
+
+static int ahci_host_init(struct ahci_probe_ent *probe_ent)
+{
+ pci_dev_t pdev = probe_ent->dev;
+ volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
+ u32 tmp, cap_save;
+ u16 tmp16;
+ int i, j;
+ volatile u8 *port_mmio;
+ unsigned short vendor;
+
+ cap_save = readl(mmio + HOST_CAP);
+ cap_save &= ((1 << 28) | (1 << 17));
+ cap_save |= (1 << 27);
+
+ /* global controller reset */
+ tmp = readl(mmio + HOST_CTL);
+ if ((tmp & HOST_RESET) == 0)
+ writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
+
+ /* reset must complete within 1 second, or
+ * the hardware should be considered fried.
+ */
+ ssleep(1);
+
+ tmp = readl(mmio + HOST_CTL);
+ if (tmp & HOST_RESET) {
+ debug("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+
+ writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
+ writel(cap_save, mmio + HOST_CAP);
+ writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
+
+ pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+
+ if (vendor == PCI_VENDOR_ID_INTEL) {
+ u16 tmp16;
+ pci_read_config_word(pdev, 0x92, &tmp16);
+ tmp16 |= 0xf;
+ pci_write_config_word(pdev, 0x92, tmp16);
+ }
+
+ probe_ent->cap = readl(mmio + HOST_CAP);
+ probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
+ probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
+
+ debug("cap 0x%x port_map 0x%x n_ports %d\n",
+ probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
+
+ for (i = 0; i < probe_ent->n_ports; i++) {
+ probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
+ port_mmio = (u8 *) probe_ent->port[i].port_mmio;
+ ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
+
+ /* make sure port is not active */
+ tmp = readl(port_mmio + PORT_CMD);
+ if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
+ PORT_CMD_FIS_RX | PORT_CMD_START)) {
+ tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
+ PORT_CMD_FIS_RX | PORT_CMD_START);
+ writel_with_flush(tmp, port_mmio + PORT_CMD);
+
+ /* spec says 500 msecs for each bit, so
+ * this is slightly incorrect.
+ */
+ msleep(500);
+ }
+
+ writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
+
+ j = 0;
+ while (j < 100) {
+ msleep(10);
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ if ((tmp & 0xf) == 0x3)
+ break;
+ j++;
+ }
+
+ tmp = readl(port_mmio + PORT_SCR_ERR);
+ debug("PORT_SCR_ERR 0x%x\n", tmp);
+ writel(tmp, port_mmio + PORT_SCR_ERR);
+
+ /* ack any pending irq events for this port */
+ tmp = readl(port_mmio + PORT_IRQ_STAT);
+ debug("PORT_IRQ_STAT 0x%x\n", tmp);
+ if (tmp)
+ writel(tmp, port_mmio + PORT_IRQ_STAT);
+
+ writel(1 << i, mmio + HOST_IRQ_STAT);
+
+ /* set irq mask (enables interrupts) */
+ writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
+
+ /*register linkup ports */
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ debug("Port %d status: 0x%x\n", i, tmp);
+ if ((tmp & 0xf) == 0x03)
+ probe_ent->link_port_map |= (0x01 << i);
+ }
+
+ tmp = readl(mmio + HOST_CTL);
+ debug("HOST_CTL 0x%x\n", tmp);
+ writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
+ tmp = readl(mmio + HOST_CTL);
+ debug("HOST_CTL 0x%x\n", tmp);
+
+ pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
+ tmp |= PCI_COMMAND_MASTER;
+ pci_write_config_word(pdev, PCI_COMMAND, tmp16);
+
+ return 0;
+}
+
+
+static void ahci_print_info(struct ahci_probe_ent *probe_ent)
+{
+ pci_dev_t pdev = probe_ent->dev;
+ volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
+ u32 vers, cap, impl, speed;
+ const char *speed_s;
+ u16 cc;
+ const char *scc_s;
+
+ vers = readl(mmio + HOST_VERSION);
+ cap = probe_ent->cap;
+ impl = probe_ent->port_map;
+
+ speed = (cap >> 20) & 0xf;
+ if (speed == 1)
+ speed_s = "1.5";
+ else if (speed == 2)
+ speed_s = "3";
+ else
+ speed_s = "?";
+
+ pci_read_config_word(pdev, 0x0a, &cc);
+ if (cc == 0x0101)
+ scc_s = "IDE";
+ else if (cc == 0x0106)
+ scc_s = "SATA";
+ else if (cc == 0x0104)
+ scc_s = "RAID";
+ else
+ scc_s = "unknown";
+
+ printf("AHCI %02x%02x.%02x%02x "
+ "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
+ (vers >> 24) & 0xff,
+ (vers >> 16) & 0xff,
+ (vers >> 8) & 0xff,
+ vers & 0xff,
+ ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
+
+ printf("flags: "
+ "%s%s%s%s%s%s"
+ "%s%s%s%s%s%s%s\n",
+ cap & (1 << 31) ? "64bit " : "",
+ cap & (1 << 30) ? "ncq " : "",
+ cap & (1 << 28) ? "ilck " : "",
+ cap & (1 << 27) ? "stag " : "",
+ cap & (1 << 26) ? "pm " : "",
+ cap & (1 << 25) ? "led " : "",
+ cap & (1 << 24) ? "clo " : "",
+ cap & (1 << 19) ? "nz " : "",
+ cap & (1 << 18) ? "only " : "",
+ cap & (1 << 17) ? "pmp " : "",
+ cap & (1 << 15) ? "pio " : "",
+ cap & (1 << 14) ? "slum " : "",
+ cap & (1 << 13) ? "part " : "");
+}
+
+static int ahci_init_one(pci_dev_t pdev)
+{
+ u32 iobase, vendor;
+ int rc;
+
+ memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
+
+ probe_ent = malloc(sizeof(probe_ent));
+ memset(probe_ent, 0, sizeof(probe_ent));
+ probe_ent->dev = pdev;
+
+ pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
+ iobase &= ~0xf;
+
+ probe_ent->host_flags = ATA_FLAG_SATA
+ | ATA_FLAG_NO_LEGACY
+ | ATA_FLAG_MMIO
+ | ATA_FLAG_PIO_DMA
+ | ATA_FLAG_NO_ATAPI;
+ probe_ent->pio_mask = 0x1f;
+ probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
+
+ probe_ent->mmio_base = iobase;
+
+ /* Take from kernel:
+ * JMicron-specific fixup:
+ * make sure we're in AHCI mode
+ */
+ pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+ if (vendor == 0x197b)
+ pci_write_config_byte(pdev, 0x41, 0xa1);
+
+ /* initialize adapter */
+ rc = ahci_host_init(probe_ent);
+ if (rc)
+ goto err_out;
+
+ ahci_print_info(probe_ent);
+
+ return 0;
+
+ err_out:
+ return rc;
+}
+
+
+#define MAX_DATA_BYTE_COUNT (4*1024*1024)
+
+static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
+{
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+ u32 sg_count;
+ int i;
+
+ sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
+ if (sg_count > AHCI_MAX_SG) {
+ printf("Error:Too much sg!\n");
+ return -1;
+ }
+
+ for (i = 0; i < sg_count; i++) {
+ ahci_sg->addr =
+ cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
+ ahci_sg->addr_hi = 0;
+ ahci_sg->flags_size = cpu_to_le32(0x3fffff &
+ (buf_len < MAX_DATA_BYTE_COUNT
+ ? (buf_len - 1)
+ : (MAX_DATA_BYTE_COUNT - 1)));
+ ahci_sg++;
+ buf_len -= MAX_DATA_BYTE_COUNT;
+ }
+
+ return sg_count;
+}
+
+
+static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
+{
+ pp->cmd_slot->opts = cpu_to_le32(opts);
+ pp->cmd_slot->status = 0;
+ pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
+ pp->cmd_slot->tbl_addr_hi = 0;
+}
+
+
+static void ahci_set_feature(u8 port)
+{
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 cmd_fis_len = 5; /* five dwords */
+ u8 fis[20];
+
+ /*set feature */
+ memset(fis, 0, 20);
+ fis[0] = 0x27;
+ fis[1] = 1 << 7;
+ fis[2] = ATA_CMD_SETF;
+ fis[3] = SETFEATURES_XFER;
+ fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
+
+ memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
+ ahci_fill_cmd_slot(pp, cmd_fis_len);
+ writel(1, port_mmio + PORT_CMD_ISSUE);
+ readl(port_mmio + PORT_CMD_ISSUE);
+
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
+ printf("set feature error!\n");
+ }
+}
+
+
+static int ahci_port_start(u8 port)
+{
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 port_status;
+ u32 mem;
+
+ debug("Enter start port: %d\n", port);
+ port_status = readl(port_mmio + PORT_SCR_STAT);
+ debug("Port %d status: %x\n", port, port_status);
+ if ((port_status & 0xf) != 0x03) {
+ printf("No Link on this port!\n");
+ return -1;
+ }
+
+ mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
+ if (!mem) {
+ free(pp);
+ printf("No mem for table!\n");
+ return -ENOMEM;
+ }
+
+ mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
+ memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+
+ /*
+ * First item in chunk of DMA memory: 32-slot command table,
+ * 32 bytes each in size
+ */
+ pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
+ debug("cmd_slot = 0x%x\n", pp->cmd_slot);
+ mem += (AHCI_CMD_SLOT_SZ + 224);
+
+ /*
+ * Second item: Received-FIS area
+ */
+ pp->rx_fis = mem;
+ mem += AHCI_RX_FIS_SZ;
+
+ /*
+ * Third item: data area for storing a single command
+ * and its scatter-gather table
+ */
+ pp->cmd_tbl = mem;
+ debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
+
+ mem += AHCI_CMD_TBL_HDR;
+ pp->cmd_tbl_sg = (struct ahci_sg *)mem;
+
+ writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
+
+ writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+
+ writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
+ PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
+ PORT_CMD_START, port_mmio + PORT_CMD);
+
+ debug("Exit start port %d\n", port);
+
+ return 0;
+}
+
+
+static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
+ int buf_len)
+{
+
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 opts;
+ u32 port_status;
+ int sg_count;
+
+ debug("Enter get_ahci_device_data: for port %d\n", port);
+
+ if (port > probe_ent->n_ports) {
+ printf("Invaild port number %d\n", port);
+ return -1;
+ }
+
+ port_status = readl(port_mmio + PORT_SCR_STAT);
+ if ((port_status & 0xf) != 0x03) {
+ debug("No Link on port %d!\n", port);
+ return -1;
+ }
+
+ memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
+
+ sg_count = ahci_fill_sg(port, buf, buf_len);
+ opts = (fis_len >> 2) | (sg_count << 16);
+ ahci_fill_cmd_slot(pp, opts);
+
+ writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
+
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
+ printf("timeout exit!\n");
+ return -1;
+ }
+ debug("get_ahci_device_data: %d byte transferred.\n",
+ pp->cmd_slot->status);
+
+ return 0;
+}
+
+
+static char *ata_id_strcpy(u16 *target, u16 *src, int len)
+{
+ int i;
+ for (i = 0; i < len / 2; i++)
+ target[i] = le16_to_cpu(src[i]);
+ return (char *)target;
+}
+
+
+static void dump_ataid(hd_driveid_t *ataid)
+{
+ debug("(49)ataid->capability = 0x%x\n", ataid->capability);
+ debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
+ debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
+ debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
+ debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
+ debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
+ debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
+ debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
+ debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
+ debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
+ debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
+ debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
+ debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
+ debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
+ debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
+}
+
+
+/*
+ * SCSI INQUIRY command operation.
+ */
+static int ata_scsiop_inquiry(ccb *pccb)
+{
+ u8 hdr[] = {
+ 0,
+ 0,
+ 0x5, /* claim SPC-3 version compatibility */
+ 2,
+ 95 - 4,
+ };
+ u8 fis[20];
+ u8 *tmpid;
+ u8 port;
+
+ /* Clean ccb data buffer */
+ memset(pccb->pdata, 0, pccb->datalen);
+
+ memcpy(pccb->pdata, hdr, sizeof(hdr));
+
+ if (pccb->datalen <= 35)
+ return 0;
+
+ memset(fis, 0, 20);
+ /* Construct the FIS */
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_IDENT; /* Command byte. */
+
+ /* Read id from sata */
+ port = pccb->target;
+ if (!(tmpid = malloc(sizeof(hd_driveid_t))))
+ return -ENOMEM;
+
+ if (get_ahci_device_data(port, (u8 *) & fis, 20,
+ tmpid, sizeof(hd_driveid_t))) {
+ debug("scsi_ahci: SCSI inquiry command failure.\n");
+ return -EIO;
+ }
+
+ if (ataid[port])
+ free(ataid[port]);
+ ataid[port] = (hd_driveid_t *) tmpid;
+
+ memcpy(&pccb->pdata[8], "ATA ", 8);
+ ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
+ ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
+
+ dump_ataid(ataid[port]);
+ return 0;
+}
+
+
+/*
+ * SCSI READ10 command operation.
+ */
+static int ata_scsiop_read10(ccb * pccb)
+{
+ u64 lba = 0;
+ u32 len = 0;
+ u8 fis[20];
+
+ lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
+ | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
+ len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
+
+ /* For 10-byte and 16-byte SCSI R/W commands, transfer
+ * length 0 means transfer 0 block of data.
+ * However, for ATA R/W commands, sector count 0 means
+ * 256 or 65536 sectors, not 0 sectors as in SCSI.
+ *
+ * WARNING: one or two older ATA drives treat 0 as 0...
+ */
+ if (!len)
+ return 0;
+ memset(fis, 0, 20);
+
+ /* Construct the FIS */
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
+
+ /* LBA address, only support LBA28 in this driver */
+ fis[4] = pccb->cmd[5];
+ fis[5] = pccb->cmd[4];
+ fis[6] = pccb->cmd[3];
+ fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
+
+ /* Sector Count */
+ fis[12] = pccb->cmd[8];
+ fis[13] = pccb->cmd[7];
+
+ /* Read from ahci */
+ if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
+ pccb->pdata, pccb->datalen)) {
+ debug("scsi_ahci: SCSI READ10 command failure.\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
+/*
+ * SCSI READ CAPACITY10 command operation.
+ */
+static int ata_scsiop_read_capacity10(ccb *pccb)
+{
+ u8 buf[8];
+
+ if (!ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
+ "\tNo ATA info!\n"
+ "\tPlease run SCSI commmand INQUIRY firstly!\n");
+ return -EPERM;
+ }
+
+ memset(buf, 0, 8);
+
+ *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+
+ buf[6] = 512 >> 8;
+ buf[7] = 512 & 0xff;
+
+ memcpy(pccb->pdata, buf, 8);
+
+ return 0;
+}
+
+
+/*
+ * SCSI TEST UNIT READY command operation.
+ */
+static int ata_scsiop_test_unit_ready(ccb *pccb)
+{
+ return (ataid[pccb->target]) ? 0 : -EPERM;
+}
+
+
+int scsi_exec(ccb *pccb)
+{
+ int ret;
+
+ switch (pccb->cmd[0]) {
+ case SCSI_READ10:
+ ret = ata_scsiop_read10(pccb);
+ break;
+ case SCSI_RD_CAPAC:
+ ret = ata_scsiop_read_capacity10(pccb);
+ break;
+ case SCSI_TST_U_RDY:
+ ret = ata_scsiop_test_unit_ready(pccb);
+ break;
+ case SCSI_INQUIRY:
+ ret = ata_scsiop_inquiry(pccb);
+ break;
+ default:
+ printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
+ return FALSE;
+ }
+
+ if (ret) {
+ debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
+ return FALSE;
+ }
+ return TRUE;
+
+}
+
+
+void scsi_low_level_init(int busdevfunc)
+{
+ int i;
+ u32 linkmap;
+
+ ahci_init_one(busdevfunc);
+
+ linkmap = probe_ent->link_port_map;
+
+ for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) {
+ if (((linkmap >> i) & 0x01)) {
+ if (ahci_port_start((u8) i)) {
+ printf("Can not start port %d\n", i);
+ continue;
+ }
+ ahci_set_feature((u8) i);
+ }
+ }
+}
+
+
+void scsi_bus_reset(void)
+{
+ /*Not implement*/
+}
+
+
+void scsi_print_error(ccb * pccb)
+{
+ /*The ahci error info can be read in the ahci driver*/
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATMEL_USART
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+#include "atmel_usart.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+ unsigned long divisor;
+ unsigned long usart_hz;
+
+ /*
+ * Master Clock
+ * Baud Rate = --------------
+ * 16 * CD
+ */
+ usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id);
+ divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
+ usart3_writel(gd->console_uart, BRGR, USART3_BF(CD, divisor));
+}
+
+int serial_init(void)
+{
+ usart3_writel(gd->console_uart, CR,
+ USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
+
+ serial_setbrg();
+
+ usart3_writel(gd->console_uart, CR,
+ USART3_BIT(RXEN) | USART3_BIT(TXEN));
+ usart3_writel(gd->console_uart, MR,
+ USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
+ | USART3_BF(USCLKS, USART3_USCLKS_MCK)
+ | USART3_BF(CHRL, USART3_CHRL_8)
+ | USART3_BF(PAR, USART3_PAR_NONE)
+ | USART3_BF(NBSTOP, USART3_NBSTOP_1));
+
+ return 0;
+}
+
+void serial_putc(char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(TXRDY))) ;
+ usart3_writel(gd->console_uart, THR, c);
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
+
+int serial_getc(void)
+{
+ while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY))) ;
+ return usart3_readl(gd->console_uart, RHR);
+}
+
+int serial_tstc(void)
+{
+ return (usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY)) != 0;
+}
+
+#endif /* CONFIG_ATMEL_USART */
--- /dev/null
+/*
+ * Register definitions for the Atmel USART3 module.
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __DRIVERS_ATMEL_USART_H__
+#define __DRIVERS_ATMEL_USART_H__
+
+/* USART3 register offsets */
+#define USART3_CR 0x0000
+#define USART3_MR 0x0004
+#define USART3_IER 0x0008
+#define USART3_IDR 0x000c
+#define USART3_IMR 0x0010
+#define USART3_CSR 0x0014
+#define USART3_RHR 0x0018
+#define USART3_THR 0x001c
+#define USART3_BRGR 0x0020
+#define USART3_RTOR 0x0024
+#define USART3_TTGR 0x0028
+#define USART3_FIDI 0x0040
+#define USART3_NER 0x0044
+#define USART3_XXR 0x0048
+#define USART3_IFR 0x004c
+#define USART3_RPR 0x0100
+#define USART3_RCR 0x0104
+#define USART3_TPR 0x0108
+#define USART3_TCR 0x010c
+#define USART3_RNPR 0x0110
+#define USART3_RNCR 0x0114
+#define USART3_TNPR 0x0118
+#define USART3_TNCR 0x011c
+#define USART3_PTCR 0x0120
+#define USART3_PTSR 0x0124
+
+/* Bitfields in CR */
+#define USART3_RSTRX_OFFSET 2
+#define USART3_RSTRX_SIZE 1
+#define USART3_RSTTX_OFFSET 3
+#define USART3_RSTTX_SIZE 1
+#define USART3_RXEN_OFFSET 4
+#define USART3_RXEN_SIZE 1
+#define USART3_RXDIS_OFFSET 5
+#define USART3_RXDIS_SIZE 1
+#define USART3_TXEN_OFFSET 6
+#define USART3_TXEN_SIZE 1
+#define USART3_TXDIS_OFFSET 7
+#define USART3_TXDIS_SIZE 1
+#define USART3_RSTSTA_OFFSET 8
+#define USART3_RSTSTA_SIZE 1
+#define USART3_STTBRK_OFFSET 9
+#define USART3_STTBRK_SIZE 1
+#define USART3_STPBRK_OFFSET 10
+#define USART3_STPBRK_SIZE 1
+#define USART3_STTTO_OFFSET 11
+#define USART3_STTTO_SIZE 1
+#define USART3_SENDA_OFFSET 12
+#define USART3_SENDA_SIZE 1
+#define USART3_RSTIT_OFFSET 13
+#define USART3_RSTIT_SIZE 1
+#define USART3_RSTNACK_OFFSET 14
+#define USART3_RSTNACK_SIZE 1
+#define USART3_RETTO_OFFSET 15
+#define USART3_RETTO_SIZE 1
+#define USART3_DTREN_OFFSET 16
+#define USART3_DTREN_SIZE 1
+#define USART3_DTRDIS_OFFSET 17
+#define USART3_DTRDIS_SIZE 1
+#define USART3_RTSEN_OFFSET 18
+#define USART3_RTSEN_SIZE 1
+#define USART3_RTSDIS_OFFSET 19
+#define USART3_RTSDIS_SIZE 1
+#define USART3_COMM_TX_OFFSET 30
+#define USART3_COMM_TX_SIZE 1
+#define USART3_COMM_RX_OFFSET 31
+#define USART3_COMM_RX_SIZE 1
+
+/* Bitfields in MR */
+#define USART3_USART_MODE_OFFSET 0
+#define USART3_USART_MODE_SIZE 4
+#define USART3_USCLKS_OFFSET 4
+#define USART3_USCLKS_SIZE 2
+#define USART3_CHRL_OFFSET 6
+#define USART3_CHRL_SIZE 2
+#define USART3_SYNC_OFFSET 8
+#define USART3_SYNC_SIZE 1
+#define USART3_PAR_OFFSET 9
+#define USART3_PAR_SIZE 3
+#define USART3_NBSTOP_OFFSET 12
+#define USART3_NBSTOP_SIZE 2
+#define USART3_CHMODE_OFFSET 14
+#define USART3_CHMODE_SIZE 2
+#define USART3_MSBF_OFFSET 16
+#define USART3_MSBF_SIZE 1
+#define USART3_MODE9_OFFSET 17
+#define USART3_MODE9_SIZE 1
+#define USART3_CLKO_OFFSET 18
+#define USART3_CLKO_SIZE 1
+#define USART3_OVER_OFFSET 19
+#define USART3_OVER_SIZE 1
+#define USART3_INACK_OFFSET 20
+#define USART3_INACK_SIZE 1
+#define USART3_DSNACK_OFFSET 21
+#define USART3_DSNACK_SIZE 1
+#define USART3_MAX_ITERATION_OFFSET 24
+#define USART3_MAX_ITERATION_SIZE 3
+#define USART3_FILTER_OFFSET 28
+#define USART3_FILTER_SIZE 1
+
+/* Bitfields in CSR */
+#define USART3_RXRDY_OFFSET 0
+#define USART3_RXRDY_SIZE 1
+#define USART3_TXRDY_OFFSET 1
+#define USART3_TXRDY_SIZE 1
+#define USART3_RXBRK_OFFSET 2
+#define USART3_RXBRK_SIZE 1
+#define USART3_ENDRX_OFFSET 3
+#define USART3_ENDRX_SIZE 1
+#define USART3_ENDTX_OFFSET 4
+#define USART3_ENDTX_SIZE 1
+#define USART3_OVRE_OFFSET 5
+#define USART3_OVRE_SIZE 1
+#define USART3_FRAME_OFFSET 6
+#define USART3_FRAME_SIZE 1
+#define USART3_PARE_OFFSET 7
+#define USART3_PARE_SIZE 1
+#define USART3_TIMEOUT_OFFSET 8
+#define USART3_TIMEOUT_SIZE 1
+#define USART3_TXEMPTY_OFFSET 9
+#define USART3_TXEMPTY_SIZE 1
+#define USART3_ITERATION_OFFSET 10
+#define USART3_ITERATION_SIZE 1
+#define USART3_TXBUFE_OFFSET 11
+#define USART3_TXBUFE_SIZE 1
+#define USART3_RXBUFF_OFFSET 12
+#define USART3_RXBUFF_SIZE 1
+#define USART3_NACK_OFFSET 13
+#define USART3_NACK_SIZE 1
+#define USART3_RIIC_OFFSET 16
+#define USART3_RIIC_SIZE 1
+#define USART3_DSRIC_OFFSET 17
+#define USART3_DSRIC_SIZE 1
+#define USART3_DCDIC_OFFSET 18
+#define USART3_DCDIC_SIZE 1
+#define USART3_CTSIC_OFFSET 19
+#define USART3_CTSIC_SIZE 1
+#define USART3_RI_OFFSET 20
+#define USART3_RI_SIZE 1
+#define USART3_DSR_OFFSET 21
+#define USART3_DSR_SIZE 1
+#define USART3_DCD_OFFSET 22
+#define USART3_DCD_SIZE 1
+#define USART3_CTS_OFFSET 23
+#define USART3_CTS_SIZE 1
+
+/* Bitfields in RHR */
+#define USART3_RXCHR_OFFSET 0
+#define USART3_RXCHR_SIZE 9
+
+/* Bitfields in THR */
+#define USART3_TXCHR_OFFSET 0
+#define USART3_TXCHR_SIZE 9
+
+/* Bitfields in BRGR */
+#define USART3_CD_OFFSET 0
+#define USART3_CD_SIZE 16
+
+/* Bitfields in RTOR */
+#define USART3_TO_OFFSET 0
+#define USART3_TO_SIZE 16
+
+/* Bitfields in TTGR */
+#define USART3_TG_OFFSET 0
+#define USART3_TG_SIZE 8
+
+/* Bitfields in FIDI */
+#define USART3_FI_DI_RATIO_OFFSET 0
+#define USART3_FI_DI_RATIO_SIZE 11
+
+/* Bitfields in NER */
+#define USART3_NB_ERRORS_OFFSET 0
+#define USART3_NB_ERRORS_SIZE 8
+
+/* Bitfields in XXR */
+#define USART3_XOFF_OFFSET 0
+#define USART3_XOFF_SIZE 8
+#define USART3_XON_OFFSET 8
+#define USART3_XON_SIZE 8
+
+/* Bitfields in IFR */
+#define USART3_IRDA_FILTER_OFFSET 0
+#define USART3_IRDA_FILTER_SIZE 8
+
+/* Bitfields in RCR */
+#define USART3_RXCTR_OFFSET 0
+#define USART3_RXCTR_SIZE 16
+
+/* Bitfields in TCR */
+#define USART3_TXCTR_OFFSET 0
+#define USART3_TXCTR_SIZE 16
+
+/* Bitfields in RNCR */
+#define USART3_RXNCR_OFFSET 0
+#define USART3_RXNCR_SIZE 16
+
+/* Bitfields in TNCR */
+#define USART3_TXNCR_OFFSET 0
+#define USART3_TXNCR_SIZE 16
+
+/* Bitfields in PTCR */
+#define USART3_RXTEN_OFFSET 0
+#define USART3_RXTEN_SIZE 1
+#define USART3_RXTDIS_OFFSET 1
+#define USART3_RXTDIS_SIZE 1
+#define USART3_TXTEN_OFFSET 8
+#define USART3_TXTEN_SIZE 1
+#define USART3_TXTDIS_OFFSET 9
+#define USART3_TXTDIS_SIZE 1
+
+/* Constants for USART_MODE */
+#define USART3_USART_MODE_NORMAL 0
+#define USART3_USART_MODE_RS485 1
+#define USART3_USART_MODE_HARDWARE 2
+#define USART3_USART_MODE_MODEM 3
+#define USART3_USART_MODE_ISO7816_T0 4
+#define USART3_USART_MODE_ISO7816_T1 6
+#define USART3_USART_MODE_IRDA 8
+
+/* Constants for USCLKS */
+#define USART3_USCLKS_MCK 0
+#define USART3_USCLKS_MCK_DIV 1
+#define USART3_USCLKS_SCK 3
+
+/* Constants for CHRL */
+#define USART3_CHRL_5 0
+#define USART3_CHRL_6 1
+#define USART3_CHRL_7 2
+#define USART3_CHRL_8 3
+
+/* Constants for PAR */
+#define USART3_PAR_EVEN 0
+#define USART3_PAR_ODD 1
+#define USART3_PAR_SPACE 2
+#define USART3_PAR_MARK 3
+#define USART3_PAR_NONE 4
+#define USART3_PAR_MULTI 6
+
+/* Constants for NBSTOP */
+#define USART3_NBSTOP_1 0
+#define USART3_NBSTOP_1_5 1
+#define USART3_NBSTOP_2 2
+
+/* Constants for CHMODE */
+#define USART3_CHMODE_NORMAL 0
+#define USART3_CHMODE_ECHO 1
+#define USART3_CHMODE_LOCAL_LOOP 2
+#define USART3_CHMODE_REMOTE_LOOP 3
+
+/* Constants for MSBF */
+#define USART3_MSBF_LSBF 0
+#define USART3_MSBF_MSBF 1
+
+/* Constants for OVER */
+#define USART3_OVER_X16 0
+#define USART3_OVER_X8 1
+
+/* Constants for CD */
+#define USART3_CD_DISABLE 0
+#define USART3_CD_BYPASS 1
+
+/* Constants for TO */
+#define USART3_TO_DISABLE 0
+
+/* Constants for TG */
+#define USART3_TG_DISABLE 0
+
+/* Constants for FI_DI_RATIO */
+#define USART3_FI_DI_RATIO_DISABLE 0
+
+/* Bit manipulation macros */
+#define USART3_BIT(name) \
+ (1 << USART3_##name##_OFFSET)
+#define USART3_BF(name,value) \
+ (((value) & ((1 << USART3_##name##_SIZE) - 1)) \
+ << USART3_##name##_OFFSET)
+#define USART3_BFEXT(name,value) \
+ (((value) >> USART3_##name##_OFFSET) \
+ & ((1 << USART3_##name##_SIZE) - 1))
+#define USART3_BFINS(name,value,old) \
+ (((old) & ~(((1 << USART3_##name##_SIZE) - 1) \
+ << USART3_##name##_OFFSET)) \
+ | USART3_BF(name,value))
+
+/* Register access macros */
+#define usart3_readl(port,reg) \
+ readl((port)->regs + USART3_##reg)
+#define usart3_writel(port,reg,value) \
+ writel((value), (port)->regs + USART3_##reg)
+
+#endif /* __DRIVERS_ATMEL_USART_H__ */
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_HARD_I2C
+
+#include <command.h>
+#include <i2c.h> /* Functional interface */
+
+#include <asm/io.h>
+#include <asm/fsl_i2c.h> /* HW definitions */
+
+#define I2C_TIMEOUT (CFG_HZ / 4)
+#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET))
+
+
+void
+i2c_init(int speed, int slaveadd)
+{
+ /* stop I2C controller */
+ writeb(0x0, &I2C->cr);
+
+ /* set clock */
+ writeb(0x3f, &I2C->fdr);
+
+ /* set default filter */
+ writeb(0x10, &I2C->dfsrr);
+
+ /* write slave address */
+ writeb(slaveadd, &I2C->adr);
+
+ /* clear status register */
+ writeb(0x0, &I2C->sr);
+
+ /* start I2C controller */
+ writeb(I2C_CR_MEN, &I2C->cr);
+}
+
+static __inline__ int
+i2c_wait4bus(void)
+{
+ ulong timeval = get_timer(0);
+
+ while (readb(&I2C->sr) & I2C_SR_MBB) {
+ if (get_timer(timeval) > I2C_TIMEOUT) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static __inline__ int
+i2c_wait(int write)
+{
+ u32 csr;
+ ulong timeval = get_timer(0);
+
+ do {
+ csr = readb(&I2C->sr);
+ if (!(csr & I2C_SR_MIF))
+ continue;
+
+ writeb(0x0, &I2C->sr);
+
+ if (csr & I2C_SR_MAL) {
+ debug("i2c_wait: MAL\n");
+ return -1;
+ }
+
+ if (!(csr & I2C_SR_MCF)) {
+ debug("i2c_wait: unfinished\n");
+ return -1;
+ }
+
+ if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
+ debug("i2c_wait: No RXACK\n");
+ return -1;
+ }
+
+ return 0;
+ } while (get_timer (timeval) < I2C_TIMEOUT);
+
+ debug("i2c_wait: timed out\n");
+ return -1;
+}
+
+static __inline__ int
+i2c_write_addr (u8 dev, u8 dir, int rsta)
+{
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
+ | (rsta ? I2C_CR_RSTA : 0),
+ &I2C->cr);
+
+ writeb((dev << 1) | dir, &I2C->dr);
+
+ if (i2c_wait(I2C_WRITE) < 0)
+ return 0;
+
+ return 1;
+}
+
+static __inline__ int
+__i2c_write(u8 *data, int length)
+{
+ int i;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
+ &I2C->cr);
+
+ for (i = 0; i < length; i++) {
+ writeb(data[i], &I2C->dr);
+
+ if (i2c_wait(I2C_WRITE) < 0)
+ break;
+ }
+
+ return i;
+}
+
+static __inline__ int
+__i2c_read(u8 *data, int length)
+{
+ int i;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
+ &I2C->cr);
+
+ /* dummy read */
+ readb(&I2C->dr);
+
+ for (i = 0; i < length; i++) {
+ if (i2c_wait(I2C_READ) < 0)
+ break;
+
+ /* Generate ack on last next to last byte */
+ if (i == length - 2)
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
+ &I2C->cr);
+
+ /* Generate stop on last byte */
+ if (i == length - 1)
+ writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
+
+ data[i] = readb(&I2C->dr);
+ }
+
+ return i;
+}
+
+int
+i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus() >= 0
+ && i2c_write_addr(dev, I2C_WRITE, 0) != 0
+ && __i2c_write(&a[4 - alen], alen) == alen
+ && i2c_write_addr(dev, I2C_READ, 1) != 0) {
+ i = __i2c_read(data, length);
+ }
+
+ writeb(I2C_CR_MEN, &I2C->cr);
+
+ if (i == length)
+ return 0;
+
+ return -1;
+}
+
+int
+i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus() >= 0
+ && i2c_write_addr(dev, I2C_WRITE, 0) != 0
+ && __i2c_write(&a[4 - alen], alen) == alen) {
+ i = __i2c_write(data, length);
+ }
+
+ writeb(I2C_CR_MEN, &I2C->cr);
+
+ if (i == length)
+ return 0;
+
+ return -1;
+}
+
+int
+i2c_probe(uchar chip)
+{
+ int tmp;
+
+ /*
+ * Try to read the first location of the chip. The underlying
+ * driver doesn't appear to support sending just the chip address
+ * and looking for an <ACK> back.
+ */
+ udelay(10000);
+
+ return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+}
+
+uchar
+i2c_reg_read(uchar i2c_addr, uchar reg)
+{
+ uchar buf[1];
+
+ i2c_read(i2c_addr, reg, 1, buf, 1);
+
+ return buf[0];
+}
+
+void
+i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+ i2c_write(i2c_addr, reg, 1, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_FSL_I2C */
size += nand_info[i].size;
if (nand_curr_device == -1)
nand_curr_device = i;
-}
+ }
printf("%lu MiB\n", size / (1024 * 1024));
+
+#ifdef CFG_NAND_SELECT_DEVICE
+ /*
+ * Select the chip in the board/cpu specific driver
+ */
+ board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
+#endif
}
#endif
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
+ bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+ & 0xffff) + 1;
bar_res = io;
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
}
if (pci_io) {
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
+ {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
{}
};
/*
- * tsec.c
* Freescale Three Speed Ethernet Controller driver
*
* This software may be used and distributed according to the
*/
#include <config.h>
-#include <mpc85xx.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#define TX_BUF_CNT 2
-static uint rxIdx; /* index of the current RX buffer */
-static uint txIdx; /* index of the current TX buffer */
+static uint rxIdx; /* index of the current RX buffer */
+static uint txIdx; /* index of the current TX buffer */
typedef volatile struct rtxbd {
txbd8_t txbd[TX_BUF_CNT];
rxbd8_t rxbd[PKTBUFSRX];
-} RTXBD;
+} RTXBD;
struct tsec_info_struct {
unsigned int phyaddr;
unsigned int phyregidx;
};
-
/* The tsec_info structure contains 3 values which the
* driver uses to determine how to operate a given ethernet
- * device. For now, the structure is initialized with the
- * knowledge that all current implementations have 2 TSEC
- * devices, and one FEC. The information needed is:
+ * device. The information needed is:
* phyaddr - The address of the PHY which is attached to
* the given device.
*
*
* phyregidx - This variable specifies which ethernet device
* controls the MII Management registers which are connected
- * to the PHY. For 8540/8560, only TSEC1 (index 0) has
+ * to the PHY. For now, only TSEC1 (index 0) has
* access to the PHYs, so all of the entries have "0".
*
* The values specified in the table are taken from the board's
* config file in include/configs/. When implementing a new
* board with ethernet capability, it is necessary to define:
- * TSEC1_PHY_ADDR
- * TSEC1_PHYIDX
- * TSEC2_PHY_ADDR
- * TSEC2_PHYIDX
+ * TSECn_PHY_ADDR
+ * TSECn_PHYIDX
*
- * and for 8560:
+ * for n = 1,2,3, etc. And for FEC:
* FEC_PHY_ADDR
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC1)
+ {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
- { 0, 0, 0},
+ {0, 0, 0},
#endif
#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC2)
+ {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
#else
- { 0, 0, 0},
+ {0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else
-# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
+#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
-# else
- { 0, 0, 0},
-# endif
-# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
- {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
-# else
- { 0, 0, 0},
-# endif
+#else
+ {0, 0, 0},
+#endif
+#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
+ {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#else
+ {0, 0, 0},
+#endif
#endif
};
#error "rtx must be 64-bit aligned"
#endif
-static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
-static int tsec_recv(struct eth_device* dev);
-static int tsec_init(struct eth_device* dev, bd_t * bd);
-static void tsec_halt(struct eth_device* dev);
-static void init_registers(volatile tsec_t *regs);
+static int tsec_send(struct eth_device *dev,
+ volatile void *packet, int length);
+static int tsec_recv(struct eth_device *dev);
+static int tsec_init(struct eth_device *dev, bd_t * bd);
+static void tsec_halt(struct eth_device *dev);
+static void init_registers(volatile tsec_t * regs);
static void startup_tsec(struct eth_device *dev);
static int init_phy(struct eth_device *dev);
void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
uint read_phy_reg(struct tsec_private *priv, uint regnum);
-struct phy_info * get_phy_info(struct eth_device *dev);
+struct phy_info *get_phy_info(struct eth_device *dev);
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
static void adjust_link(struct eth_device *dev);
static void relocate_cmds(void);
static int tsec_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
+ unsigned char reg, unsigned short value);
static int tsec_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
+ unsigned char reg, unsigned short *value);
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
-int tsec_initialize(bd_t *bis, int index, char *devname)
+int tsec_initialize(bd_t * bis, int index, char *devname)
{
- struct eth_device* dev;
+ struct eth_device *dev;
int i;
struct tsec_private *priv;
- dev = (struct eth_device*) malloc(sizeof *dev);
+ dev = (struct eth_device *)malloc(sizeof *dev);
- if(NULL == dev)
+ if (NULL == dev)
return 0;
memset(dev, 0, sizeof *dev);
- priv = (struct tsec_private *) malloc(sizeof(*priv));
+ priv = (struct tsec_private *)malloc(sizeof(*priv));
- if(NULL == priv)
+ if (NULL == priv)
return 0;
privlist[index] = priv;
- priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
+ priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
- tsec_info[index].phyregidx*TSEC_SIZE);
+ tsec_info[index].phyregidx *
+ TSEC_SIZE);
priv->phyaddr = tsec_info[index].phyaddr;
priv->flags = tsec_info[index].flags;
sprintf(dev->name, devname);
dev->iobase = 0;
- dev->priv = priv;
- dev->init = tsec_init;
- dev->halt = tsec_halt;
- dev->send = tsec_send;
- dev->recv = tsec_recv;
+ dev->priv = priv;
+ dev->init = tsec_init;
+ dev->halt = tsec_halt;
+ dev->send = tsec_send;
+ dev->recv = tsec_recv;
/* Tell u-boot to get the addr from the env */
- for(i=0;i<6;i++)
+ for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
-
/* Reset the MAC */
priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
return init_phy(dev);
}
-
/* Initializes data structures and registers for the controller,
* and brings the interface up. Returns the link status, meaning
* that it returns success if the link is up, failure otherwise.
- * This allows u-boot to find the first active controller. */
-int tsec_init(struct eth_device* dev, bd_t * bd)
+ * This allows u-boot to find the first active controller.
+ */
+int tsec_init(struct eth_device *dev, bd_t * bd)
{
uint tempval;
char tmpbuf[MAC_ADDR_LEN];
/* Copy the station address into the address registers.
* Backwards, because little endian MACS are dumb */
- for(i=0;i<MAC_ADDR_LEN;i++) {
+ for (i = 0; i < MAC_ADDR_LEN; i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
}
- regs->macstnaddr1 = *((uint *)(tmpbuf));
+ regs->macstnaddr1 = *((uint *) (tmpbuf));
- tempval = *((uint *)(tmpbuf +4));
+ tempval = *((uint *) (tmpbuf + 4));
regs->macstnaddr2 = tempval;
}
-
/* Write value to the device's PHY through the registers
* specified in priv, modifying the register specified in regnum.
* It will wait for the write to be done (or for a timeout to
{
volatile tsec_t *regbase = priv->phyregs;
uint phyid = priv->phyaddr;
- int timeout=1000000;
+ int timeout = 1000000;
regbase->miimadd = (phyid << 8) | regnum;
regbase->miimcon = value;
asm("sync");
- timeout=1000000;
- while((regbase->miimind & MIIMIND_BUSY) && timeout--);
+ timeout = 1000000;
+ while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
}
-
/* Reads register regnum on the device's PHY through the
* registers specified in priv. It lowers and raises the read
* command, and waits for the data to become valid (miimind
asm("sync");
/* Wait for the the indication that the read is done */
- while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
+ while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
/* Grab the value read from the PHY */
value = regbase->miimstat;
return value;
}
-
/* Discover which PHY is attached to the device, and configure it
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_info *curphy;
+ volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
/* Assign a Physical address to the TBI */
-
- {
- volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
- regs->tbipa = TBIPA_VALUE;
- regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
- regs->tbipa = TBIPA_VALUE;
- asm("sync");
- }
+ regs->tbipa = TBIPA_VALUE;
+ regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
+ regs->tbipa = TBIPA_VALUE;
+ asm("sync");
/* Reset MII (due to new addresses) */
priv->phyregs->miimcfg = MIIMCFG_RESET;
asm("sync");
priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
asm("sync");
- while(priv->phyregs->miimind & MIIMIND_BUSY);
+ while (priv->phyregs->miimind & MIIMIND_BUSY) ;
- if(0 == relocated)
+ if (0 == relocated)
relocate_cmds();
/* Get the cmd structure corresponding to the attached
* PHY */
curphy = get_phy_info(dev);
- if(NULL == curphy) {
+ if (NULL == curphy) {
printf("%s: No PHY found\n", dev->name);
return 0;
return 1;
}
-
-/* Returns which value to write to the control register. */
-/* For 10/100, the value is slightly different */
-uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
+/*
+ * Returns which value to write to the control register.
+ * For 10/100, the value is slightly different
+ */
+uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
{
- if(priv->flags & TSEC_GIGABIT)
+ if (priv->flags & TSEC_GIGABIT)
return MIIM_CONTROL_INIT;
else
return MIIM_CR_INIT;
}
-
/* Parse the status register for link, and then do
- * auto-negotiation */
-uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
+ * auto-negotiation
+ */
+uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
{
/*
- * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
+ * Wait if PHY is capable of autonegotiation and autonegotiation
+ * is not complete.
*/
mii_reg = read_phy_reg(priv, MIIM_STATUS);
- if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ if ((mii_reg & PHY_BMSR_AUTN_ABLE)
+ && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
int i = 0;
- puts ("Waiting for PHY auto negotiation to complete");
- while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) {
+ puts("Waiting for PHY auto negotiation to complete");
+ while (!((mii_reg & PHY_BMSR_AUTN_COMP)
+ && (mii_reg & MIIM_STATUS_LINK))) {
/*
* Timeout reached ?
*/
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
+ puts(" TIMEOUT !\n");
priv->link = 0;
- break;
+ return 0;
}
if ((i++ % 1000) == 0) {
- putc ('.');
+ putc('.');
}
- udelay (1000); /* 1 ms */
+ udelay(1000); /* 1 ms */
mii_reg = read_phy_reg(priv, MIIM_STATUS);
}
- puts (" done\n");
+ puts(" done\n");
priv->link = 1;
- udelay (500000); /* another 500 ms (results in faster booting) */
+ udelay(500000); /* another 500 ms (results in faster booting) */
} else {
priv->link = 1;
}
return 0;
}
-
/* Parse the 88E1011's status register for speed and duplex
- * information */
-uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
+ * information
+ */
+uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
{
uint speed;
(mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
int i = 0;
- puts ("Waiting for PHY realtime link");
+ puts("Waiting for PHY realtime link");
while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
(mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
/*
* Timeout reached ?
*/
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
+ puts(" TIMEOUT !\n");
priv->link = 0;
break;
}
if ((i++ % 1000) == 0) {
- putc ('.');
+ putc('.');
}
- udelay (1000); /* 1 ms */
+ udelay(1000); /* 1 ms */
mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
}
- puts (" done\n");
- udelay (500000); /* another 500 ms (results in faster booting) */
+ puts(" done\n");
+ udelay(500000); /* another 500 ms (results in faster booting) */
}
- if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
+ if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
priv->duplexity = 1;
else
priv->duplexity = 0;
- speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
+ speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
- switch(speed) {
- case MIIM_88E1011_PHYSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_88E1011_PHYSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
+ switch (speed) {
+ case MIIM_88E1011_PHYSTAT_GBIT:
+ priv->speed = 1000;
+ break;
+ case MIIM_88E1011_PHYSTAT_100:
+ priv->speed = 100;
+ break;
+ default:
+ priv->speed = 10;
}
return 0;
}
-
/* Parse the cis8201's status register for speed and duplex
- * information */
-uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
+ * information
+ */
+uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
{
uint speed;
- if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
+ if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
priv->duplexity = 1;
else
priv->duplexity = 0;
speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
- switch(speed) {
- case MIIM_CIS8201_AUXCONSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_CIS8201_AUXCONSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
- break;
+ switch (speed) {
+ case MIIM_CIS8201_AUXCONSTAT_GBIT:
+ priv->speed = 1000;
+ break;
+ case MIIM_CIS8201_AUXCONSTAT_100:
+ priv->speed = 100;
+ break;
+ default:
+ priv->speed = 10;
+ break;
}
return 0;
}
+/* Parse the vsc8244's status register for speed and duplex
+ * information
+ */
+uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
+{
+ uint speed;
+
+ if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
+ priv->duplexity = 1;
+ else
+ priv->duplexity = 0;
+
+ speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
+ switch (speed) {
+ case MIIM_VSC8244_AUXCONSTAT_GBIT:
+ priv->speed = 1000;
+ break;
+ case MIIM_VSC8244_AUXCONSTAT_100:
+ priv->speed = 100;
+ break;
+ default:
+ priv->speed = 10;
+ break;
+ }
+
+ return 0;
+}
/* Parse the DM9161's status register for speed and duplex
- * information */
-uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
+ * information
+ */
+uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
{
- if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
+ if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
priv->speed = 100;
else
priv->speed = 10;
- if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
+ if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
priv->duplexity = 1;
else
priv->duplexity = 0;
return 0;
}
-
-/* Hack to write all 4 PHYs with the LED values */
-uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
+/*
+ * Hack to write all 4 PHYs with the LED values
+ */
+uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
{
uint phyid;
volatile tsec_t *regbase = priv->phyregs;
- int timeout=1000000;
+ int timeout = 1000000;
- for(phyid=0;phyid<4;phyid++) {
+ for (phyid = 0; phyid < 4; phyid++) {
regbase->miimadd = (phyid << 8) | mii_reg;
regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
asm("sync");
- timeout=1000000;
- while((regbase->miimind & MIIMIND_BUSY) && timeout--);
+ timeout = 1000000;
+ while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
}
return MIIM_CIS8204_SLEDCON_INIT;
}
-uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
+uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
{
if (priv->flags & TSEC_REDUCED)
return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
/* Initialized required registers to appropriate values, zeroing
* those we don't care about (unless zero is bad, in which case,
- * choose a more appropriate value) */
-static void init_registers(volatile tsec_t *regs)
+ * choose a more appropriate value)
+ */
+static void init_registers(volatile tsec_t * regs)
{
/* Clear IEVENT */
regs->ievent = IEVENT_INIT_CLEAR;
}
-
/* Configure maccfg2 based on negotiated speed and duplex
- * reported by PHY handling code */
+ * reported by PHY handling code
+ */
static void adjust_link(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
volatile tsec_t *regs = priv->regs;
- if(priv->link) {
- if(priv->duplexity != 0)
+ if (priv->link) {
+ if (priv->duplexity != 0)
regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
else
regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
- switch(priv->speed) {
- case 1000:
- regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
- | MACCFG2_GMII);
- break;
- case 100:
- case 10:
- regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
- | MACCFG2_MII);
-
- /* If We're in reduced mode, we need
- * to say whether we're 10 or 100 MB.
- */
- if ((priv->speed == 100)
- && (priv->flags & TSEC_REDUCED))
- regs->ecntrl |= ECNTRL_R100;
- else
- regs->ecntrl &= ~(ECNTRL_R100);
- break;
- default:
- printf("%s: Speed was bad\n", dev->name);
- break;
+ switch (priv->speed) {
+ case 1000:
+ regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
+ | MACCFG2_GMII);
+ break;
+ case 100:
+ case 10:
+ regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
+ | MACCFG2_MII);
+
+ /* If We're in reduced mode, we need
+ * to say whether we're 10 or 100 MB.
+ */
+ if ((priv->speed == 100)
+ && (priv->flags & TSEC_REDUCED))
+ regs->ecntrl |= ECNTRL_R100;
+ else
+ regs->ecntrl &= ~(ECNTRL_R100);
+ break;
+ default:
+ printf("%s: Speed was bad\n", dev->name);
+ break;
}
printf("Speed: %d, %s duplex\n", priv->speed,
- (priv->duplexity) ? "full" : "half");
+ (priv->duplexity) ? "full" : "half");
} else {
printf("%s: No link.\n", dev->name);
}
}
-
/* Set up the buffers and their descriptors, and bring up the
- * interface */
+ * interface
+ */
static void startup_tsec(struct eth_device *dev)
{
int i;
for (i = 0; i < PKTBUFSRX; i++) {
rtx.rxbd[i].status = RXBD_EMPTY;
rtx.rxbd[i].length = 0;
- rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
+ rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
}
- rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
+ rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
/* Initialize the TX Buffer Descriptors */
- for(i=0; i<TX_BUF_CNT; i++) {
+ for (i = 0; i < TX_BUF_CNT; i++) {
rtx.txbd[i].status = 0;
rtx.txbd[i].length = 0;
rtx.txbd[i].bufPtr = 0;
}
- rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
+ rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
/* Start up the PHY */
phy_run_commands(priv, priv->phyinfo->startup);
/* This returns the status bits of the device. The return value
* is never checked, and this is what the 8260 driver did, so we
* do the same. Presumably, this would be zero if there were no
- * errors */
-static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
+ * errors
+ */
+static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
{
int i;
int result = 0;
volatile tsec_t *regs = priv->regs;
/* Find an empty buffer descriptor */
- for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
- debug ("%s: tsec: tx buffers full\n", dev->name);
+ debug("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
- rtx.txbd[txIdx].bufPtr = (uint)packet;
+ rtx.txbd[txIdx].bufPtr = (uint) packet;
rtx.txbd[txIdx].length = length;
- rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
+ rtx.txbd[txIdx].status |=
+ (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
/* Tell the DMA to go */
regs->tstat = TSTAT_CLEAR_THALT;
/* Wait for buffer to be transmitted */
- for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
- debug ("%s: tsec: tx error\n", dev->name);
+ debug("%s: tsec: tx error\n", dev->name);
return result;
}
}
return result;
}
-static int tsec_recv(struct eth_device* dev)
+static int tsec_recv(struct eth_device *dev)
{
int length;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
volatile tsec_t *regs = priv->regs;
- while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
+ while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
length = rtx.rxbd[rxIdx].length;
NetReceive(NetRxPackets[rxIdx], length - 4);
} else {
printf("Got error %x\n",
- (rtx.rxbd[rxIdx].status & RXBD_STATS));
+ (rtx.rxbd[rxIdx].status & RXBD_STATS));
}
rtx.rxbd[rxIdx].length = 0;
/* Set the wrap bit if this is the last element in the list */
- rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+ rtx.rxbd[rxIdx].status =
+ RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
rxIdx = (rxIdx + 1) % PKTBUFSRX;
}
- if(regs->ievent&IEVENT_BSY) {
+ if (regs->ievent & IEVENT_BSY) {
regs->ievent = IEVENT_BSY;
regs->rstat = RSTAT_CLEAR_RHALT;
}
}
-
/* Stop the interface */
-static void tsec_halt(struct eth_device* dev)
+static void tsec_halt(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
volatile tsec_t *regs = priv->regs;
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
- while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
+ while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
phy_run_commands(priv, priv->phyinfo->shutdown);
}
-
struct phy_info phy_info_M88E1011S = {
0x01410c6,
"Marvell 88E1011S",
4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1d, 0x1f, NULL},
- {0x1e, 0x200c, NULL},
- {0x1d, 0x5, NULL},
- {0x1e, 0x0, NULL},
- {0x1e, 0x100, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {0x1d, 0x1f, NULL},
+ {0x1e, 0x200c, NULL},
+ {0x1d, 0x5, NULL},
+ {0x1e, 0x0, NULL},
+ {0x1e, 0x100, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_88E1011_PHY_STATUS, miim_read,
+ &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
struct phy_info phy_info_M88E1111S = {
0x01410cc,
"Marvell 88E1111S",
4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1d, 0x1f, NULL},
- {0x1e, 0x200c, NULL},
- {0x1d, 0x5, NULL},
- {0x1e, 0x0, NULL},
- {0x1e, 0x100, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {0x1d, 0x1f, NULL},
+ {0x1e, 0x200c, NULL},
+ {0x1d, 0x5, NULL},
+ {0x1e, 0x0, NULL},
+ {0x1e, 0x100, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_88E1011_PHY_STATUS, miim_read,
+ &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+
+static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
+{
+ uint mii_data = read_phy_reg(priv, mii_reg);
+
+ /* Setting MIIM_88E1145_PHY_EXT_CR */
+ if (priv->flags & TSEC_REDUCED)
+ return mii_data |
+ MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
+ else
+ return mii_data;
+}
+
+static struct phy_info phy_info_M88E1145 = {
+ 0x01410cd,
+ "Marvell 88E1145",
+ 4,
+ (struct phy_cmd[]){ /* config */
+ /* Errata E0, E1 */
+ {29, 0x001b, NULL},
+ {30, 0x418f, NULL},
+ {29, 0x0016, NULL},
+ {30, 0xa2da, NULL},
+
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
+ NULL},
+ {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_88E1111_PHY_LED_CONTROL,
+ MIIM_88E1111_PHY_LED_DIRECT, NULL},
+ /* Read the Status */
+ {MIIM_88E1011_PHY_STATUS, miim_read,
+ &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
struct phy_info phy_info_cis8204 = {
0x3f11,
"Cicada Cis8204",
6,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
- {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Override PHY config settings */
+ {MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
+ &mii_cis8204_fixled},
+ {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
+ &mii_cis8204_setmode},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_CIS8201_AUX_CONSTAT, miim_read,
+ &mii_parse_cis8201},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
/* Cicada 8201 */
0xfc41,
"CIS8201",
4,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
- /* Set up the interface mode */
- {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Override PHY config settings */
+ {MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
+ /* Set up the interface mode */
+ {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
+ NULL},
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_CIS8201_AUX_CONSTAT, miim_read,
+ &mii_parse_cis8201},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+struct phy_info phy_info_VSC8244 = {
+ 0x3f1b,
+ "Vitesse VSC8244",
+ 6,
+ (struct phy_cmd[]){ /* config */
+ /* Override PHY config settings */
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_VSC8244_AUX_CONSTAT, miim_read,
+ &mii_parse_vsc8244},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
-
struct phy_info phy_info_dm9161 = {
0x0181b88,
"Davicom DM9161E",
4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
- /* Do not bypass the scrambler/descrambler */
- {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
- /* Clear 10BTCSR to default */
- {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CR_INIT, NULL},
- /* Restart Auto Negotiation */
- {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
+ /* Do not bypass the scrambler/descrambler */
+ {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
+ /* Clear 10BTCSR to default */
+ {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
+ NULL},
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CR_INIT, NULL},
+ /* Restart Auto Negotiation */
+ {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_DM9161_SCSR, miim_read,
+ &mii_parse_dm9161_scsr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
0x0001378e,
"LXT971",
4,
- (struct phy_cmd []) { /* config */
- { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
- { miim_end, }
- },
- (struct phy_cmd []) { /* startup - enable interrupts */
- /* { 0x12, 0x00f2, NULL }, */
- { MIIM_STATUS, miim_read, NULL },
- { MIIM_STATUS, miim_read, &mii_parse_sr },
- { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
- { miim_end, }
- },
- (struct phy_cmd []) { /* shutdown - disable interrupts */
- { miim_end, }
- },
+ (struct phy_cmd[]){ /* config */
+ {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup - enable interrupts */
+ /* { 0x12, 0x00f2, NULL }, */
+ {MIIM_STATUS, miim_read, NULL},
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown - disable interrupts */
+ {miim_end,}
+ },
};
/* Parse the DP83865's link and auto-neg status register for speed and duplex
- * information */
+ * information
+ */
uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
{
switch (mii_reg & MIIM_DP83865_SPD_MASK) {
0x20005c7,
"NatSemi DP83865",
4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the link and auto-neg status */
- {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the link and auto-neg status */
+ {MIIM_DP83865_LANR, miim_read,
+ &mii_parse_dp83865_lanr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
struct phy_info *phy_info[] = {
&phy_info_cis8204,
&phy_info_M88E1011S,
&phy_info_M88E1111S,
+ &phy_info_M88E1145,
&phy_info_dm9161,
&phy_info_lxt971,
+ &phy_info_VSC8244,
&phy_info_dp83865,
NULL
};
-
/* Grab the identifier of the device's PHY, and search through
* all of the known PHYs to see if one matches. If so, return
- * it, if not, return NULL */
-struct phy_info * get_phy_info(struct eth_device *dev)
+ * it, if not, return NULL
+ */
+struct phy_info *get_phy_info(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
uint phy_reg, phy_ID;
/* loop through all the known PHY types, and find one that */
/* matches the ID we read from the PHY. */
- for(i=0; phy_info[i]; i++) {
- if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
+ for (i = 0; phy_info[i]; i++) {
+ if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
theInfo = phy_info[i];
}
- if(theInfo == NULL)
- {
+ if (theInfo == NULL) {
printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
return NULL;
} else {
return theInfo;
}
-
/* Execute the given series of commands on the given device's
- * PHY, running functions as necessary*/
+ * PHY, running functions as necessary
+ */
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
{
int i;
phyregs->miimcfg = MIIMCFG_INIT_VALUE;
- while(phyregs->miimind & MIIMIND_BUSY);
+ while (phyregs->miimind & MIIMIND_BUSY) ;
- for(i=0;cmd->mii_reg != miim_end;i++) {
- if(cmd->mii_data == miim_read) {
+ for (i = 0; cmd->mii_reg != miim_end; i++) {
+ if (cmd->mii_data == miim_read) {
result = read_phy_reg(priv, cmd->mii_reg);
- if(cmd->funct != NULL)
- (*(cmd->funct))(result, priv);
+ if (cmd->funct != NULL)
+ (*(cmd->funct)) (result, priv);
} else {
- if(cmd->funct != NULL)
- result = (*(cmd->funct))(cmd->mii_reg, priv);
+ if (cmd->funct != NULL)
+ result = (*(cmd->funct)) (cmd->mii_reg, priv);
else
result = cmd->mii_data;
}
}
-
/* Relocate the function pointers in the phy cmd lists */
static void relocate_cmds(void)
{
struct phy_cmd **cmdlistptr;
struct phy_cmd *cmd;
- int i,j,k;
+ int i, j, k;
- for(i=0; phy_info[i]; i++) {
+ for (i = 0; phy_info[i]; i++) {
/* First thing's first: relocate the pointers to the
* PHY command structures (the structs were done) */
- phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
- + gd->reloc_off);
+ phy_info[i] = (struct phy_info *)((uint) phy_info[i]
+ + gd->reloc_off);
phy_info[i]->name += gd->reloc_off;
phy_info[i]->config =
- (struct phy_cmd *)((uint)phy_info[i]->config
- + gd->reloc_off);
+ (struct phy_cmd *)((uint) phy_info[i]->config
+ + gd->reloc_off);
phy_info[i]->startup =
- (struct phy_cmd *)((uint)phy_info[i]->startup
- + gd->reloc_off);
+ (struct phy_cmd *)((uint) phy_info[i]->startup
+ + gd->reloc_off);
phy_info[i]->shutdown =
- (struct phy_cmd *)((uint)phy_info[i]->shutdown
- + gd->reloc_off);
+ (struct phy_cmd *)((uint) phy_info[i]->shutdown
+ + gd->reloc_off);
cmdlistptr = &phy_info[i]->config;
- j=0;
- for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
- k=0;
- for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
+ j = 0;
+ for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
+ k = 0;
+ for (cmd = *cmdlistptr;
+ cmd->mii_reg != miim_end;
+ cmd++) {
/* Only relocate non-NULL pointers */
- if(cmd->funct)
+ if (cmd->funct)
cmd->funct += gd->reloc_off;
k++;
relocated = 1;
}
-
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
&& !defined(BITBANGMII)
-struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
+struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
{
int i;
- for(i=0;i<MAXCONTROLLERS;i++) {
- if(privlist[i]->phyaddr == phyaddr)
+ for (i = 0; i < MAXCONTROLLERS; i++) {
+ if (privlist[i]->phyaddr == phyaddr)
return privlist[i];
}
* 0 on success
*/
static int tsec_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
+ unsigned char reg, unsigned short *value)
{
unsigned short ret;
struct tsec_private *priv = get_priv_for_phy(addr);
- if(NULL == priv) {
+ if (NULL == priv) {
printf("Can't read PHY at address %d\n", addr);
return -1;
}
* 0 on success
*/
static int tsec_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
+ unsigned char reg, unsigned short value)
{
struct tsec_private *priv = get_priv_for_phy(addr);
- if(NULL == priv) {
+ if (NULL == priv) {
printf("Can't write PHY at address %d\n", addr);
return -1;
}
#define TSEC_SIZE 0x01000
/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
#elif defined(CONFIG_MPC83XX)
#define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
#define MIIM_GBIT_CON 0x09
#define MIIM_GBIT_CON_ADVERT 0x0e00
+/* Entry for Vitesse VSC8244 regs starts here */
+/* Vitesse VSC8244 Auxiliary Control/Status Register */
+#define MIIM_VSC8244_AUX_CONSTAT 0x1c
+#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
+#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
+#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
+#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
+#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
+#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
+
+/* Vitesse VSC8244 Extended PHY Control Register 1 */
+#define MIIM_VSC8244_EPHY_CON 0x17
+#define MIIM_VSC8244_EPHYCON_INIT 0x0006
+
+/* Vitesse VSC8244 Serial LED Control Register */
+#define MIIM_VSC8244_LED_CON 0x1b
+#define MIIM_VSC8244_LEDCON_INIT 0xF011
+
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
#define MIIM_88E1011_PHYSTAT_LINK 0x0400
+#define MIIM_88E1011_PHY_SCR 0x10
+#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
+
+/* 88E1111 PHY LED Control Register */
+#define MIIM_88E1111_PHY_LED_CONTROL 24
+#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
+
+/* 88E1145 Extended PHY Specific Control Register */
+#define MIIM_88E1145_PHY_EXT_CR 20
+#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
+#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
+
+#define MIIM_88E1145_PHY_PAGE 29
+#define MIIM_88E1145_PHY_CAL_OV 30
+
+
/* DM9161 Control register values */
#define MIIM_DM9161_CR_STOP 0x0400
#define MIIM_DM9161_CR_RSTAN 0x1200
LOAD_ADDR = 0x1000
endif
+ifeq ($(ARCH),avr32)
+LOAD_ADDR = 0x00000000
+endif
+
include $(TOPDIR)/config.mk
+ELF = hello_world
SREC = hello_world.srec
-BIN = hello_world.bin hello_world
+BIN = hello_world.bin
ifeq ($(CPU),mpc8xx)
+ELF = test_burst
SREC = test_burst.srec
-BIN = test_burst.bin test_burst
+BIN = test_burst.bin
endif
ifeq ($(ARCH),i386)
-SREC += 82559_eeprom.srec
-BIN += 82559_eeprom.bin 82559_eeprom
+ELF += 82559_eeprom
+SREC += 82559_eeprom.srec
+BIN += 82559_eeprom.bin
endif
ifeq ($(ARCH),ppc)
-SREC += sched.srec
-BIN += sched.bin sched
+ELF += sched
+SREC += sched.srec
+BIN += sched.bin
endif
ifeq ($(ARCH),blackfin)
+ELF += smc91111_eeprom
SREC += smc91111_eeprom.srec
-BIN += smc91111_eeprom.bin smc91111_eeprom
+BIN += smc91111_eeprom.bin
endif
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
-SREC += timer.srec
-BIN += timer.bin timer
+ELF += timer
+SREC += timer.srec
+BIN += timer.bin
endif
# The following example is 8260 specific...
ifeq ($(CPU),mpc8260)
-SREC += mem_to_mem_idma2intr.srec
-BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr
+ELF += mem_to_mem_idma2intr
+SREC += mem_to_mem_idma2intr.srec
+BIN += mem_to_mem_idma2intr.bin
endif
# Demo for 52xx IRQs
ifeq ($(CPU),mpc5xxx)
-SREC += interrupt.srec
-BIN += interrupt.bin interrupt
+ELF += interrupt
+SREC += interrupt.srec
+BIN += interrupt.bin
endif
# Utility for resetting i82559 EEPROM
ifeq ($(BOARD),oxc)
-SREC += eepro100_eeprom.srec
-BIN += eepro100_eeprom.bin eepro100_eeprom
+ELF += eepro100_eeprom
+SREC += eepro100_eeprom.srec
+BIN += eepro100_eeprom.bin
endif
ifeq ($(BIG_ENDIAN),y)
SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(if $(LIBAOBJS),$(LIBAOBJS:.o=.S))
OBJS := $(addprefix $(obj),$(COBJS))
+ELF := $(addprefix $(obj),$(ELF))
BIN := $(addprefix $(obj),$(BIN))
SREC := $(addprefix $(obj),$(SREC))
CPPFLAGS += -I..
-all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN)
+all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF)
#########################################################################
$(LIB): $(obj).depend $(LIBOBJS)
$(AR) $(ARFLAGS) $@ $(LIBOBJS)
+$(ELF):
$(obj)%: $(obj)%.o $(LIB)
$(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
-o $@ -e $(notdir $(<:.o=)) $< $(LIB) \
-L$(gcclibdir) -lgcc
+
+$(SREC):
$(obj)%.srec: $(obj)%
$(OBJCOPY) -O srec $< $@ 2>/dev/null
+$(BIN):
$(obj)%.bin: $(obj)%
$(OBJCOPY) -O binary $< $@ 2>/dev/null
" P0 = [P0 + %1]\n" \
" JUMP (P0)\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");
+#elif defined(CONFIG_AVR32)
+/*
+ * r6 holds the pointer to the global_data. r8 is call clobbered.
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile( \
+ " .globl\t" #x "\n" \
+ #x ":\n" \
+ " ld.w r8, r6[%0]\n" \
+ " ld.w pc, r8[%1]\n" \
+ : \
+ : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \
+ : "r8");
#else
#error stubs definition missing for this architecture
#endif
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ * Zhang Wei<wei.zhang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _AHCI_H_
+#define _AHCI_H_
+
+#define AHCI_PCI_BAR 0x24
+#define AHCI_MAX_SG 56 /* hardware max is 64K */
+#define AHCI_CMD_SLOT_SZ 32
+#define AHCI_RX_FIS_SZ 256
+#define AHCI_CMD_TBL_HDR 0x80
+#define AHCI_CMD_TBL_CDB 0x40
+#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \
+ + AHCI_RX_FIS_SZ
+#define AHCI_CMD_ATAPI (1 << 5)
+#define AHCI_CMD_WRITE (1 << 6)
+#define AHCI_CMD_PREFETCH (1 << 7)
+#define AHCI_CMD_RESET (1 << 8)
+#define AHCI_CMD_CLR_BUSY (1 << 10)
+
+#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
+
+/* Global controller registers */
+#define HOST_CAP 0x00 /* host capabilities */
+#define HOST_CTL 0x04 /* global host control */
+#define HOST_IRQ_STAT 0x08 /* interrupt status */
+#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
+#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
+
+/* HOST_CTL bits */
+#define HOST_RESET (1 << 0) /* reset controller; self-clear */
+#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
+#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
+
+/* Registers for each SATA port */
+#define PORT_LST_ADDR 0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT 0x10 /* interrupt status */
+#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
+#define PORT_CMD 0x18 /* port command */
+#define PORT_TFDATA 0x20 /* taskfile data */
+#define PORT_SIG 0x24 /* device TF signature */
+#define PORT_CMD_ISSUE 0x38 /* command issue */
+#define PORT_SCR 0x28 /* SATA phy register block */
+#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
+ | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
+
+#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
+ | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
+ | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
+ | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
+ | PORT_IRQ_D2H_REG_FIS
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO (1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
+#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
+
+#define AHCI_MAX_PORTS 32
+
+/* SETFEATURES stuff */
+#define SETFEATURES_XFER 0x03
+#define XFER_UDMA_7 0x47
+#define XFER_UDMA_6 0x46
+#define XFER_UDMA_5 0x45
+#define XFER_UDMA_4 0x44
+#define XFER_UDMA_3 0x43
+#define XFER_UDMA_2 0x42
+#define XFER_UDMA_1 0x41
+#define XFER_UDMA_0 0x40
+#define XFER_MW_DMA_2 0x22
+#define XFER_MW_DMA_1 0x21
+#define XFER_MW_DMA_0 0x20
+#define XFER_SW_DMA_2 0x12
+#define XFER_SW_DMA_1 0x11
+#define XFER_SW_DMA_0 0x10
+#define XFER_PIO_4 0x0C
+#define XFER_PIO_3 0x0B
+#define XFER_PIO_2 0x0A
+#define XFER_PIO_1 0x09
+#define XFER_PIO_0 0x08
+#define XFER_PIO_SLOW 0x00
+
+#define ATA_FLAG_SATA (1 << 3)
+#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
+#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
+#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
+#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
+#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
+
+struct ahci_cmd_hdr {
+ u32 opts;
+ u32 status;
+ u32 tbl_addr;
+ u32 tbl_addr_hi;
+ u32 reserved[4];
+};
+
+struct ahci_sg {
+ u32 addr;
+ u32 addr_hi;
+ u32 reserved;
+ u32 flags_size;
+};
+
+struct ahci_ioports {
+ u32 cmd_addr;
+ u32 scr_addr;
+ u32 port_mmio;
+ struct ahci_cmd_hdr *cmd_slot;
+ struct ahci_sg *cmd_tbl_sg;
+ u32 cmd_tbl;
+ u32 rx_fis;
+};
+
+struct ahci_probe_ent {
+ pci_dev_t dev;
+ struct ahci_ioports port[AHCI_MAX_PORTS];
+ u32 n_ports;
+ u32 hard_port_no;
+ u32 host_flags;
+ u32 host_set_flags;
+ u32 mmio_base;
+ u32 pio_mask;
+ u32 udma_mask;
+ u32 flags;
+ u32 cap; /* cache of HOST_CAP register */
+ u32 port_map; /* cache of HOST_PORTS_IMPL reg */
+ u32 link_port_map; /*linkup port map*/
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ADDRSPACE_H
+#define __ASM_AVR32_ADDRSPACE_H
+
+/* Memory segments when segmentation is enabled */
+#define P0SEG 0x00000000
+#define P1SEG 0x80000000
+#define P2SEG 0xa0000000
+#define P3SEG 0xc0000000
+#define P4SEG 0xe0000000
+
+/* Returns the privileged segment base of a given address */
+#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
+
+/* Returns the physical address of a PnSEG (n=1,2) address */
+#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
+
+/*
+ * Map an address to a certain privileged segment
+ */
+#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
+#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
+#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
+#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
+
+#endif /* __ASM_AVR32_ADDRSPACE_H */
--- /dev/null
+/*
+ * Register definition for the High-speed Bus Matrix
+ */
+#ifndef __ASM_AVR32_HMATRIX2_H__
+#define __ASM_AVR32_HMATRIX2_H__
+
+/* HMATRIX2 register offsets */
+#define HMATRIX2_MCFG0 0x0000
+#define HMATRIX2_MCFG1 0x0004
+#define HMATRIX2_MCFG2 0x0008
+#define HMATRIX2_MCFG3 0x000c
+#define HMATRIX2_MCFG4 0x0010
+#define HMATRIX2_MCFG5 0x0014
+#define HMATRIX2_MCFG6 0x0018
+#define HMATRIX2_MCFG7 0x001c
+#define HMATRIX2_MCFG8 0x0020
+#define HMATRIX2_MCFG9 0x0024
+#define HMATRIX2_MCFG10 0x0028
+#define HMATRIX2_MCFG11 0x002c
+#define HMATRIX2_MCFG12 0x0030
+#define HMATRIX2_MCFG13 0x0034
+#define HMATRIX2_MCFG14 0x0038
+#define HMATRIX2_MCFG15 0x003c
+#define HMATRIX2_SCFG0 0x0040
+#define HMATRIX2_SCFG1 0x0044
+#define HMATRIX2_SCFG2 0x0048
+#define HMATRIX2_SCFG3 0x004c
+#define HMATRIX2_SCFG4 0x0050
+#define HMATRIX2_SCFG5 0x0054
+#define HMATRIX2_SCFG6 0x0058
+#define HMATRIX2_SCFG7 0x005c
+#define HMATRIX2_SCFG8 0x0060
+#define HMATRIX2_SCFG9 0x0064
+#define HMATRIX2_SCFG10 0x0068
+#define HMATRIX2_SCFG11 0x006c
+#define HMATRIX2_SCFG12 0x0070
+#define HMATRIX2_SCFG13 0x0074
+#define HMATRIX2_SCFG14 0x0078
+#define HMATRIX2_SCFG15 0x007c
+#define HMATRIX2_PRAS0 0x0080
+#define HMATRIX2_PRBS0 0x0084
+#define HMATRIX2_PRAS1 0x0088
+#define HMATRIX2_PRBS1 0x008c
+#define HMATRIX2_PRAS2 0x0090
+#define HMATRIX2_PRBS2 0x0094
+#define HMATRIX2_PRAS3 0x0098
+#define HMATRIX2_PRBS3 0x009c
+#define HMATRIX2_PRAS4 0x00a0
+#define HMATRIX2_PRBS4 0x00a4
+#define HMATRIX2_PRAS5 0x00a8
+#define HMATRIX2_PRBS5 0x00ac
+#define HMATRIX2_PRAS6 0x00b0
+#define HMATRIX2_PRBS6 0x00b4
+#define HMATRIX2_PRAS7 0x00b8
+#define HMATRIX2_PRBS7 0x00bc
+#define HMATRIX2_PRAS8 0x00c0
+#define HMATRIX2_PRBS8 0x00c4
+#define HMATRIX2_PRAS9 0x00c8
+#define HMATRIX2_PRBS9 0x00cc
+#define HMATRIX2_PRAS10 0x00d0
+#define HMATRIX2_PRBS10 0x00d4
+#define HMATRIX2_PRAS11 0x00d8
+#define HMATRIX2_PRBS11 0x00dc
+#define HMATRIX2_PRAS12 0x00e0
+#define HMATRIX2_PRBS12 0x00e4
+#define HMATRIX2_PRAS13 0x00e8
+#define HMATRIX2_PRBS13 0x00ec
+#define HMATRIX2_PRAS14 0x00f0
+#define HMATRIX2_PRBS14 0x00f4
+#define HMATRIX2_PRAS15 0x00f8
+#define HMATRIX2_PRBS15 0x00fc
+#define HMATRIX2_MRCR 0x0100
+#define HMATRIX2_SFR0 0x0110
+#define HMATRIX2_SFR1 0x0114
+#define HMATRIX2_SFR2 0x0118
+#define HMATRIX2_SFR3 0x011c
+#define HMATRIX2_SFR4 0x0120
+#define HMATRIX2_SFR5 0x0124
+#define HMATRIX2_SFR6 0x0128
+#define HMATRIX2_SFR7 0x012c
+#define HMATRIX2_SFR8 0x0130
+#define HMATRIX2_SFR9 0x0134
+#define HMATRIX2_SFR10 0x0138
+#define HMATRIX2_SFR11 0x013c
+#define HMATRIX2_SFR12 0x0140
+#define HMATRIX2_SFR13 0x0144
+#define HMATRIX2_SFR14 0x0148
+#define HMATRIX2_SFR15 0x014c
+#define HMATRIX2_VERSION 0x01fc
+
+/* Bitfields in MCFG0 */
+#define HMATRIX2_ULBT_OFFSET 0
+#define HMATRIX2_ULBT_SIZE 3
+
+/* Bitfields in SCFG0 */
+#define HMATRIX2_SLOT_CYCLE_OFFSET 0
+#define HMATRIX2_SLOT_CYCLE_SIZE 8
+#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
+#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
+#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
+#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
+#define HMATRIX2_ARBT_OFFSET 24
+#define HMATRIX2_ARBT_SIZE 2
+
+/* Bitfields in PRAS0 */
+#define HMATRIX2_M0PR_OFFSET 0
+#define HMATRIX2_M0PR_SIZE 4
+#define HMATRIX2_M1PR_OFFSET 4
+#define HMATRIX2_M1PR_SIZE 4
+#define HMATRIX2_M2PR_OFFSET 8
+#define HMATRIX2_M2PR_SIZE 4
+#define HMATRIX2_M3PR_OFFSET 12
+#define HMATRIX2_M3PR_SIZE 4
+#define HMATRIX2_M4PR_OFFSET 16
+#define HMATRIX2_M4PR_SIZE 4
+#define HMATRIX2_M5PR_OFFSET 20
+#define HMATRIX2_M5PR_SIZE 4
+#define HMATRIX2_M6PR_OFFSET 24
+#define HMATRIX2_M6PR_SIZE 4
+#define HMATRIX2_M7PR_OFFSET 28
+#define HMATRIX2_M7PR_SIZE 4
+
+/* Bitfields in PRBS0 */
+#define HMATRIX2_M8PR_OFFSET 0
+#define HMATRIX2_M8PR_SIZE 4
+#define HMATRIX2_M9PR_OFFSET 4
+#define HMATRIX2_M9PR_SIZE 4
+#define HMATRIX2_M10PR_OFFSET 8
+#define HMATRIX2_M10PR_SIZE 4
+#define HMATRIX2_M11PR_OFFSET 12
+#define HMATRIX2_M11PR_SIZE 4
+#define HMATRIX2_M12PR_OFFSET 16
+#define HMATRIX2_M12PR_SIZE 4
+#define HMATRIX2_M13PR_OFFSET 20
+#define HMATRIX2_M13PR_SIZE 4
+#define HMATRIX2_M14PR_OFFSET 24
+#define HMATRIX2_M14PR_SIZE 4
+#define HMATRIX2_M15PR_OFFSET 28
+#define HMATRIX2_M15PR_SIZE 4
+
+/* Bitfields in MRCR */
+#define HMATRIX2_RBC0_OFFSET 0
+#define HMATRIX2_RBC0_SIZE 1
+#define HMATRIX2_RBC1_OFFSET 1
+#define HMATRIX2_RBC1_SIZE 1
+#define HMATRIX2_RBC2_OFFSET 2
+#define HMATRIX2_RBC2_SIZE 1
+#define HMATRIX2_RBC3_OFFSET 3
+#define HMATRIX2_RBC3_SIZE 1
+#define HMATRIX2_RBC4_OFFSET 4
+#define HMATRIX2_RBC4_SIZE 1
+#define HMATRIX2_RBC5_OFFSET 5
+#define HMATRIX2_RBC5_SIZE 1
+#define HMATRIX2_RBC6_OFFSET 6
+#define HMATRIX2_RBC6_SIZE 1
+#define HMATRIX2_RBC7_OFFSET 7
+#define HMATRIX2_RBC7_SIZE 1
+#define HMATRIX2_RBC8_OFFSET 8
+#define HMATRIX2_RBC8_SIZE 1
+#define HMATRIX2_RBC9_OFFSET 9
+#define HMATRIX2_RBC9_SIZE 1
+#define HMATRIX2_RBC10_OFFSET 10
+#define HMATRIX2_RBC10_SIZE 1
+#define HMATRIX2_RBC11_OFFSET 11
+#define HMATRIX2_RBC11_SIZE 1
+#define HMATRIX2_RBC12_OFFSET 12
+#define HMATRIX2_RBC12_SIZE 1
+#define HMATRIX2_RBC13_OFFSET 13
+#define HMATRIX2_RBC13_SIZE 1
+#define HMATRIX2_RBC14_OFFSET 14
+#define HMATRIX2_RBC14_SIZE 1
+#define HMATRIX2_RBC15_OFFSET 15
+#define HMATRIX2_RBC15_SIZE 1
+
+/* Bitfields in SFR0 */
+#define HMATRIX2_SFR_OFFSET 0
+#define HMATRIX2_SFR_SIZE 32
+
+/* Bitfields in SFR4 */
+#define HMATRIX2_CS1A_OFFSET 1
+#define HMATRIX2_CS1A_SIZE 1
+#define HMATRIX2_CS3A_OFFSET 3
+#define HMATRIX2_CS3A_SIZE 1
+#define HMATRIX2_CS4A_OFFSET 4
+#define HMATRIX2_CS4A_SIZE 1
+#define HMATRIX2_CS5A_OFFSET 5
+#define HMATRIX2_CS5A_SIZE 1
+#define HMATRIX2_DBPUC_OFFSET 8
+#define HMATRIX2_DBPUC_SIZE 1
+
+/* Bitfields in VERSION */
+#define HMATRIX2_VERSION_OFFSET 0
+#define HMATRIX2_VERSION_SIZE 12
+#define HMATRIX2_MFN_OFFSET 16
+#define HMATRIX2_MFN_SIZE 3
+
+/* Constants for ULBT */
+#define HMATRIX2_ULBT_INFINITE 0
+#define HMATRIX2_ULBT_SINGLE 1
+#define HMATRIX2_ULBT_FOUR_BEAT 2
+#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
+#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
+#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
+
+/* Constants for ARBT */
+#define HMATRIX2_ARBT_ROUND_ROBIN 0
+#define HMATRIX2_ARBT_FIXED_PRIORITY 1
+
+/* Bit manipulation macros */
+#define HMATRIX2_BIT(name) \
+ (1 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BF(name,value) \
+ (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
+ << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BFEXT(name,value) \
+ (((value) >> HMATRIX2_##name##_OFFSET) \
+ & ((1 << HMATRIX2_##name##_SIZE) - 1))
+#define HMATRIX2_BFINS(name,value,old) \
+ (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
+ << HMATRIX2_##name##_OFFSET)) \
+ | HMATRIX2_BF(name,value))
+
+/* Register access macros */
+#define hmatrix2_readl(port,reg) \
+ readl((port)->regs + HMATRIX2_##reg)
+#define hmatrix2_writel(port,reg,value) \
+ writel((value), (port)->regs + HMATRIX2_##reg)
+
+#endif /* __ASM_AVR32_HMATRIX2_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
+#define __ASM_AVR32_PART_MEMORY_MAP_H__
+
+#define AUDIOC_BASE 0xFFF02800
+#define DAC_BASE 0xFFF02000
+#define DMAC_BASE 0xFF200000
+#define ECC_BASE 0xFFF03C00
+#define HISI_BASE 0xFFF02C00
+#define HMATRIX_BASE 0xFFF00800
+#define HSDRAMC_BASE 0xFFF03800
+#define HSMC_BASE 0xFFF03400
+#define LCDC_BASE 0xFF000000
+#define MACB0_BASE 0xFFF01800
+#define MACB1_BASE 0xFFF01C00
+#define MMCI_BASE 0xFFF02400
+#define PIOA_BASE 0xFFE02800
+#define PIOB_BASE 0xFFE02C00
+#define PIOC_BASE 0xFFE03000
+#define PIOD_BASE 0xFFE03400
+#define PIOE_BASE 0xFFE03800
+#define PSIF_BASE 0xFFE03C00
+#define PWM_BASE 0xFFF01400
+#define SM_BASE 0xFFF00000
+#define INTC_BASE 0XFFF00400
+#define SPI0_BASE 0xFFE00000
+#define SPI1_BASE 0xFFE00400
+#define SSC0_BASE 0xFFE01C00
+#define SSC1_BASE 0xFFE02000
+#define SSC2_BASE 0xFFE02400
+#define TIMER0_BASE 0xFFF00C00
+#define TIMER1_BASE 0xFFF01000
+#define TWI_BASE 0xFFE00800
+#define USART0_BASE 0xFFE00C00
+#define USART1_BASE 0xFFE01000
+#define USART2_BASE 0xFFE01400
+#define USART3_BASE 0xFFE01800
+#define USB_FIFO 0xFF300000
+#define USB_BASE 0xFFF03000
+
+#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_AVR32_ARCH_PM_H
+#define _ASM_AVR32_ARCH_PM_H
+
+#include <config.h>
+
+enum clock_domain_id {
+ CLOCK_CPU,
+ CLOCK_HSB,
+ CLOCK_PBA,
+ CLOCK_PBB,
+ NR_CLOCK_DOMAINS,
+};
+
+enum resource_type {
+ RESOURCE_GPIO,
+ RESOURCE_CLOCK,
+};
+
+enum gpio_func {
+ GPIO_FUNC_GPIO,
+ GPIO_FUNC_A,
+ GPIO_FUNC_B,
+};
+
+enum device_id {
+ DEVICE_HEBI,
+ DEVICE_PBA_BRIDGE,
+ DEVICE_PBB_BRIDGE,
+ DEVICE_HRAMC,
+ /* GPIO controllers must be kept together */
+ DEVICE_PIOA,
+ DEVICE_PIOB,
+ DEVICE_PIOC,
+ DEVICE_PIOD,
+ DEVICE_PIOE,
+ DEVICE_SM,
+ DEVICE_INTC,
+ DEVICE_HMATRIX,
+#if defined(CFG_HPDC)
+ DEVICE_HPDC,
+#endif
+#if defined(CFG_MACB0)
+ DEVICE_MACB0,
+#endif
+#if defined(CFG_MACB1)
+ DEVICE_MACB1,
+#endif
+#if defined(CFG_LCDC)
+ DEVICE_LCDC,
+#endif
+#if defined(CFG_USART0)
+ DEVICE_USART0,
+#endif
+#if defined(CFG_USART1)
+ DEVICE_USART1,
+#endif
+#if defined(CFG_USART2)
+ DEVICE_USART2,
+#endif
+#if defined(CFG_USART3)
+ DEVICE_USART3,
+#endif
+#if defined(CFG_MMCI)
+ DEVICE_MMCI,
+#endif
+#if defined(CFG_DMAC)
+ DEVICE_DMAC,
+#endif
+ NR_DEVICES,
+ NO_DEVICE = -1,
+};
+
+struct resource {
+ enum resource_type type;
+ union {
+ struct {
+ unsigned long base;
+ } iomem;
+ struct {
+ unsigned char nr_pins;
+ enum device_id gpio_dev;
+ enum gpio_func func;
+ unsigned short start;
+ } gpio;
+ struct {
+ enum clock_domain_id id;
+ unsigned char index;
+ } clock;
+ } u;
+};
+
+struct device {
+ void *regs;
+ unsigned int nr_resources;
+ const struct resource *resource;
+};
+
+struct clock_domain {
+ unsigned short reg;
+ enum clock_domain_id id;
+ enum device_id bridge;
+};
+
+extern const struct device chip_device[NR_DEVICES];
+extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
+
+/**
+ * Set up PIO, clock management and I/O memory for a device.
+ */
+const struct device *get_device(enum device_id devid);
+void put_device(const struct device *dev);
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins, enum gpio_func func);
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins);
+
+void pm_init(void);
+int pm_enable_clock(enum clock_domain_id id, unsigned int index);
+void pm_disable_clock(enum clock_domain_id id, unsigned int index);
+unsigned long pm_get_clock_freq(enum clock_domain_id domain);
+
+void cpu_enable_sdram(void);
+
+#endif /* _ASM_AVR32_ARCH_PM_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BITOPS_H
+#define __ASM_AVR32_BITOPS_H
+
+#endif /* __ASM_AVR32_BITOPS_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BYTEORDER_H
+#define __ASM_AVR32_BYTEORDER_H
+
+#include <asm/types.h>
+
+#define __arch__swab32(x) __builtin_bswap_32(x)
+#define __arch__swab16(x) __builtin_bswap_16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* __ASM_AVR32_BYTEORDER_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_CACHEFLUSH_H
+#define __ASM_AVR32_CACHEFLUSH_H
+
+/*
+ * Invalidate any cacheline containing virtual address vaddr without
+ * writing anything back to memory.
+ *
+ * Note that this function may corrupt unrelated data structures when
+ * applied on buffers that are not cacheline aligned in both ends.
+ */
+static inline void dcache_invalidate_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory.
+ */
+static inline void dcache_clean_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory and then invalidate it.
+ */
+static inline void dcache_flush_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Invalidate any instruction cacheline containing virtual address
+ * vaddr.
+ */
+static inline void icache_invalidate_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Applies the above functions on all lines that are touched by the
+ * specified virtual address range.
+ */
+void dcache_invalidate_range(volatile void *start, size_t len);
+void dcache_clean_range(volatile void *start, size_t len);
+void dcache_flush_range(volatile void *start, size_t len);
+void icache_invalidate_range(volatile void *start, size_t len);
+
+static inline void dcache_flush_unlocked(void)
+{
+ asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
+}
+
+/*
+ * Make sure any pending writes are completed before continuing.
+ */
+#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
+
+#endif /* __ASM_AVR32_CACHEFLUSH_H */
--- /dev/null
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ * uint32_t remainder = *n % base;
+ * *n = *n / base;
+ * return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ * beware of side effects!
+ */
+
+#include <linux/types.h>
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({ \
+ uint32_t __base = (base); \
+ uint32_t __rem; \
+ (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
+ if (((n) >> 32) == 0) { \
+ __rem = (uint32_t)(n) % __base; \
+ (n) = (uint32_t)(n) / __base; \
+ } else \
+ __rem = __div64_32(&(n), __base); \
+ __rem; \
+ })
+
+#endif /* _ASM_GENERIC_DIV64_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_DMA_MAPPING_H
+#define __ASM_AVR32_DMA_MAPPING_H
+
+#include <asm/io.h>
+#include <asm/cacheflush.h>
+
+enum dma_data_direction {
+ DMA_BIDIRECTIONAL = 0,
+ DMA_TO_DEVICE = 1,
+ DMA_FROM_DEVICE = 2,
+};
+extern void *dma_alloc_coherent(size_t len, unsigned long *handle);
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ extern void __bad_dma_data_direction(void);
+
+ switch (dir) {
+ case DMA_BIDIRECTIONAL:
+ dcache_flush_range(vaddr, len);
+ break;
+ case DMA_TO_DEVICE:
+ dcache_clean_range(vaddr, len);
+ break;
+ case DMA_FROM_DEVICE:
+ dcache_invalidate_range(vaddr, len);
+ break;
+ default:
+ /* This will cause a linker error */
+ __bad_dma_data_direction();
+ }
+
+ return virt_to_phys(vaddr);
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+ unsigned long paddr)
+{
+
+}
+
+#endif /* __ASM_AVR32_DMA_MAPPING_H */
--- /dev/null
+#ifndef _ASM_AVR32_ERRNO_H
+#define _ASM_AVR32_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Argument list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+#endif /* _ASM_AVR32_ERRNO_H */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_GLOBAL_DATA_H__
+#define __ASM_GLOBAL_DATA_H__
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef struct global_data {
+ bd_t *bd;
+ unsigned long flags;
+ const struct device *console_uart;
+ const struct device *sm;
+ unsigned long baudrate;
+ unsigned long sdram_size;
+ unsigned long have_console; /* serial_init() was called */
+ unsigned long reloc_off; /* Relocation Offset */
+ unsigned long env_addr; /* Address of env struct */
+ unsigned long env_valid; /* Checksum of env valid? */
+ unsigned long cpu_hz; /* cpu core clock frequency */
+ void **jt; /* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
+#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+#define GD_FLG_SILENT 0x00004 /* Silent mode */
+
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
+
+#endif /* __ASM_GLOBAL_DATA_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005, 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_INITCALLS_H__
+#define __ASM_AVR32_INITCALLS_H__
+
+#include <config.h>
+
+extern int cpu_init(void);
+extern int timer_init(void);
+extern void board_init_memories(void);
+extern void board_init_pio(void);
+extern void board_init_info(void);
+
+#endif /* __ASM_AVR32_INITCALLS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_IO_H
+#define __ASM_AVR32_IO_H
+
+#ifdef __KERNEL__
+
+/*
+ * Generic IO read/write. These perform native-endian accesses. Note
+ * that some architectures will want to re-define __raw_{read,write}w.
+ */
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#define __raw_readb(a) (*(volatile unsigned char *)(a))
+#define __raw_readw(a) (*(volatile unsigned short *)(a))
+#define __raw_readl(a) (*(volatile unsigned int *)(a))
+
+/* As long as I/O is only performed in P4 (or possibly P3), we're safe */
+#define writeb(v,a) __raw_writeb(v,a)
+#define writew(v,a) __raw_writew(v,a)
+#define writel(v,a) __raw_writel(v,a)
+
+#define readb(a) __raw_readb(a)
+#define readw(a) __raw_readw(a)
+#define readl(a) __raw_readl(a)
+
+/*
+ * Bad read/write accesses...
+ */
+extern void __readwrite_bug(const char *fn);
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * All I/O is memory mapped, so these macros doesn't make very much sense
+ */
+#define outb(v,p) __raw_writeb(v, p)
+#define outw(v,p) __raw_writew(cpu_to_le16(v),p)
+#define outl(v,p) __raw_writel(cpu_to_le32(v),p)
+
+#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#include <asm/addrspace.h>
+
+/* virt_to_phys will only work when address is in P1 or P2 */
+static __inline__ unsigned long virt_to_phys(volatile void *address)
+{
+ return PHYSADDR(address);
+}
+
+static __inline__ void * phys_to_virt(unsigned long address)
+{
+ return (void *)P1SEGADDR(address);
+}
+
+#define cached(addr) ((void *)P1SEGADDR(addr))
+#define uncached(addr) ((void *)P2SEGADDR(addr))
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_AVR32_IO_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_POSIX_TYPES_H
+#define __ASM_AVR32_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef unsigned long __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef unsigned short __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+ unsigned long *__tmp = __p->fds_bits;
+ int __i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 16:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ __tmp[ 8] = 0; __tmp[ 9] = 0;
+ __tmp[10] = 0; __tmp[11] = 0;
+ __tmp[12] = 0; __tmp[13] = 0;
+ __tmp[14] = 0; __tmp[15] = 0;
+ return;
+
+ case 8:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ return;
+
+ case 4:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ return;
+ }
+ }
+ __i = __FDSET_LONGS;
+ while (__i) {
+ __i--;
+ *__tmp = 0;
+ __tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* __ASM_AVR32_POSIX_TYPES_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PROCESSOR_H
+#define __ASM_AVR32_PROCESSOR_H
+
+#ifndef __ASSEMBLY__
+
+#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; })
+
+struct avr32_cpuinfo {
+ unsigned long loops_per_jiffy;
+};
+
+extern struct avr32_cpuinfo boot_cpu_data;
+
+#ifdef CONFIG_SMP
+extern struct avr32_cpuinfo cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#else
+#define cpu_data (&boot_cpu_data)
+#define current_cpu_data boot_cpu_data
+#endif
+
+/* TODO: Make configurable (2GB will serve as a reasonable default) */
+#define TASK_SIZE 0x80000000
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+#define cpu_relax() barrier()
+#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory")
+
+/* This struct contains the CPU context as stored by switch_to() */
+struct thread_struct {
+ unsigned long pc;
+ unsigned long ksp; /* Kernel stack pointer */
+ unsigned long r7;
+ unsigned long r6;
+ unsigned long r5;
+ unsigned long r4;
+ unsigned long r3;
+ unsigned long r2;
+ unsigned long r1;
+ unsigned long r0;
+};
+
+#define INIT_THREAD { \
+ .ksp = sizeof(init_stack) + (long)&init_stack, \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define start_thread(regs, new_pc, new_sp) \
+ set_fs(USER_DS); \
+ regs->sr = 0; /* User mode. */ \
+ regs->gr[REG_PC] = new_pc; \
+ regs->gr[REG_SP] = new_sp
+
+struct task_struct;
+
+/* Free all resources held by a thread */
+extern void release_thread(struct task_struct *);
+
+/* Create a kernel thread without removing it from tasklists */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk) do { } while(0)
+
+/* Return saved PC of a blocked thread */
+#define thread_saved_pc(tsk) (tsk->thread.pc)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PROCESSOR_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PTRACE_H
+#define __ASM_AVR32_PTRACE_H
+
+/*
+ * Status Register bits
+ */
+#define SR_H 0x40000000
+#define SR_R 0x20000000
+#define SR_J 0x10000000
+#define SR_DM 0x08000000
+#define SR_D 0x04000000
+#define MODE_NMI 0x01c00000
+#define MODE_EXCEPTION 0x01800000
+#define MODE_INT3 0x01400000
+#define MODE_INT2 0x01000000
+#define MODE_INT1 0x00c00000
+#define MODE_INT0 0x00800000
+#define MODE_SUPERVISOR 0x00400000
+#define MODE_USER 0x00000000
+#define MODE_MASK 0x01c00000
+#define SR_EM 0x00200000
+#define SR_I3M 0x00100000
+#define SR_I2M 0x00080000
+#define SR_I1M 0x00040000
+#define SR_I0M 0x00020000
+#define SR_GM 0x00010000
+
+#define MODE_SHIFT 22
+#define SR_EM_BIT 21
+#define SR_I3M_BIT 20
+#define SR_I2M_BIT 19
+#define SR_I1M_BIT 18
+#define SR_I0M_BIT 17
+#define SR_GM_BIT 16
+
+/* The user-visible part */
+#define SR_Q 0x00000010
+#define SR_V 0x00000008
+#define SR_N 0x00000004
+#define SR_Z 0x00000002
+#define SR_C 0x00000001
+
+/*
+ * The order is defined by the stdsp instruction. r0 is stored first, so it
+ * gets the highest address.
+ *
+ * Registers 0-12 are general-purpose registers (r12 is normally used for
+ * the function return value).
+ * Register 13 is the stack pointer
+ * Register 14 is the link register
+ * Register 15 is the program counter
+ */
+#define FRAME_SIZE_FULL 72
+#define REG_R12_ORIG 68
+#define REG_R0 64
+#define REG_R1 60
+#define REG_R2 56
+#define REG_R3 52
+#define REG_R4 48
+#define REG_R5 44
+#define REG_R6 40
+#define REG_R7 36
+#define REG_R8 32
+#define REG_R9 28
+#define REG_R10 34
+#define REG_R11 20
+#define REG_R12 16
+#define REG_SP 12
+#define REG_LR 8
+
+#define FRAME_SIZE_MIN 8
+#define REG_PC 4
+#define REG_SR 0
+
+#ifndef __ASSEMBLY__
+struct pt_regs {
+ /* These are always saved */
+ unsigned long sr;
+ unsigned long pc;
+
+ /* These are sometimes saved */
+ unsigned long lr;
+ unsigned long sp;
+ unsigned long r12;
+ unsigned long r11;
+ unsigned long r10;
+ unsigned long r9;
+ unsigned long r8;
+ unsigned long r7;
+ unsigned long r6;
+ unsigned long r5;
+ unsigned long r4;
+ unsigned long r3;
+ unsigned long r2;
+ unsigned long r1;
+ unsigned long r0;
+
+ /* Only saved on system call */
+ unsigned long r12_orig;
+};
+
+#ifdef __KERNEL__
+# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+# define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs (struct pt_regs *);
+
+static __inline__ int valid_user_regs(struct pt_regs *regs)
+{
+ /*
+ * Some of the Java bits might be acceptable if/when we
+ * implement some support for that stuff...
+ */
+ if ((regs->sr & 0xffff0000) == 0)
+ return 1;
+
+ /*
+ * Force status register flags to be sane and report this
+ * illegal behaviour...
+ */
+ regs->sr &= 0x0000ffff;
+ return 0;
+}
+#endif
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PTRACE_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SDRAM_H
+#define __ASM_AVR32_SDRAM_H
+
+struct sdram_info {
+ unsigned long phys_addr;
+ unsigned int row_bits, col_bits, bank_bits;
+ unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+};
+
+extern unsigned long sdram_init(const struct sdram_info *info);
+
+#endif /* __ASM_AVR32_SDRAM_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SECTIONS_H
+#define __ASM_AVR32_SECTIONS_H
+
+/* References to section boundaries */
+
+extern char _text[], _etext[];
+extern char __flashprog_start[], __flashprog_end[];
+extern char _data[], __data_lma[], _edata[], __edata_lma[];
+extern char __got_start[], __got_lma[], __got_end[];
+extern char _end[];
+
+/*
+ * Everything in .flashprog will be locked in the icache so it doesn't
+ * get disturbed when executing flash commands.
+ */
+#define __flashprog __attribute__((section(".flashprog"), __noinline__))
+
+#endif /* __ASM_AVR32_SECTIONS_H */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * Based on linux/include/asm-arm/setup.h
+ * Copyright (C) 1997-1999 Russel King
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SETUP_H__
+#define __ASM_AVR32_SETUP_H__
+
+#define COMMAND_LINE_SIZE 256
+
+/* Magic number indicating that a tag table is present */
+#define ATAG_MAGIC 0xa2a25441
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Generic memory range, used by several tags.
+ *
+ * addr is always physical.
+ * size is measured in bytes.
+ * next is for use by the OS, e.g. for grouping regions into
+ * linked lists.
+ */
+struct tag_mem_range {
+ u32 addr;
+ u32 size;
+ struct tag_mem_range * next;
+};
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE 0x00000000
+
+struct tag_header {
+ u32 size;
+ u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE 0x54410001
+
+struct tag_core {
+ u32 flags;
+ u32 pagesize;
+ u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM 0x54410002
+/* ATAG_MEM uses tag_mem_range */
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE 0x54410003
+
+struct tag_cmdline {
+ char cmdline[1]; /* this is the minimum size */
+};
+
+/* Ramdisk image (may be compressed) */
+#define ATAG_RDIMG 0x54410004
+/* ATAG_RDIMG uses tag_mem_range */
+
+/* Information about various clocks present in the system */
+#define ATAG_CLOCK 0x54410005
+
+struct tag_clock {
+ u32 clock_id; /* Which clock are we talking about? */
+ u32 clock_flags; /* Special features */
+ u64 clock_hz; /* Clock speed in Hz */
+};
+
+/* The clock types we know about */
+#define ACLOCK_BOOTCPU 0 /* The CPU we're booting from */
+#define ACLOCK_HSB 1 /* Deprecated */
+
+/* Memory reserved for the system (e.g. the bootloader) */
+#define ATAG_RSVD_MEM 0x54410006
+/* ATAG_RSVD_MEM uses tag_mem_range */
+
+/* Ethernet information */
+
+#define ATAG_ETHERNET 0x54410007
+
+struct tag_ethernet {
+ u8 mac_index;
+ u8 mii_phy_addr;
+ u8 hw_address[6];
+};
+
+#define AETH_INVALID_PHY 0xff
+
+struct tag {
+ struct tag_header hdr;
+ union {
+ struct tag_core core;
+ struct tag_mem_range mem_range;
+ struct tag_cmdline cmdline;
+ struct tag_clock clock;
+ struct tag_ethernet ethernet;
+ } u;
+};
+
+struct tagtable {
+ u32 tag;
+ int (*parse)(struct tag *);
+};
+
+#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
+#define __tagtable(tag, fn) \
+ static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member) \
+ ((unsigned long)(&((struct tag *)0L)->member + 1) \
+ <= (tag)->hdr.size * 4)
+
+#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base) \
+ for (t = base; t->hdr.size; t = tag_next(t))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_SETUP_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_STRING_H
+#define __ASM_AVR32_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *s, int c, size_t n);
+
+#endif /* __ASM_AVR32_STRING_H */
--- /dev/null
+/*
+ * System registers for AVR32
+ */
+#ifndef __ASM_AVR32_SYSREG_H__
+#define __ASM_AVR32_SYSREG_H__
+
+/* system register offsets */
+#define SYSREG_SR 0x0000
+#define SYSREG_EVBA 0x0004
+#define SYSREG_ACBA 0x0008
+#define SYSREG_CPUCR 0x000c
+#define SYSREG_ECR 0x0010
+#define SYSREG_RSR_SUP 0x0014
+#define SYSREG_RSR_INT0 0x0018
+#define SYSREG_RSR_INT1 0x001c
+#define SYSREG_RSR_INT2 0x0020
+#define SYSREG_RSR_INT3 0x0024
+#define SYSREG_RSR_EX 0x0028
+#define SYSREG_RSR_NMI 0x002c
+#define SYSREG_RSR_DBG 0x0030
+#define SYSREG_RAR_SUP 0x0034
+#define SYSREG_RAR_INT0 0x0038
+#define SYSREG_RAR_INT1 0x003c
+#define SYSREG_RAR_INT2 0x0040
+#define SYSREG_RAR_INT3 0x0044
+#define SYSREG_RAR_EX 0x0048
+#define SYSREG_RAR_NMI 0x004c
+#define SYSREG_RAR_DBG 0x0050
+#define SYSREG_JECR 0x0054
+#define SYSREG_JOSP 0x0058
+#define SYSREG_JAVA_LV0 0x005c
+#define SYSREG_JAVA_LV1 0x0060
+#define SYSREG_JAVA_LV2 0x0064
+#define SYSREG_JAVA_LV3 0x0068
+#define SYSREG_JAVA_LV4 0x006c
+#define SYSREG_JAVA_LV5 0x0070
+#define SYSREG_JAVA_LV6 0x0074
+#define SYSREG_JAVA_LV7 0x0078
+#define SYSREG_JTBA 0x007c
+#define SYSREG_JBCR 0x0080
+#define SYSREG_CONFIG0 0x0100
+#define SYSREG_CONFIG1 0x0104
+#define SYSREG_COUNT 0x0108
+#define SYSREG_COMPARE 0x010c
+#define SYSREG_TLBEHI 0x0110
+#define SYSREG_TLBELO 0x0114
+#define SYSREG_PTBR 0x0118
+#define SYSREG_TLBEAR 0x011c
+#define SYSREG_MMUCR 0x0120
+#define SYSREG_TLBARLO 0x0124
+#define SYSREG_TLBARHI 0x0128
+#define SYSREG_PCCNT 0x012c
+#define SYSREG_PCNT0 0x0130
+#define SYSREG_PCNT1 0x0134
+#define SYSREG_PCCR 0x0138
+#define SYSREG_BEAR 0x013c
+#define SYSREG_SABAL 0x0300
+#define SYSREG_SABAH 0x0304
+#define SYSREG_SABD 0x0308
+
+/* Bitfields in SR */
+#define SYSREG_SR_C_OFFSET 0
+#define SYSREG_SR_C_SIZE 1
+#define SYSREG_Z_OFFSET 1
+#define SYSREG_Z_SIZE 1
+#define SYSREG_SR_N_OFFSET 2
+#define SYSREG_SR_N_SIZE 1
+#define SYSREG_SR_V_OFFSET 3
+#define SYSREG_SR_V_SIZE 1
+#define SYSREG_Q_OFFSET 4
+#define SYSREG_Q_SIZE 1
+#define SYSREG_L_OFFSET 5
+#define SYSREG_L_SIZE 1
+#define SYSREG_T_OFFSET 14
+#define SYSREG_T_SIZE 1
+#define SYSREG_SR_R_OFFSET 15
+#define SYSREG_SR_R_SIZE 1
+#define SYSREG_GM_OFFSET 16
+#define SYSREG_GM_SIZE 1
+#define SYSREG_I0M_OFFSET 17
+#define SYSREG_I0M_SIZE 1
+#define SYSREG_I1M_OFFSET 18
+#define SYSREG_I1M_SIZE 1
+#define SYSREG_I2M_OFFSET 19
+#define SYSREG_I2M_SIZE 1
+#define SYSREG_I3M_OFFSET 20
+#define SYSREG_I3M_SIZE 1
+#define SYSREG_EM_OFFSET 21
+#define SYSREG_EM_SIZE 1
+#define SYSREG_M0_OFFSET 22
+#define SYSREG_M0_SIZE 1
+#define SYSREG_M1_OFFSET 23
+#define SYSREG_M1_SIZE 1
+#define SYSREG_M2_OFFSET 24
+#define SYSREG_M2_SIZE 1
+#define SYSREG_SR_D_OFFSET 26
+#define SYSREG_SR_D_SIZE 1
+#define SYSREG_DM_OFFSET 27
+#define SYSREG_DM_SIZE 1
+#define SYSREG_SR_J_OFFSET 28
+#define SYSREG_SR_J_SIZE 1
+#define SYSREG_H_OFFSET 29
+#define SYSREG_H_SIZE 1
+
+/* Bitfields in CPUCR */
+#define SYSREG_BI_OFFSET 0
+#define SYSREG_BI_SIZE 1
+#define SYSREG_BE_OFFSET 1
+#define SYSREG_BE_SIZE 1
+#define SYSREG_FE_OFFSET 2
+#define SYSREG_FE_SIZE 1
+#define SYSREG_RE_OFFSET 3
+#define SYSREG_RE_SIZE 1
+#define SYSREG_IBE_OFFSET 4
+#define SYSREG_IBE_SIZE 1
+#define SYSREG_IEE_OFFSET 5
+#define SYSREG_IEE_SIZE 1
+
+/* Bitfields in ECR */
+#define SYSREG_ECR_OFFSET 0
+#define SYSREG_ECR_SIZE 32
+
+/* Bitfields in CONFIG0 */
+#define SYSREG_CONFIG0_R_OFFSET 0
+#define SYSREG_CONFIG0_R_SIZE 1
+#define SYSREG_CONFIG0_D_OFFSET 1
+#define SYSREG_CONFIG0_D_SIZE 1
+#define SYSREG_CONFIG0_S_OFFSET 2
+#define SYSREG_CONFIG0_S_SIZE 1
+#define SYSREG_O_OFFSET 3
+#define SYSREG_O_SIZE 1
+#define SYSREG_P_OFFSET 4
+#define SYSREG_P_SIZE 1
+#define SYSREG_CONFIG0_J_OFFSET 5
+#define SYSREG_CONFIG0_J_SIZE 1
+#define SYSREG_F_OFFSET 6
+#define SYSREG_F_SIZE 1
+#define SYSREG_MMUT_OFFSET 7
+#define SYSREG_MMUT_SIZE 3
+#define SYSREG_AR_OFFSET 10
+#define SYSREG_AR_SIZE 3
+#define SYSREG_AT_OFFSET 13
+#define SYSREG_AT_SIZE 3
+#define SYSREG_PROCESSORREVISION_OFFSET 16
+#define SYSREG_PROCESSORREVISION_SIZE 8
+#define SYSREG_PROCESSORID_OFFSET 24
+#define SYSREG_PROCESSORID_SIZE 8
+
+/* Bitfields in CONFIG1 */
+#define SYSREG_DASS_OFFSET 0
+#define SYSREG_DASS_SIZE 3
+#define SYSREG_DLSZ_OFFSET 3
+#define SYSREG_DLSZ_SIZE 3
+#define SYSREG_DSET_OFFSET 6
+#define SYSREG_DSET_SIZE 4
+#define SYSREG_IASS_OFFSET 10
+#define SYSREG_IASS_SIZE 3
+#define SYSREG_ILSZ_OFFSET 13
+#define SYSREG_ILSZ_SIZE 3
+#define SYSREG_ISET_OFFSET 16
+#define SYSREG_ISET_SIZE 4
+#define SYSREG_DMMUSZ_OFFSET 20
+#define SYSREG_DMMUSZ_SIZE 6
+#define SYSREG_IMMUSZ_OFFSET 26
+#define SYSREG_IMMUSZ_SIZE 6
+
+/* Bitfields in TLBEHI */
+#define SYSREG_ASID_OFFSET 0
+#define SYSREG_ASID_SIZE 8
+#define SYSREG_TLBEHI_I_OFFSET 8
+#define SYSREG_TLBEHI_I_SIZE 1
+#define SYSREG_TLBEHI_V_OFFSET 9
+#define SYSREG_TLBEHI_V_SIZE 1
+#define SYSREG_VPN_OFFSET 10
+#define SYSREG_VPN_SIZE 22
+
+/* Bitfields in TLBELO */
+#define SYSREG_W_OFFSET 0
+#define SYSREG_W_SIZE 1
+#define SYSREG_TLBELO_D_OFFSET 1
+#define SYSREG_TLBELO_D_SIZE 1
+#define SYSREG_SZ_OFFSET 2
+#define SYSREG_SZ_SIZE 2
+#define SYSREG_AP_OFFSET 4
+#define SYSREG_AP_SIZE 3
+#define SYSREG_B_OFFSET 7
+#define SYSREG_B_SIZE 1
+#define SYSREG_G_OFFSET 8
+#define SYSREG_G_SIZE 1
+#define SYSREG_TLBELO_C_OFFSET 9
+#define SYSREG_TLBELO_C_SIZE 1
+#define SYSREG_PFN_OFFSET 10
+#define SYSREG_PFN_SIZE 22
+
+/* Bitfields in MMUCR */
+#define SYSREG_E_OFFSET 0
+#define SYSREG_E_SIZE 1
+#define SYSREG_M_OFFSET 1
+#define SYSREG_M_SIZE 1
+#define SYSREG_MMUCR_I_OFFSET 2
+#define SYSREG_MMUCR_I_SIZE 1
+#define SYSREG_MMUCR_N_OFFSET 3
+#define SYSREG_MMUCR_N_SIZE 1
+#define SYSREG_MMUCR_S_OFFSET 4
+#define SYSREG_MMUCR_S_SIZE 1
+#define SYSREG_DLA_OFFSET 8
+#define SYSREG_DLA_SIZE 6
+#define SYSREG_DRP_OFFSET 14
+#define SYSREG_DRP_SIZE 6
+#define SYSREG_ILA_OFFSET 20
+#define SYSREG_ILA_SIZE 6
+#define SYSREG_IRP_OFFSET 26
+#define SYSREG_IRP_SIZE 6
+
+/* Bitfields in PCCR */
+#define SYSREG_PCCR_R_OFFSET 1
+#define SYSREG_PCCR_R_SIZE 1
+#define SYSREG_PCCR_C_OFFSET 2
+#define SYSREG_PCCR_C_SIZE 1
+#define SYSREG_PCCR_S_OFFSET 3
+#define SYSREG_PCCR_S_SIZE 1
+#define SYSREG_IEC_OFFSET 4
+#define SYSREG_IEC_SIZE 1
+#define SYSREG_IE0_OFFSET 5
+#define SYSREG_IE0_SIZE 1
+#define SYSREG_IE1_OFFSET 6
+#define SYSREG_IE1_SIZE 1
+#define SYSREG_FC_OFFSET 8
+#define SYSREG_FC_SIZE 1
+#define SYSREG_F0_OFFSET 9
+#define SYSREG_F0_SIZE 1
+#define SYSREG_F1_OFFSET 10
+#define SYSREG_F1_SIZE 1
+#define SYSREG_CONF0_OFFSET 12
+#define SYSREG_CONF0_SIZE 6
+#define SYSREG_CONF1_OFFSET 18
+#define SYSREG_CONF1_SIZE 6
+
+/* Constants for ECR */
+#define ECR_UNRECOVERABLE 0
+#define ECR_TLB_MULTIPLE 1
+#define ECR_BUS_ERROR_WRITE 2
+#define ECR_BUS_ERROR_READ 3
+#define ECR_NMI 4
+#define ECR_ADDR_ALIGN_X 5
+#define ECR_PROTECTION_X 6
+#define ECR_DEBUG 7
+#define ECR_ILLEGAL_OPCODE 8
+#define ECR_UNIMPL_INSTRUCTION 9
+#define ECR_PRIVILEGE_VIOLATION 10
+#define ECR_FPE 11
+#define ECR_COPROC_ABSENT 12
+#define ECR_ADDR_ALIGN_R 13
+#define ECR_ADDR_ALIGN_W 14
+#define ECR_PROTECTION_R 15
+#define ECR_PROTECTION_W 16
+#define ECR_DTLB_MODIFIED 17
+#define ECR_TLB_MISS_X 20
+#define ECR_TLB_MISS_R 24
+#define ECR_TLB_MISS_W 28
+
+/* Bit manipulation macros */
+#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET)
+#define SYSREG_BF(name,value) \
+ (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \
+ << SYSREG_##name##_OFFSET)
+#define SYSREG_BFEXT(name,value) \
+ (((value) >> SYSREG_##name##_OFFSET) \
+ & ((1 << SYSREG_##name##_SIZE) - 1))
+#define SYSREG_BFINS(name,value,old) \
+ (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \
+ << SYSREG_##name##_OFFSET)) \
+ | SYSREG_BF(name,value))
+
+/* Register access macros */
+#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg)
+#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value)
+
+#endif /* __ASM_AVR32_SYSREG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_TYPES_H
+#define __ASM_AVR32_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+
+#endif /* __ASM_AVR32_TYPES_H */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_U_BOOT_H__
+#define __ASM_U_BOOT_H__ 1
+
+typedef struct bd_info {
+ unsigned long bi_baudrate;
+ unsigned long bi_ip_addr;
+ unsigned char bi_enetaddr[6];
+ unsigned char bi_phy_id[4];
+ struct environment_s *bi_env;
+ unsigned long bi_board_number;
+ void *bi_boot_params;
+ struct {
+ unsigned long start;
+ unsigned long size;
+ } bi_dram[CONFIG_NR_DRAM_BANKS];
+ unsigned long bi_flashstart;
+ unsigned long bi_flashsize;
+ unsigned long bi_flashoffset;
+} bd_t;
+
+#define bi_memstart bi_dram[0].start
+#define bi_memsize bi_dram[0].size
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ *
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* __ASM_U_BOOT_H__ */
--- /dev/null
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c {
+
+ u8 adr; /* I2C slave address */
+ u8 res0[3];
+#define I2C_ADR 0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES ~(I2C_ADR)
+
+ u8 fdr; /* I2C frequency divider register */
+ u8 res1[3];
+#define IC2_FDR 0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES ~(IC2_FDR)
+
+ u8 cr; /* I2C control redister */
+ u8 res2[3];
+#define I2C_CR_MEN 0x80
+#define I2C_CR_MIEN 0x40
+#define I2C_CR_MSTA 0x20
+#define I2C_CR_MTX 0x10
+#define I2C_CR_TXAK 0x08
+#define I2C_CR_RSTA 0x04
+#define I2C_CR_BCST 0x01
+
+ u8 sr; /* I2C status register */
+ u8 res3[3];
+#define I2C_SR_MCF 0x80
+#define I2C_SR_MAAS 0x40
+#define I2C_SR_MBB 0x20
+#define I2C_SR_MAL 0x10
+#define I2C_SR_BCSTM 0x08
+#define I2C_SR_SRW 0x04
+#define I2C_SR_MIF 0x02
+#define I2C_SR_RXAK 0x01
+
+ u8 dr; /* I2C data register */
+ u8 res4[3];
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+
+ u8 dfsrr; /* I2C digital filter sampling rate register */
+ u8 res5[3];
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+
+ /* Fill out the reserved block */
+ u8 res6[0xE8];
+} fsl_i2c_t;
+
+
+#define I2C_READ 1
+#define I2C_WRITE 0
+
+#endif /* _ASM_I2C_H_ */
#ifndef __IMMAP_85xx__
#define __IMMAP_85xx__
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+
/*
* Local-Access Registers and ECM Registers(0x0000-0x2000)
*/
* I2C Registers(0x3000-0x4000)
*/
typedef struct ccsr_i2c {
- u_char i2cadr; /* 0x3000 - I2C Address Register */
-#define MPC85xx_I2CADR_MASK 0xFE
- char res1[3];
- u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */
-#define MPC85xx_I2CFDR_MASK 0x3F
- char res2[3];
- u_char i2ccr; /* 0x3008 - I2C Control Register */
-#define MPC85xx_I2CCR_MEN 0x80
-#define MPC85xx_I2CCR_MIEN 0x40
-#define MPC85xx_I2CCR_MSTA 0x20
-#define MPC85xx_I2CCR_MTX 0x10
-#define MPC85xx_I2CCR_TXAK 0x08
-#define MPC85xx_I2CCR_RSTA 0x04
-#define MPC85xx_I2CCR_BCST 0x01
- char res3[3];
- u_char i2csr; /* 0x300c - I2C Status Register */
-#define MPC85xx_I2CSR_MCF 0x80
-#define MPC85xx_I2CSR_MAAS 0x40
-#define MPC85xx_I2CSR_MBB 0x20
-#define MPC85xx_I2CSR_MAL 0x10
-#define MPC85xx_I2CSR_BCSTM 0x08
-#define MPC85xx_I2CSR_SRW 0x04
-#define MPC85xx_I2CSR_MIF 0x02
-#define MPC85xx_I2CSR_RXAK 0x01
- char res4[3];
- u_char i2cdr; /* 0x3010 - I2C Data Register */
-#define MPC85xx_I2CDR_DATA 0xFF
- char res5[3];
- u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */
-#define MPC85xx_I2CDFSRR 0x3F
- char res6[4075];
+ struct fsl_i2c i2c[1];
+ u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
} ccsr_i2c_t;
#if defined(CONFIG_MPC8540) \
/*
* PCI Registers(0x8000-0x9000)
- * Omitting Reserved(0x9000-0x2_0000)
*/
typedef struct ccsr_pcix {
uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
- char res11[94688];
+ uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
+ char res11[476];
} ccsr_pcix_t;
+#define PCIX_COMMAND 0x62
+#define POWAR_EN 0x80000000
+#define POWAR_IO_READ 0x00080000
+#define POWAR_MEM_READ 0x00040000
+#define POWAR_IO_WRITE 0x00008000
+#define POWAR_MEM_WRITE 0x00004000
+#define POWAR_MEM_512M 0x0000001c
+#define POWAR_IO_1M 0x00000013
+
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_LOCAL 0x00f00000
+#define PIWAR_READ_SNOOP 0x00050000
+#define PIWAR_WRITE_SNOOP 0x00005000
+#define PIWAR_MEM_2G 0x0000001e
+
+
/*
* L2 Cache Registers(0x2_0000-0x2_1000)
*/
char res15[61651];
} ccsr_gur_t;
+#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
+
typedef struct immap {
ccsr_local_ecm_t im_local_ecm;
ccsr_ddr_t im_ddr;
ccsr_duart_t im_duart;
ccsr_lbc_t im_lbc;
ccsr_pcix_t im_pcix;
+ ccsr_pcix_t im_pcix2;
+ char reserved[90112];
ccsr_l2cache_t im_l2cache;
ccsr_dma_t im_dma;
ccsr_tsec_t im_tsec1;
--- /dev/null
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Copyright(c) 2004 Freescale Semiconductor
+ * Jeff Brown (Jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ */
+
+#ifndef __IMMAP_86xx__
+#define __IMMAP_86xx__
+
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+
+/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
+typedef struct ccsr_local_mcm {
+ uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
+ char res1[4];
+ uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
+ char res2[4];
+ uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
+ char res3[12];
+ uint bptr; /* 0x20 - Boot Page Translation Register */
+ char res4[3044];
+ uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
+ char res5[4];
+ uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
+ char res6[20];
+ uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
+ char res7[4];
+ uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
+ char res8[20];
+ uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
+ char res9[4];
+ uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
+ char res10[20];
+ uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
+ char res11[4];
+ uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
+ char res12[20];
+ uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
+ char res13[4];
+ uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
+ char res14[20];
+ uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
+ char res15[4];
+ uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
+ char res16[20];
+ uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
+ char res17[4];
+ uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
+ char res18[20];
+ uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
+ char res19[4];
+ uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
+ char res20[20];
+ uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
+ char res21[4];
+ uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
+ char res22[20];
+ uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
+ char res23[4];
+ uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
+ char res24[716];
+ uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
+ char res25[4];
+ uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
+ char res26[4];
+ uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
+ char res27[44];
+ uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
+ uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
+ uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
+ uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
+ char res28[16];
+ uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
+ uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
+ uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
+ char res29[3476];
+ uint edr; /* 0x1e00 - MCM Error Detect Register */
+ char res30[4];
+ uint eer; /* 0x1e08 - MCM Error Enable Register */
+ uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
+ uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
+ uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
+ char res31[488];
+} ccsr_local_mcm_t;
+
+/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
+
+typedef struct ccsr_ddr {
+ uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
+ char res1[4];
+ uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
+ char res2[4];
+ uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
+ char res3[4];
+ uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
+ char res4[4];
+ uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
+ char res5[4];
+ uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
+ char res6[84];
+ uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
+ uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
+ uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
+ uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
+ uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
+ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
+ char res7[104];
+ uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */
+ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
+ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
+ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
+ uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
+ uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
+ uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
+ uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
+ uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
+ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
+ uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
+ char res8[4];
+ uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
+ char res9[12];
+ uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
+ uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
+ uint init_addr; /* 0x2148 - DDR training initialzation address */
+ uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */
+ char res10[2728];
+ uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
+ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
+ char res11[512];
+ uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
+ uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
+ uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
+ char res12[20];
+ uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
+ uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
+ uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
+ char res13[20];
+ uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
+ uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
+ uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
+ uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
+ uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
+ uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
+ uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
+ char res14[164];
+ uint debug_1; /* 0x2f00 */
+ uint debug_2;
+ uint debug_3;
+ uint debug_4;
+ uint debug_5;
+ char res15[236];
+} ccsr_ddr_t;
+
+
+/* Daul I2C Registers(0x3000-0x4000) */
+typedef struct ccsr_i2c {
+ struct fsl_i2c i2c[2];
+ u8 res[4096 - 2 * sizeof(struct fsl_i2c)];
+} ccsr_i2c_t;
+
+/* DUART Registers(0x4000-0x5000) */
+typedef struct ccsr_duart {
+ char res1[1280];
+ u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
+ u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
+ u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
+ u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
+ u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
+ u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
+ u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
+ u_char uscr1; /* 0x4507 - UART1 Scratch Register */
+ char res2[8];
+ u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
+ char res3[239];
+ u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
+ u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
+ u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
+ u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
+ u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
+ u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
+ u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
+ u_char uscr2; /* 0x4607 - UART2 Scratch Register */
+ char res4[8];
+ u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
+ char res5[2543];
+} ccsr_duart_t;
+
+
+/* Local Bus Controller Registers(0x5000-0x6000) */
+typedef struct ccsr_lbc {
+ uint br0; /* 0x5000 - LBC Base Register 0 */
+ uint or0; /* 0x5004 - LBC Options Register 0 */
+ uint br1; /* 0x5008 - LBC Base Register 1 */
+ uint or1; /* 0x500c - LBC Options Register 1 */
+ uint br2; /* 0x5010 - LBC Base Register 2 */
+ uint or2; /* 0x5014 - LBC Options Register 2 */
+ uint br3; /* 0x5018 - LBC Base Register 3 */
+ uint or3; /* 0x501c - LBC Options Register 3 */
+ uint br4; /* 0x5020 - LBC Base Register 4 */
+ uint or4; /* 0x5024 - LBC Options Register 4 */
+ uint br5; /* 0x5028 - LBC Base Register 5 */
+ uint or5; /* 0x502c - LBC Options Register 5 */
+ uint br6; /* 0x5030 - LBC Base Register 6 */
+ uint or6; /* 0x5034 - LBC Options Register 6 */
+ uint br7; /* 0x5038 - LBC Base Register 7 */
+ uint or7; /* 0x503c - LBC Options Register 7 */
+ char res1[40];
+ uint mar; /* 0x5068 - LBC UPM Address Register */
+ char res2[4];
+ uint mamr; /* 0x5070 - LBC UPMA Mode Register */
+ uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
+ uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
+ char res3[8];
+ uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
+ uint mdr; /* 0x5088 - LBC UPM Data Register */
+ char res4[8];
+ uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
+ char res5[8];
+ uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
+ uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
+ char res6[8];
+ uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
+ uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
+ uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
+ uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
+ uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
+ char res7[12];
+ uint lbcr; /* 0x50d0 - LBC Configuration Register */
+ uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
+ char res8[3880];
+} ccsr_lbc_t;
+
+/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
+typedef struct ccsr_pex {
+ uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
+ uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
+ char res1[4];
+ uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
+ char res2[16];
+ uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
+ uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
+ uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
+ uint pm_command; /* 0x802c - PEX PM Command register */
+ char res3[3016];
+ uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
+ uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
+ uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
+ uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
+ char res4[8];
+ uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
+ char res5[12];
+ uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
+ uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
+ uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
+ char res6[4];
+ uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
+ char res7[12];
+ uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
+ uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
+ uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
+ char res8[4];
+ uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
+ char res9[12];
+ uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
+ uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
+ uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
+ char res10[4];
+ uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
+ char res11[12];
+ uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
+ uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
+ uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
+ char res12[4];
+ uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
+ char res13[12];
+ char res14[256];
+ uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
+ char res15[4];
+ uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
+ uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
+ uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
+ char res16[12];
+ uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
+ char res17[4];
+ uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
+ uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
+ uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
+ char res18[12];
+ uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
+ char res19[4];
+ uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
+ uint piwbear1;
+ uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
+ char res20[12];
+ uint pedr; /* 0x8e00 - PEX Error Detect Register */
+ char res21[4];
+ uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
+ char res22[4];
+ uint pecdr; /* 0x8e10 - PEX Error Disable Register */
+ char res23[12];
+ uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
+ char res24[4];
+ uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
+ uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
+ uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
+ uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
+ char res25[452];
+ char res26[4];
+} ccsr_pex_t;
+
+/* Hyper Transport Register Block (0xA000-0xB000) */
+typedef struct ccsr_ht {
+ uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
+ uint hcfg_data; /* 0xa004 - HT Configuration Data register */
+ char res1[3064];
+ uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
+ char res2[12];
+ uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
+ char res3[12];
+ uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
+ char res4[4];
+ uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
+ char res5[4];
+ uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
+ char res6[12];
+ uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
+ char res7[4];
+ uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
+ char res8[4];
+ uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
+ char res9[12];
+ uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
+ char res10[4];
+ uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
+ char res11[4];
+ uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
+ char res12[12];
+ uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
+ char res13[4];
+ uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
+ char res14[4];
+ uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
+ char res15[236];
+ uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
+ char res16[4];
+ uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
+ char res17[4];
+ uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
+ char res18[12];
+ uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
+ char res19[4];
+ uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
+ char res20[4];
+ uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
+ char res21[12];
+ uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
+ char res22[4];
+ uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
+ char res23[4];
+ uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
+ char res24[12];
+ uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
+ char res25[4];
+ uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
+ char res26[4];
+ uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
+ char res27[12];
+ uint hedr; /* 0xae00 - HT Error Detect register */
+ char res28[4];
+ uint heier; /* 0xae08 - HT Error Interrupt Enable register */
+ char res29[4];
+ uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
+ char res30[12];
+ uint hecsr; /* 0xae20 - HT Error Capture Status register */
+ char res31[4];
+ uint hec0; /* 0xae28 - HT Error Capture 0 register */
+ uint hec1; /* 0xae2c - HT Error Capture 1 register */
+ uint hec2; /* 0xae30 - HT Error Capture 2 register */
+ char res32[460];
+} ccsr_ht_t;
+
+/* DMA Registers(0x2_1000-0x2_2000) */
+typedef struct ccsr_dma {
+ char res1[256];
+ uint mr0; /* 0x21100 - DMA 0 Mode Register */
+ uint sr0; /* 0x21104 - DMA 0 Status Register */
+ char res2[4];
+ uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
+ uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
+ uint sar0; /* 0x21114 - DMA 0 Source Address Register */
+ uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
+ uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
+ uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
+ char res3[4];
+ uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
+ char res4[8];
+ uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
+ char res5[4];
+ uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
+ uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
+ uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
+ char res6[56];
+ uint mr1; /* 0x21180 - DMA 1 Mode Register */
+ uint sr1; /* 0x21184 - DMA 1 Status Register */
+ char res7[4];
+ uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
+ uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
+ uint sar1; /* 0x21194 - DMA 1 Source Address Register */
+ uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
+ uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
+ uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
+ char res8[4];
+ uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
+ char res9[8];
+ uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
+ char res10[4];
+ uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
+ uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
+ uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
+ char res11[56];
+ uint mr2; /* 0x21200 - DMA 2 Mode Register */
+ uint sr2; /* 0x21204 - DMA 2 Status Register */
+ char res12[4];
+ uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
+ uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
+ uint sar2; /* 0x21214 - DMA 2 Source Address Register */
+ uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
+ uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
+ uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
+ char res13[4];
+ uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
+ char res14[8];
+ uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
+ char res15[4];
+ uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
+ uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
+ uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
+ char res16[56];
+ uint mr3; /* 0x21280 - DMA 3 Mode Register */
+ uint sr3; /* 0x21284 - DMA 3 Status Register */
+ char res17[4];
+ uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
+ uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
+ uint sar3; /* 0x21294 - DMA 3 Source Address Register */
+ uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
+ uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
+ uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
+ char res18[4];
+ uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
+ char res19[8];
+ uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
+ char res20[4];
+ uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
+ uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
+ uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
+ char res21[56];
+ uint dgsr; /* 0x21300 - DMA General Status Register */
+ char res22[3324];
+} ccsr_dma_t;
+
+/* tsec1-4: 24000-28000 */
+typedef struct ccsr_tsec {
+ uint id; /* 0x24000 - Controller ID Register */
+ char res1[12];
+ uint ievent; /* 0x24010 - Interrupt Event Register */
+ uint imask; /* 0x24014 - Interrupt Mask Register */
+ uint edis; /* 0x24018 - Error Disabled Register */
+ char res2[4];
+ uint ecntrl; /* 0x24020 - Ethernet Control Register */
+ char res2_1[4];
+ uint ptv; /* 0x24028 - Pause Time Value Register */
+ uint dmactrl; /* 0x2402c - DMA Control Register */
+ uint tbipa; /* 0x24030 - TBI PHY Address Register */
+ char res3[88];
+ uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
+ char res4[8];
+ uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
+ uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
+ char res4_1[4];
+ uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
+ uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
+ char res5[84];
+ uint tctrl; /* 0x24100 - Transmit Control Register */
+ uint tstat; /* 0x24104 - Transmit Status Register */
+ uint dfvlan; /* 0x24108 - Default VLAN control word */
+ char res6[4];
+ uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
+ uint tqueue; /* 0x24114 - Transmit Queue Control Register */
+ char res7[40];
+ uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
+ uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
+ char res8[52];
+ uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
+ char res9[4];
+ uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
+ char res10[4];
+ uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
+ char res11[4];
+ uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
+ char res12[4];
+ uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
+ char res13[4];
+ uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
+ char res14[4];
+ uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
+ char res15[4];
+ uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
+ char res16[4];
+ uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
+ char res17[64];
+ uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
+ uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
+ char res18[4];
+ uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
+ char res19[4];
+ uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
+ char res20[4];
+ uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
+ char res21[4];
+ uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
+ char res22[4];
+ uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
+ char res23[4];
+ uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
+ char res24[4];
+ uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
+ char res25[192];
+ uint rctrl; /* 0x24300 - Receive Control Register */
+ uint rstat; /* 0x24304 - Receive Status Register */
+ char res26[8];
+ uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
+ uint rqueue; /* 0x24314 - Receive queue control register */
+ char res27[24];
+ uint rbifx; /* 0x24330 - Receive bit field extract control Register */
+ uint rqfar; /* 0x24334 - Receive queue filing table address Register */
+ uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
+ uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
+ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
+ char res28[56];
+ uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
+ char res29[4];
+ uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
+ char res30[4];
+ uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
+ char res31[4];
+ uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
+ char res32[4];
+ uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
+ char res33[4];
+ uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
+ char res34[4];
+ uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
+ char res35[4];
+ uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
+ char res36[4];
+ uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
+ char res37[64];
+ uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
+ uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
+ char res38[4];
+ uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
+ char res39[4];
+ uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
+ char res40[4];
+ uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
+ char res41[4];
+ uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
+ char res42[4];
+ uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
+ char res43[4];
+ uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
+ char res44[4];
+ uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
+ char res45[192];
+ uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
+ uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
+ uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
+ uint hafdup; /* 0x2450c - Half Duplex Register */
+ uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
+ char res46[12];
+ uint miimcfg; /* 0x24520 - MII Management Configuration Register */
+ uint miimcom; /* 0x24524 - MII Management Command Register */
+ uint miimadd; /* 0x24528 - MII Management Address Register */
+ uint miimcon; /* 0x2452c - MII Management Control Register */
+ uint miimstat; /* 0x24530 - MII Management Status Register */
+ uint miimind; /* 0x24534 - MII Management Indicator Register */
+ uint ifctrl; /* 0x24538 - Interface Contrl Register */
+ uint ifstat; /* 0x2453c - Interface Status Register */
+ uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
+ uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
+ uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
+ uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
+ uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
+ uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
+ uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
+ uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
+ uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
+ uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
+ uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
+ uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
+ uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
+ uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
+ uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
+ uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
+ uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
+ uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
+ uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
+ uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
+ uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
+ uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
+ uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
+ uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
+ uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
+ uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
+ uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
+ uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
+ uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
+ uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
+ uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
+ uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
+ char res48[192];
+ uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
+ uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
+ uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
+ uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
+ uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
+ uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
+ uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
+ uint rbyt; /* 0x2469c - Receive Byte Counter */
+ uint rpkt; /* 0x246a0 - Receive Packet Counter */
+ uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
+ uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
+ uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
+ uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
+ uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
+ uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
+ uint raln; /* 0x246bc - Receive Alignment Error Counter */
+ uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
+ uint rcde; /* 0x246c4 - Receive Code Error Counter */
+ uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
+ uint rund; /* 0x246cc - Receive Undersize Packet Counter */
+ uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
+ uint rfrg; /* 0x246d4 - Receive Fragments Counter */
+ uint rjbr; /* 0x246d8 - Receive Jabber Counter */
+ uint rdrp; /* 0x246dc - Receive Drop Counter */
+ uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
+ uint tpkt; /* 0x246e4 - Transmit Packet Counter */
+ uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
+ uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
+ uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
+ uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
+ uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
+ uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
+ uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
+ uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
+ uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
+ uint tncl; /* 0x2470c - Transmit Total Collision Counter */
+ char res49[4];
+ uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
+ uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
+ uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
+ uint txcf; /* 0x24720 - Transmit Control Frame Counter */
+ uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
+ uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
+ uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
+ uint car1; /* 0x24730 - Carry Register One */
+ uint car2; /* 0x24734 - Carry Register Two */
+ uint cam1; /* 0x24738 - Carry Mask Register One */
+ uint cam2; /* 0x2473c - Carry Mask Register Two */
+ uint rrej; /* 0x24740 - Receive filer rejected packet counter */
+ char res50[188];
+ uint iaddr0; /* 0x24800 - Indivdual address register 0 */
+ uint iaddr1; /* 0x24804 - Indivdual address register 1 */
+ uint iaddr2; /* 0x24808 - Indivdual address register 2 */
+ uint iaddr3; /* 0x2480c - Indivdual address register 3 */
+ uint iaddr4; /* 0x24810 - Indivdual address register 4 */
+ uint iaddr5; /* 0x24814 - Indivdual address register 5 */
+ uint iaddr6; /* 0x24818 - Indivdual address register 6 */
+ uint iaddr7; /* 0x2481c - Indivdual address register 7 */
+ char res51[96];
+ uint gaddr0; /* 0x24880 - Global address register 0 */
+ uint gaddr1; /* 0x24884 - Global address register 1 */
+ uint gaddr2; /* 0x24888 - Global address register 2 */
+ uint gaddr3; /* 0x2488c - Global address register 3 */
+ uint gaddr4; /* 0x24890 - Global address register 4 */
+ uint gaddr5; /* 0x24894 - Global address register 5 */
+ uint gaddr6; /* 0x24898 - Global address register 6 */
+ uint gaddr7; /* 0x2489c - Global address register 7 */
+ char res52[352];
+ uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
+ char res53[500];
+ uint attr; /* 0x24BF8 - DMA Attribute register */
+ uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
+ char res54[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers(0x4_0000-0x6_1000) */
+
+typedef struct ccsr_pic {
+ char res1[64];
+ uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
+ char res2[12];
+ uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
+ char res3[12];
+ uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
+ char res4[12];
+ uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
+ char res5[12];
+ uint ctpr; /* 0x40080 - Current Task Priority Register */
+ char res6[12];
+ uint whoami; /* 0x40090 - Who Am I Register */
+ char res7[12];
+ uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
+ char res8[12];
+ uint eoi; /* 0x400b0 - End Of Interrupt Register */
+ char res9[3916];
+ uint frr; /* 0x41000 - Feature Reporting Register */
+ char res10[28];
+ uint gcr; /* 0x41020 - Global Configuration Register */
+ char res11[92];
+ uint vir; /* 0x41080 - Vendor Identification Register */
+ char res12[12];
+ uint pir; /* 0x41090 - Processor Initialization Register */
+ char res13[12];
+ uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
+ char res14[12];
+ uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
+ char res15[12];
+ uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
+ char res16[12];
+ uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
+ char res17[12];
+ uint svr; /* 0x410e0 - Spurious Vector Register */
+ char res18[12];
+ uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
+ char res19[12];
+ uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
+ char res20[12];
+ uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
+ char res21[12];
+ uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
+ char res22[12];
+ uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
+ char res23[12];
+ uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
+ char res24[12];
+ uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
+ char res25[12];
+ uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
+ char res26[12];
+ uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
+ char res27[12];
+ uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
+ char res28[12];
+ uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
+ char res29[12];
+ uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
+ char res30[12];
+ uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
+ char res31[12];
+ uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
+ char res32[12];
+ uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
+ char res33[12];
+ uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
+ char res34[12];
+ uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
+ char res35[268];
+ uint tcr; /* 0x41300 - Timer Control Register */
+ char res36[12];
+ uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
+ char res37[12];
+ uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
+ char res38[12];
+ uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
+ char res39[12];
+ uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
+ char res40[12];
+ uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
+ char res41[12];
+ uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
+ char res42[12];
+ uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
+ char res43[12];
+ uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
+ char res44[12];
+ uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
+ char res45[12];
+ uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
+ char res46[12];
+ uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
+ char res47[12];
+ uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
+ char res48[60];
+ uint msgr0; /* 0x41400 - Message Register 0 */
+ char res49[12];
+ uint msgr1; /* 0x41410 - Message Register 1 */
+ char res50[12];
+ uint msgr2; /* 0x41420 - Message Register 2 */
+ char res51[12];
+ uint msgr3; /* 0x41430 - Message Register 3 */
+ char res52[204];
+ uint mer; /* 0x41500 - Message Enable Register */
+ char res53[12];
+ uint msr; /* 0x41510 - Message Status Register */
+ char res54[60140];
+ uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
+ char res55[12];
+ uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
+ char res56[12];
+ uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
+ char res57[12];
+ uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
+ char res58[12];
+ uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
+ char res59[12];
+ uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
+ char res60[12];
+ uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
+ char res61[12];
+ uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
+ char res62[12];
+ uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
+ char res63[12];
+ uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
+ char res64[12];
+ uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
+ char res65[12];
+ uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
+ char res66[12];
+ uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
+ char res67[12];
+ uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
+ char res68[12];
+ uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
+ char res69[12];
+ uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
+ char res70[12];
+ uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
+ char res71[12];
+ uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
+ char res72[12];
+ uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
+ char res73[12];
+ uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
+ char res74[12];
+ uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
+ char res75[12];
+ uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
+ char res76[12];
+ uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
+ char res77[12];
+ uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
+ char res78[140];
+ uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
+ char res79[12];
+ uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
+ char res80[12];
+ uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
+ char res81[12];
+ uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
+ char res82[12];
+ uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
+ char res83[12];
+ uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
+ char res84[12];
+ uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
+ char res85[12];
+ uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
+ char res86[12];
+ uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
+ char res87[12];
+ uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
+ char res88[12];
+ uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
+ char res89[12];
+ uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
+ char res90[12];
+ uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
+ char res91[12];
+ uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
+ char res92[12];
+ uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
+ char res93[12];
+ uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
+ char res94[12];
+ uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
+ char res95[12];
+ uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
+ char res96[12];
+ uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
+ char res97[12];
+ uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
+ char res98[12];
+ uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
+ char res99[12];
+ uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
+ char res100[12];
+ uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
+ char res101[12];
+ uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
+ char res102[12];
+ uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
+ char res103[12];
+ uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
+ char res104[12];
+ uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
+ char res105[12];
+ uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
+ char res106[12];
+ uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
+ char res107[12];
+ uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
+ char res108[12];
+ uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
+ char res109[12];
+ uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
+ char res110[12];
+ uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
+ char res111[12];
+ uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
+ char res112[12];
+ uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
+ char res113[12];
+ uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
+ char res114[12];
+ uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
+ char res115[12];
+ uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
+ char res116[12];
+ uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
+ char res117[12];
+ uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
+ char res118[12];
+ uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
+ char res119[12];
+ uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
+ char res120[12];
+ uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
+ char res121[12];
+ uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
+ char res122[12];
+ uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
+ char res123[12];
+ uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
+ char res124[12];
+ uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
+ char res125[12];
+ uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
+ char res126[12];
+ uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
+ char res127[12];
+ uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
+ char res128[12];
+ uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
+ char res129[12];
+ uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
+ char res130[12];
+ uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
+ char res131[12];
+ uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
+ char res132[12];
+ uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
+ char res133[12];
+ uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
+ char res134[12];
+ uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
+ char res135[12];
+ uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
+ char res136[12];
+ uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
+ char res137[12];
+ uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
+ char res138[12];
+ uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
+ char res139[12];
+ uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
+ char res140[12];
+ uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
+ char res141[12];
+ uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
+ char res142[4108];
+ uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
+ char res143[12];
+ uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
+ char res144[12];
+ uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
+ char res145[12];
+ uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
+ char res146[12];
+ uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
+ char res147[12];
+ uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
+ char res148[12];
+ uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
+ char res149[12];
+ uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
+ char res150[59852];
+ uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
+ char res151[12];
+ uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
+ char res152[12];
+ uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
+ char res153[12];
+ uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
+ char res154[12];
+ uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
+ char res155[12];
+ uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
+ char res156[12];
+ uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
+ char res157[12];
+ uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
+ char res158[3916];
+} ccsr_pic_t;
+
+/* RapidIO Registers(0xc_0000-0xe_0000) */
+
+typedef struct ccsr_rio {
+ uint didcar; /* 0xc0000 - Device Identity Capability Register */
+ uint dicar; /* 0xc0004 - Device Information Capability Register */
+ uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
+ uint aicar; /* 0xc000c - Assembly Information Capability Register */
+ uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
+ uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
+ uint socar; /* 0xc0018 - Source Operations Capability Register */
+ uint docar; /* 0xc001c - Destination Operations Capability Register */
+ char res1[32];
+ uint msr; /* 0xc0040 - Mailbox Command And Status Register */
+ uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+ char res2[4];
+ uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+ char res3[12];
+ uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+ uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
+ char res4[4];
+ uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+ uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
+ char res5[144];
+ uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+ char res6[28];
+ uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
+ uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
+ char res7[20];
+ uint pgccsr; /* 0xc013c - Port General Command and Status Register */
+ uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+ uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+ uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
+ char res8[12];
+ uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
+ uint pccsr; /* 0xc015c - Port Control Command and Status Register */
+ char res9[1184];
+ uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
+ char res10[4];
+ uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
+ uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
+ char res11[4];
+ uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
+ uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
+ uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
+ char res12[32];
+ uint edcsr; /* 0xc0640 - Port 0 error detect status register */
+ uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
+ uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
+ uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
+ uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
+ uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
+ uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
+ char res13[12];
+ uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
+ uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
+ char res14[63892];
+ uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
+ char res15[12];
+ uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
+ char res16[12];
+ uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
+ char res17[92];
+ uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
+ char res18[124];
+ uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
+ char res19[28];
+ uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
+ char res20[12];
+ uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
+ char res21[12];
+ uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
+ char res22[20];
+ uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
+ char res23[4];
+ uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
+ char res24[2716];
+ uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+ uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
+ char res25[8];
+ uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+ char res26[12];
+ uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+ uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
+ uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+ char res27[4];
+ uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+ uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
+ uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
+ uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
+ uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+ uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
+ uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+ char res28[4];
+ uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+ uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
+ uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
+ uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
+ uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+ uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
+ uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+ char res29[4];
+ uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+ uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
+ uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
+ uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
+ uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+ uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
+ uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+ char res30[4];
+ uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+ uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
+ uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
+ uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
+ uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+ uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
+ uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+ char res31[4];
+ uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+ uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
+ uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
+ uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
+ uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+ uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
+ uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+ char res32[4];
+ uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+ uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
+ uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
+ uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
+ uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+ uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
+ uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+ char res33[4];
+ uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+ uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
+ uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
+ uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
+ uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+ uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
+ uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+ char res34[4];
+ uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+ uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
+ uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
+ uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
+ char res35[64];
+ uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+ uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+ char res36[4];
+ uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+ char res37[12];
+ uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+ char res38[4];
+ uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+ char res39[4];
+ uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+ char res40[12];
+ uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+ char res41[4];
+ uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+ char res42[4];
+ uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+ char res43[12];
+ uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+ char res44[4];
+ uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+ char res45[4];
+ uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+ char res46[12];
+ uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+ char res47[12];
+ uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+ char res48[12];
+ uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+ uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+ uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+ uint pecr; /* 0xd0e0c - Port Error Control Register */
+ uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+ uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
+ uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
+ char res49[4];
+ uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
+ char res50[4];
+ uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
+ uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
+ char res51[8656];
+ uint omr; /* 0xd3000 - Outbound Mode Register */
+ uint osr; /* 0xd3004 - Outbound Status Register */
+ uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+ uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
+ uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
+ uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
+ uint odpr; /* 0xd3018 - Outbound Destination Port Register */
+ uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
+ uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
+ uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+ uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
+ uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
+ uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
+ uint omlr; /* 0xd3034 - Outbound Multicast List Register */
+ char res52[40];
+ uint imr; /* 0xd3060 - Outbound Mode Register */
+ uint isr; /* 0xd3064 - Inbound Status Register */
+ uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+ uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
+ uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
+ uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
+ uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
+ char res53[900];
+ uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
+ uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
+ char res54[16];
+ uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
+ uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
+ char res55[12];
+ uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
+ char res56[48];
+ uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
+ uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
+ uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
+ uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
+ uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
+ uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
+ uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
+ char res57[100];
+ uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
+ uint pwsr; /* 0xd34e4 - Port-Write Status Register */
+ uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
+ uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
+ char res58[51984];
+} ccsr_rio_t;
+
+/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+typedef struct ccsr_gur {
+ uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+ uint porbmsr; /* 0xe0004 - POR boot mode status register */
+#define MPC86xx_PORBMSR_HA 0x00060000
+ uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
+ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
+ char res1[12];
+ uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
+ char res2[12];
+ uint gpiocr; /* 0xe0030 - GPIO control register */
+ char res3[12];
+ uint gpoutdr; /* 0xe0040 - General-purpose output data register */
+ char res4[12];
+ uint gpindr; /* 0xe0050 - General-purpose input data register */
+ char res5[12];
+ uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+ char res6[12];
+ uint devdisr; /* 0xe0070 - Device disable control */
+#define MPC86xx_DEVDISR_PCIEX1 0x80000000
+#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+ char res7[12];
+ uint powmgtcsr; /* 0xe0080 - Power management status and control register */
+ char res8[12];
+ uint mcpsumr; /* 0xe0090 - Machine check summary register */
+ char res9[12];
+ uint pvr; /* 0xe00a0 - Processor version register */
+ uint svr; /* 0xe00a4 - System version register */
+ char res10[3416];
+ uint clkocr; /* 0xe0e00 - Clock out select register */
+ char res11[12];
+ uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
+ char res12[12];
+ uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
+ int res13[57];
+ uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
+ int res14[6];
+ uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
+ char res15[61656];
+} ccsr_gur_t;
+
+typedef struct immap {
+ ccsr_local_mcm_t im_local_mcm;
+ ccsr_ddr_t im_ddr1;
+ ccsr_i2c_t im_i2c;
+ ccsr_duart_t im_duart;
+ ccsr_lbc_t im_lbc;
+ ccsr_ddr_t im_ddr2;
+ char res1[4096];
+ ccsr_pex_t im_pex1;
+ ccsr_pex_t im_pex2;
+ ccsr_ht_t im_ht;
+ char res2[90112];
+ ccsr_dma_t im_dma;
+ char res3[8192];
+ ccsr_tsec_t im_tsec1;
+ ccsr_tsec_t im_tsec2;
+ ccsr_tsec_t im_tsec3;
+ ccsr_tsec_t im_tsec4;
+ char res4[98304];
+ ccsr_pic_t im_pic;
+ char res5[389120];
+ ccsr_rio_t im_rio;
+ ccsr_gur_t im_gur;
+} immap_t;
+
+extern immap_t *immr;
+
+#endif /*__IMMAP_86xx__*/
*/
typedef struct _pte {
- unsigned long page_num:20;
- unsigned long flags:12; /* Page flags (some unused bits) */
+ unsigned long page_num:20;
+ unsigned long flags:12; /* Page flags (some unused bits) */
} pte;
#define PD_SHIFT (10+12) /* Page directory */
#define BOOKE_PAGESZ_1GB 10
#define BOOKE_PAGESZ_4GB 11
+#if defined(CONFIG_MPC86xx)
+#define LAWBAR_BASE_ADDR 0x00FFFFFF
+#define LAWAR_TRGT_IF 0x01F00000
+#else
#define LAWBAR_BASE_ADDR 0x000FFFFF
-#define LAWAR_EN 0x80000000
#define LAWAR_TRGT_IF 0x00F00000
+#endif
+#define LAWAR_EN 0x80000000
#define LAWAR_SIZE 0x0000003F
#define LAWAR_TRGT_IF_PCI 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
+#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
#define LAWAR_TRGT_IF_RIO 0x00c00000
#define LAWAR_TRGT_IF_DDR 0x00f00000
+#define LAWAR_TRGT_IF_DDR1 0x00f00000
+#define LAWAR_TRGT_IF_DDR2 0x01600000
#define LAWAR_SIZE_BASE 0xa
#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
+#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
+#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
+#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
+#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
#ifdef CONFIG_440SPE
/*----------------------------------------------------------------------------+
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
+#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
#define SPRN_MBAR 0x137 /* System memory base address */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define ESR_ST 0x00800000 /* Store Operation */
+#if defined(CONFIG_MPC86xx)
+#define SPRN_MSSCRO 0x3f6
+#endif
+
+
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
+#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
-#if defined(CONFIG_E500)
+#if defined(CONFIG_MPC86xx)
+#define MSSCR0 SPRN_MSSCRO
+#endif
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define PIR SPRN_PIR
#endif
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define CSRR0 SPRN_CSRR0
#define CSRR1 SPRN_CSRR1
#define IVPR SPRN_IVPR
-#define USPRG0 SPRN_USPRG0
+#define USPRG0 SPRN_USPRG
#define SPRG4R SPRN_SPRG4R
#define SPRG5R SPRN_SPRG5R
#define SPRG6R SPRN_SPRG6R
#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
+#define PVR_86xx 0x80040000
+#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
/*
* For the 8xx processors, all of them report the same PVR family for
#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
+#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
+
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
#define SVR_8541 0x807A
#define SVR_8548 0x8031
#define SVR_8548_E 0x8039
+#define SVR_8641 0x8090
/* I am just adding a single entry for 8260 boards. I think we may be
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
- || defined(CONFIG_E500)
+ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)
#endif
#include <asm/immap_8260.h>
#endif
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
#ifdef CONFIG_MPC85xx
#include <mpc85xx.h>
#include <asm/immap_85xx.h>
char * strmhz(char *buf, long hz);
int last_stage_init(void);
extern ulong monitor_flash_len;
+#ifdef CFG_ID_EEPROM
+int mac_read_from_eeprom(void);
+#endif
/* common/flash.c */
void flash_perror (int);
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \
defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \
- defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
+ defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) || \
+ defined(CONFIG_V38B)
void board_get_enetaddr (uchar *addr);
#endif
defined (CONFIG_74xx) || \
defined (CONFIG_MPC8220) || \
defined (CONFIG_MPC85xx) || \
+ defined (CONFIG_MPC86xx) || \
defined (CONFIG_MPC83XX)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
#endif
+#if defined(CONFIG_MPC86xx)
+typedef MPC86xx_SYS_INFO sys_info_t;
+void get_sys_info ( sys_info_t * );
+#endif
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
+ *
+ * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
+ * 33MHz to accommodate, based on a PCI pin.
+ * Note that PCI-X won't work at 33MHz.
*/
#ifndef CONFIG_SYS_CLK_FREQ
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8540@0"
+#define OF_SOC "soc8540@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#define CFG_PCI1_IO_BASE 0x0
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* General PCI */
#define CFG_PCI_MEM_BASE 0x80000000
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8541@0"
+#define OF_SOC "soc8541@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2100000
+#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
+#define CONFIG_MPC85XX_PCI2
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
-#endif
-
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8548@0"
+#define OF_SOC "soc8548@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2100000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_85XX_PCI2
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
-#endif
-
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
-#define CONFIG_MPC85XX_TSEC4 1
+#undef CONFIG_MPC85XX_TSEC4
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
#define TSEC4_PHY_ADDR 3
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
-#define FEC_PHYIDX 0
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
+
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8555@0"
+#define OF_SOC "soc8555@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2100000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_MPC85XX_PCI2
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8560@0"
+#define OF_SOC "soc8560@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8641HPCN board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx 1 /* MPC86xx */
+#define CONFIG_MPC8641 1 /* MPC8641 specific */
+#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
+#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+#undef DEBUG
+
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR 0xff800000
+#endif
+
+#define CFG_RESET_ADDRESS 0xfff00100
+
+/*#undef CONFIG_PCI*/
+#define CONFIG_PCI
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+/* #define CONFIG_DDR_INTERLEAVE 1 */
+#define CACHE_LINE_INTERLEAVING 0x20000000
+#define PAGE_INTERLEAVING 0x21000000
+#define BANK_INTERLEAVING 0x22000000
+#define SUPER_BANK_INTERLEAVING 0x23000000
+
+
+#define CONFIG_ALTIVEC 1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CFG_L2
+#define L2_INIT 0
+#define L2_ENABLE (L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR1 parameters
+ */
+
+ #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
+
+ #define CFG_DDR_CS0_BNDS 0x0000000F
+ #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
+ #define CFG_DDR_EXT_REFRESH 0x00000000
+ #define CFG_DDR_TIMING_0 0x00260802
+ #define CFG_DDR_TIMING_1 0x39357322
+ #define CFG_DDR_TIMING_2 0x14904cc8
+ #define CFG_DDR_MODE_1 0x00480432
+ #define CFG_DDR_MODE_2 0x00000000
+ #define CFG_DDR_INTERVAL 0x06090100
+ #define CFG_DDR_DATA_INIT 0xdeadbeef
+ #define CFG_DDR_CLK_CTRL 0x03800000
+ #define CFG_DDR_OCD_CTRL 0x00000000
+ #define CFG_DDR_OCD_STATUS 0x00000000
+ #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
+ #define CFG_DDR_CONTROL2 0x04400000
+
+ /* Not used in fixed_sdram function */
+
+ #define CFG_DDR_MODE 0x00000022
+ #define CFG_DDR_CS1_BNDS 0x00000000
+ #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
+ #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
+ #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
+ #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
+#endif
+
+#define CFG_ID_EEPROM 1
+#define ID_EEPROM_ADDR 0x57
+
+/*
+ * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
+ * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
+ * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
+ * However, when u-boot comes up, the flash_init needs hard start addresses
+ * to build its info table. For user convenience, the flash addresses is
+ * fe800000 and ff800000. That way, u-boot knows where the flash is
+ * and the user can download u-boot code from promjet to fef00000, a
+ * more intuitive location than fe700000.
+ *
+ * Note that, on switching the boot location, fef00000 becomes fff00000.
+ */
+#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
+#define CFG_FLASH_BASE2 0xff800000
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+
+#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
+#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
+
+#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */
+#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
+
+#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
+#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
+
+#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
+#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+
+
+#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
+#define PIXIS_ID 0x0 /* Board ID at offset 0 */
+#define PIXIS_VER 0x1 /* Board version at offset 1 */
+#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
+#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
+#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
+#define PIXIS_VCTL 0x10 /* VELA Control Register */
+#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
+#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
+#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
+#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
+#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#if defined(CFG_RAMBOOT)
+#undef CFG_FLASH_CFI_DRIVER
+#undef CONFIG_SPD_EEPROM
+#define CFG_SDRAM_SIZE 256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8641@0"
+#define OF_SOC "soc8641@f8000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+/* For RTL8139 */
+#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
+#define _IO_BASE 0x00000000
+
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_IO_BASE 0xe3000000
+#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#undef CFG_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_RTL8139
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+
+#define CONFIG_MPC86XX_TSEC1 1
+#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
+#define CONFIG_MPC86XX_TSEC2 1
+#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
+#define CONFIG_MPC86XX_TSEC3 1
+#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
+#define CONFIG_MPC86XX_TSEC4 1
+#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC3_PHY_ADDR 2
+#define TSEC4_PHY_ADDR 3
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0 2G Cacheable, non-guarded
+ * 0x0000_0000 2G DDR
+ */
+#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U CFG_DBAT0U
+
+/*
+ * BAT1 1G Cache-inhibited, guarded
+ * 0x8000_0000 512M PCI-Express 1 Memory
+ * 0xa000_0000 512M PCI-Express 2 Memory
+ * Changed it for operating from 0xd0000000
+ */
+#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U CFG_DBAT1U
+
+/*
+ * BAT2 512M Cache-inhibited, guarded
+ * 0xc000_0000 512M RapidIO Memory
+ */
+#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U CFG_DBAT2U
+
+/*
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xf800_0000 4M CCSR
+ */
+#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U CFG_DBAT3U
+
+/*
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 16M PCI-Express 1 I/O
+ * 0xe300_0000 16M PCI-Express 2 I/0
+ * Note that this is at 0xe0000000
+ */
+#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U CFG_DBAT4U
+
+/*
+ * BAT5 128K Cacheable, non-guarded
+ * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L CFG_DBAT5L
+#define CFG_IBAT5U CFG_DBAT5U
+
+/*
+ * BAT6 32M Cache-inhibited, guarded
+ * 0xfe00_0000 32M FLASH
+ */
+#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U CFG_DBAT6U
+
+#define CFG_DBAT7L 0x00000000
+#define CFG_DBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+#define CFG_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CFG_CMD_EXT2) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_IMLS \
+ | CFG_CMD_FLASH \
+ | CFG_CMD_LOADS))
+ #else
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CGF_CMD_EXT2) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_IMLS \
+ | CFG_CMD_FLASH \
+ | CFG_CMD_LOADS))
+ #endif
+#else
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CFG_CMD_EXT2)
+ #else
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C)
+ #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_HAS_ETH2 1
+#define CONFIG_HAS_ETH3 1
+
+#define CONFIG_IPADDR 192.168.1.100
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /opt/nfsroot
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "dtbaddr=400000\0" \
+ "dtbfile=mpc8641_hpcn.dtb\0" \
+ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* EEPROM configuration
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* EEPROM configuration
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
#define CFG_PCI_MEM_BASE 0xC0000000
#define CFG_PCI_MEM_PHYS 0xC0000000
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
--- /dev/null
+/*
+ * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering,
+ * wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if 0
+#define DEBUG 0xFFF
+#endif
+
+#if 0
+#define DEBUG 0x01
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+*/
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
+#define CONFIG_V38B 1 /* ... on V38B board */
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
+#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
+#define CONFIG_HW_WATCHDOG 1 /* has watchdog */
+
+#define CONFIG_NETCONSOLE 1
+
+#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */
+
+#define CFG_XLB_PIPELINING 1 /* gives better performance */
+
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * DDR
+ */
+#define SDRAM_DDR 1 /* is DDR */
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+
+/*
+ * PCI - no suport
+ */
+#undef CONFIG_PCI
+
+/*
+ * Partitions
+ */
+#define CONFIG_MAC_PARTITION 1
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_PING | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_MII | \
+ CFG_CMD_SDRAMi | \
+ CFG_CMD_DATE | \
+ CFG_CMD_USB | \
+ CFG_CMD_FAT)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Boot low with 16 MB Flash
+ */
+# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT16 1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "devno=5\0" \
+ "hostname=V38B_$(devno)\0" \
+ "ipaddr=10.100.99.$(devno)\0" \
+ "netmask=255.255.0.0\0" \
+ "serverip=10.100.10.90\0" \
+ "gatewayip=10.100.254.254\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "bootfile=mpc5200/uImage\0" \
+ "bootcmd=run net_nfs\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
+ "$(netmask):$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;bootm $(kernel_addr) " \
+ "$(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs " \
+ "addip;bootm\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+
+/*
+ * RTC configuration
+ */
+#define CFG_I2C_RTC_ADDR 0x51
+
+/*
+ * Flash configuration - use CFI driver
+ */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_CFI_AMD_RESET 1
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_OVERWRITE 1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_MII 1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG 0x90000404
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x00047801
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333333
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
+/* Status LED */
+
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
+
+#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */
+
+#ifndef __ASSEMBLY__
+/* LEDs */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+ do { \
+ *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
+ } while(0)
+
+#define __led_set(_msk, _st) \
+ do { \
+ if ((_st)) \
+ *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
+ else \
+ *((volatile long *) (CFG_LED_BASE)) |= (_msk); \
+ } while(0)
+
+#define __led_init(_msk, st) \
+ { \
+ *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
+ }
+
+#endif
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AVR32 1
+#define CONFIG_AT32AP 1
+#define CONFIG_AT32AP7000 1
+#define CONFIG_ATSTK1002 1
+#define CONFIG_ATSTK1000 1
+
+#define CONFIG_ATSTK1000_EXT_FLASH 1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ 1000
+
+/*
+ * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
+ * frequency and the peripherals to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL 1
+#define CFG_POWER_MANAGER 1
+#define CFG_OSC0_HZ 20000000
+#define CFG_PLL0_DIV 1
+#define CFG_PLL0_MUL 7
+#define CFG_PLL0_SUPPRESS_CYCLES 16
+#define CFG_CLKDIV_CPU 0
+#define CFG_CLKDIV_HSB 1
+#define CFG_CLKDIV_PBA 2
+#define CFG_CLKDIV_PBB 1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT 0x04
+
+#define CFG_USART1 1
+
+#define CFG_CONSOLE_UART_DEV DEVICE_USART1
+
+/* User serviceable stuff */
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
+
+#define CONFIG_COMMANDS (CFG_CMD_BDI \
+ | CFG_CMD_LOADS \
+ | CFG_CMD_LOADB \
+ /* | CFG_CMD_IMI */ \
+ /* | CFG_CMD_CACHE */ \
+ | CFG_CMD_FLASH \
+ | CFG_CMD_MEMORY \
+ /* | CFG_CMD_NET */ \
+ | CFG_CMD_ENV \
+ /* | CFG_CMD_IRQ */ \
+ | CFG_CMD_BOOTD \
+ | CFG_CMD_CONSOLE \
+ /* | CFG_CMD_EEPROM */ \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_RUN \
+ | CFG_CMD_ECHO \
+ /* | CFG_CMD_I2C */ \
+ | CFG_CMD_REGINFO \
+ /* | CFG_CMD_DATE */ \
+ /* | CFG_CMD_DHCP */ \
+ /* | CFG_CMD_AUTOSCRIPT */ \
+ /* | CFG_CMD_MII */ \
+ | CFG_CMD_MISC \
+ /* | CFG_CMD_SDRAM */ \
+ /* | CFG_CMD_DIAG */ \
+ /* | CFG_CMD_HWFLOW */ \
+ /* | CFG_CMD_SAVES */ \
+ /* | CFG_CMD_SPI */ \
+ /* | CFG_CMD_PING */ \
+ /* | CFG_CMD_MMC */ \
+ /* | CFG_CMD_FAT */ \
+ /* | CFG_CMD_IMLS */ \
+ /* | CFG_CMD_ITEST */ \
+ /* | CFG_CMD_EXT2 */ \
+ )
+
+#include <cmd_confdefs.h>
+
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_PIO2 1
+#define CFG_NR_PIOS 5
+#define CFG_HSDRAMC 1
+
+#define CFG_DCACHE_LINESZ 32
+#define CFG_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#endif
+
+#define CFG_FLASH_BASE 0x00000000
+#define CFG_FLASH_SIZE 0x800000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 135
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE 0x24000000
+#define CFG_INTRAM_SIZE 0x8000
+
+#define CFG_SDRAM_BASE 0x10000000
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 65536
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN (256*1024)
+#define CFG_MALLOC_END \
+ ({ \
+ DECLARE_GLOBAL_DATA_PTR; \
+ CFG_SDRAM_BASE + gd->sdram_size; \
+ })
+#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
+
+#define CFG_DMA_ALLOC_LEN (16384)
+#define CFG_DMA_ALLOC_END (CFG_MALLOC_START)
+#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+/* Allow 2MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
+#define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT "Uboot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 8
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+
+#define CFG_MEMTEST_START \
+ ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
+#define CFG_MEMTEST_END \
+ ({ \
+ DECLARE_GLOBAL_DATA_PTR; \
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
+ })
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
#define CONFIG_MPC8260
#define CPU_ID_STR "MPC8270"
-#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board /*
+#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
/* 256MB SDRAM / 64MB FLASH */
#undef DEBUG
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
#define CFG_PCI_MEM_BASE 0xC0000000
#define CFG_PCI_MEM_PHYS 0xC0000000
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CFG_NAND_BASE CFG_NAND_ADDR
-
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000)
/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+
+/*-----------------------------------------------------------------------
* Cache Configuration
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
#endif
+#define CFG_I2C_OFFSET 0x3000
/* RapdIO Map configuration, mapped 1:1.
*/
struct ft_cxt {
struct boot_param_header *bph;
- int max_size; /* maximum size of tree */
- int overflow; /* set when this happens */
- u8 *p, *pstr, *pres; /* running pointers */
- u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */
- u8 *p_anchor; /* start of constructed area */
- int struct_size, strings_size, res_size;
+ u8 *p_rsvmap;
+ u8 *p_start; /* pointer to beginning of dt_struct */
+ u8 *p_end; /* pointer to end of dt_strings */
+ u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */
};
void ft_begin_node(struct ft_cxt *cxt, const char *name);
+void ft_init_cxt(struct ft_cxt *cxt, void *blob);
void ft_end_node(struct ft_cxt *cxt);
-void ft_begin_tree(struct ft_cxt *cxt);
-int ft_end_tree(struct ft_cxt *cxt);
+void ft_end_tree(struct ft_cxt *cxt);
+void ft_finalize_tree(struct ft_cxt *cxt);
void ft_nop(struct ft_cxt *cxt);
void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz);
void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
-void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end);
+void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end);
void ft_dump_blob(const void *bphp);
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
void *ft_get_prop(void *bphp, const char *propname, int *szp);
+#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
#endif
#define IH_TYPE_FIRMWARE 5 /* Firmware Image */
#define IH_TYPE_SCRIPT 6 /* Script file */
#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */
+#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */
/*
* Compression Types
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ * Jeffrey Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+#ifndef __MPC86xx_H__
+#define __MPC86xx_H__
+
+#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
+
+/*
+ * l2cr values. Look in config_<BOARD>.h for the actual setup
+ */
+#define l2cr 1017
+
+#define L2CR_L2E 0x80000000 /* bit 0 - enable */
+#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
+#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
+#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
+#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
+#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
+#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
+#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
+
+/*
+ * BAT settings. Look in config_<BOARD>.h for the actual setup
+ */
+
+#define BATU_BL_128K 0x00000000
+#define BATU_BL_256K 0x00000004
+#define BATU_BL_512K 0x0000000c
+#define BATU_BL_1M 0x0000001c
+#define BATU_BL_2M 0x0000003c
+#define BATU_BL_4M 0x0000007c
+#define BATU_BL_8M 0x000000fc
+#define BATU_BL_16M 0x000001fc
+#define BATU_BL_32M 0x000003fc
+#define BATU_BL_64M 0x000007fc
+#define BATU_BL_128M 0x00000ffc
+#define BATU_BL_256M 0x00001ffc
+#define BATU_BL_512M 0x00003ffc
+#define BATU_BL_1G 0x00007ffc
+#define BATU_BL_2G 0x0000fffc
+#define BATU_BL_4G 0x0001fffc
+
+#define BATU_VS 0x00000002
+#define BATU_VP 0x00000001
+#define BATU_INVALID 0x00000000
+
+#define BATL_WRITETHROUGH 0x00000040
+#define BATL_CACHEINHIBIT 0x00000020
+#define BATL_MEMCOHERENCE 0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+#define BATL_NO_ACCESS 0x00000000
+
+#define BATL_PP_MSK 0x00000003
+#define BATL_PP_00 0x00000000 /* No access */
+#define BATL_PP_01 0x00000001 /* Read-only */
+#define BATL_PP_10 0x00000002 /* Read-write */
+#define BATL_PP_11 0x00000003
+
+#define BATL_PP_NO_ACCESS BATL_PP_00
+#define BATL_PP_RO BATL_PP_01
+#define BATL_PP_RW BATL_PP_10
+
+#define HID0_XBSEN 0x00000100
+#define HID0_HIGH_BAT_EN 0x00800000
+#define HID0_XAEN 0x00020000
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+ unsigned long freqProcessor;
+ unsigned long freqSystemBus;
+} MPC86xx_SYS_INFO;
+
+#define l1icache_enable icache_enable
+
+void l2cache_enable(void);
+void l1dcache_enable(void);
+
+static __inline__ unsigned long get_hid0 (void)
+{
+ unsigned long hid0;
+ asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
+ return hid0;
+}
+
+static __inline__ unsigned long get_hid1 (void)
+{
+ unsigned long hid1;
+ asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
+ return hid1;
+}
+
+static __inline__ void set_hid0 (unsigned long hid0)
+{
+ asm volatile("mtspr 1008, %0" : : "r" (hid0));
+}
+
+static __inline__ void set_hid1 (unsigned long hid1)
+{
+ asm volatile("mtspr 1009, %0" : : "r" (hid1));
+}
+
+
+static __inline__ unsigned long get_l2cr (void)
+{
+ unsigned long l2cr_val;
+ asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
+ return l2cr_val;
+}
+
+#endif /* _ASMLANGUAGE */
+#endif /* __MPC86xx_H__ */
int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
+#ifdef CFG_NAND_SELECT_DEVICE
+void board_nand_select_device(struct nand_chip *nand, int chip);
+#endif
+
#endif
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
#define PCI_AGP_SIZEOF 12
+/* PCI-X registers */
+
+#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
+#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
+#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
+#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
+
+
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
extern void pci_mpc824x_init (struct pci_controller *hose);
#endif
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
#endif /* _PCI_H */
#define PCI_DEVICE_ID_REALTEK_8139 0x8139
#define PCI_DEVICE_ID_REALTEK_8169 0x8169
+#define PCI_VENDOR_ID_DLINK 0x1186
+#define PCI_DEVICE_ID_DLINK_8139 0x1300
+
#define PCI_VENDOR_ID_XILINX 0x10ee
#define PCI_DEVICE_ID_TURBOPAM 0x4020
#elif defined(CONFIG_NIOS2)
/* XXX empty just to avoid the error */
/************************************************************************/
+#elif defined(CONFIG_V38B)
+
+# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
#else
# error Status LED configuration missing
#endif
--- /dev/null
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(ARCH).a
+
+SOBJS = memset.o
+
+COBJS = board.o interrupts.o avr32_linux.o div64.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <zlib.h>
+#include <asm/byteorder.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/arch/platform.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* CPU-specific hook to allow flushing of caches, etc. */
+extern void prepare_to_boot(void);
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+extern image_header_t header; /* from cmd_bootm.c */
+
+static struct tag *setup_start_tag(struct tag *params)
+{
+ params->hdr.tag = ATAG_CORE;
+ params->hdr.size = tag_size(tag_core);
+
+ params->u.core.flags = 0;
+ params->u.core.pagesize = 4096;
+ params->u.core.rootdev = 0;
+
+ return tag_next(params);
+}
+
+static struct tag *setup_memory_tags(struct tag *params)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ params->hdr.tag = ATAG_MEM;
+ params->hdr.size = tag_size(tag_mem_range);
+
+ params->u.mem_range.addr = bd->bi_dram[i].start;
+ params->u.mem_range.size = bd->bi_dram[i].size;
+
+ params = tag_next(params);
+ }
+
+ return params;
+}
+
+static struct tag *setup_commandline_tag(struct tag *params, char *cmdline)
+{
+ if (!cmdline)
+ return params;
+
+ /* eat leading white space */
+ while (*cmdline == ' ') cmdline++;
+
+ /*
+ * Don't include tags for empty command lines; let the kernel
+ * use its default command line.
+ */
+ if (*cmdline == '\0')
+ return params;
+
+ params->hdr.tag = ATAG_CMDLINE;
+ params->hdr.size =
+ (sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2;
+ strcpy(params->u.cmdline.cmdline, cmdline);
+
+ return tag_next(params);
+}
+
+static struct tag *setup_ramdisk_tag(struct tag *params,
+ unsigned long rd_start,
+ unsigned long rd_end)
+{
+ if (rd_start == rd_end)
+ return params;
+
+ params->hdr.tag = ATAG_RDIMG;
+ params->hdr.size = tag_size(tag_mem_range);
+
+ params->u.mem_range.addr = rd_start;
+ params->u.mem_range.size = rd_end - rd_start;
+
+ return tag_next(params);
+}
+
+static struct tag *setup_clock_tags(struct tag *params)
+{
+ params->hdr.tag = ATAG_CLOCK;
+ params->hdr.size = tag_size(tag_clock);
+ params->u.clock.clock_id = ACLOCK_BOOTCPU;
+ params->u.clock.clock_flags = 0;
+ params->u.clock.clock_hz = gd->cpu_hz;
+
+#ifdef CONFIG_AT32AP7000
+ /*
+ * New kernels don't need this, but we should be backwards
+ * compatible for a while...
+ */
+ params = tag_next(params);
+
+ params->hdr.tag = ATAG_CLOCK;
+ params->hdr.size = tag_size(tag_clock);
+ params->u.clock.clock_id = ACLOCK_HSB;
+ params->u.clock.clock_flags = 0;
+ params->u.clock.clock_hz = pm_get_clock_freq(CLOCK_HSB);
+#endif
+
+ return tag_next(params);
+}
+
+static struct tag *setup_ethernet_tag(struct tag *params,
+ char *addr, int index)
+{
+ char *s, *e;
+ int i;
+
+ params->hdr.tag = ATAG_ETHERNET;
+ params->hdr.size = tag_size(tag_ethernet);
+
+ params->u.ethernet.mac_index = index;
+ params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index];
+
+ s = addr;
+ for (i = 0; i < 6; i++) {
+ params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16);
+ s = e + 1;
+ }
+
+ return tag_next(params);
+}
+
+static struct tag *setup_ethernet_tags(struct tag *params)
+{
+ char name[16] = "ethaddr";
+ char *addr;
+ int i = 0;
+
+ do {
+ addr = getenv(name);
+ if (addr)
+ params = setup_ethernet_tag(params, addr, i);
+ sprintf(name, "eth%daddr", ++i);
+ } while (i < 4);
+
+ return params;
+}
+
+static void setup_end_tag(struct tag *params)
+{
+ params->hdr.tag = ATAG_NONE;
+ params->hdr.size = 0;
+}
+
+void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+ unsigned long addr, unsigned long *len_ptr, int verify)
+{
+ unsigned long data, len = 0;
+ unsigned long initrd_start, initrd_end;
+ unsigned long image_start, image_end;
+ unsigned long checksum;
+ void (*theKernel)(int magic, void *tagtable);
+ image_header_t *hdr;
+ struct tag *params, *params_start;
+ char *commandline = getenv("bootargs");
+
+ hdr = (image_header_t *)addr;
+ image_start = addr;
+ image_end = addr + hdr->ih_size;
+
+ theKernel = (void *)ntohl(hdr->ih_ep);
+
+ /*
+ * Check if there is an initrd image
+ */
+ if (argc >= 3) {
+ SHOW_BOOT_PROGRESS(9);
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ printf("## Loading RAMDISK image at %08lx ...\n", addr);
+
+ memcpy(&header, (char *)addr, sizeof(header));
+ hdr = &header;
+
+ if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+ puts("Bad Magic Number\n");
+ SHOW_BOOT_PROGRESS(-10);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+
+ data = (unsigned long)hdr;
+ len = sizeof(*hdr);
+ checksum = ntohl(hdr->ih_hcrc);
+ hdr->ih_hcrc = 0;
+
+ if (crc32(0, (unsigned char *)data, len) != checksum) {
+ puts("Bad Header Checksum\n");
+ SHOW_BOOT_PROGRESS(-11);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+
+ SHOW_BOOT_PROGRESS(10);
+
+ print_image_hdr(hdr);
+
+ data = addr + sizeof(header);
+ len = ntohl(hdr->ih_size);
+
+ if (verify) {
+ unsigned long csum = 0;
+
+ puts(" Verifying Checksum ... ");
+ csum = crc32(0, (unsigned char *)data, len);
+ if (csum != ntohl(hdr->ih_dcrc)) {
+ puts("Bad Data CRC\n");
+ SHOW_BOOT_PROGRESS(-12);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+ puts("OK\n");
+ }
+
+ SHOW_BOOT_PROGRESS(11);
+
+ if ((hdr->ih_os != IH_OS_LINUX) ||
+ (hdr->ih_arch != IH_CPU_AVR32) ||
+ (hdr->ih_type != IH_TYPE_RAMDISK)) {
+ puts("Not a Linux/AVR32 RAMDISK image\n");
+ SHOW_BOOT_PROGRESS(-13);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+ } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) {
+ ulong tail = ntohl (len_ptr[0]) % 4;
+ int i;
+
+ SHOW_BOOT_PROGRESS (13);
+
+ /* skip kernel length and terminator */
+ data = (ulong) (&len_ptr[2]);
+ /* skip any additional image length fields */
+ for (i = 1; len_ptr[i]; ++i)
+ data += 4;
+ /* add kernel length, and align */
+ data += ntohl (len_ptr[0]);
+ if (tail) {
+ data += 4 - tail;
+ }
+
+ len = ntohl (len_ptr[1]);
+ } else {
+ /* no initrd image */
+ SHOW_BOOT_PROGRESS(14);
+ len = data = 0;
+ }
+
+ if (data) {
+ initrd_start = data;
+ initrd_end = initrd_start + len;
+ } else {
+ initrd_start = 0;
+ initrd_end = 0;
+ }
+
+ SHOW_BOOT_PROGRESS(15);
+
+ params = params_start = (struct tag *)gd->bd->bi_boot_params;
+ params = setup_start_tag(params);
+ params = setup_memory_tags(params);
+ if (initrd_start) {
+ params = setup_ramdisk_tag(params,
+ PHYSADDR(initrd_start),
+ PHYSADDR(initrd_end));
+ }
+ params = setup_commandline_tag(params, commandline);
+ params = setup_clock_tags(params);
+ params = setup_ethernet_tags(params);
+ setup_end_tag(params);
+
+ printf("\nStarting kernel at %p (params at %p)...\n\n",
+ theKernel, params_start);
+
+ prepare_to_boot();
+
+ theKernel(ATAG_MAGIC, params_start);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+
+#include <asm/initcalls.h>
+#include <asm/sections.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const char version_string[] =
+ U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " CONFIG_IDENT_STRING;
+
+unsigned long monitor_flash_len;
+
+/*
+ * Begin and end of memory area for malloc(), and current "brk"
+ */
+static unsigned long mem_malloc_start = 0;
+static unsigned long mem_malloc_end = 0;
+static unsigned long mem_malloc_brk = 0;
+
+/* The malloc area is wherever the board wants it to be */
+static void mem_malloc_init(void)
+{
+ mem_malloc_start = CFG_MALLOC_START;
+ mem_malloc_end = CFG_MALLOC_END;
+ mem_malloc_brk = mem_malloc_start;
+
+ printf("malloc: Using memory from 0x%08lx to 0x%08lx\n",
+ mem_malloc_start, mem_malloc_end);
+
+ memset ((void *)mem_malloc_start, 0,
+ mem_malloc_end - mem_malloc_start);
+}
+
+void *sbrk(ptrdiff_t increment)
+{
+ unsigned long old = mem_malloc_brk;
+ unsigned long new = old + increment;
+
+ if ((new < mem_malloc_start) || (new > mem_malloc_end))
+ return NULL;
+
+ mem_malloc_brk = new;
+ return ((void *)old);
+}
+
+static int init_baudrate(void)
+{
+ char tmp[64];
+ int i;
+
+ i = getenv_r("baudrate", tmp, sizeof(tmp));
+ if (i > 0) {
+ gd->baudrate = simple_strtoul(tmp, NULL, 10);
+ } else {
+ gd->baudrate = CONFIG_BAUDRATE;
+ }
+ return 0;
+}
+
+
+static int display_banner (void)
+{
+ printf ("\n\n%s\n\n", version_string);
+ printf ("U-Boot code: %p -> %p data: %p -> %p\n",
+ _text, _etext, _data, _end);
+ return 0;
+}
+
+void hang(void)
+{
+ for (;;) ;
+}
+
+static int display_dram_config (void)
+{
+ int i;
+
+ puts ("DRAM Configuration:\n");
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+ print_size (gd->bd->bi_dram[i].size, "\n");
+ }
+
+ return 0;
+}
+
+static void display_flash_config (void)
+{
+ puts ("Flash: ");
+ print_size(gd->bd->bi_flashsize, " ");
+ printf("at address 0x%08lx\n", gd->bd->bi_flashstart);
+}
+
+void start_u_boot (void)
+{
+ gd_t gd_data;
+
+ /* Initialize the global data pointer */
+ memset(&gd_data, 0, sizeof(gd_data));
+ gd = &gd_data;
+
+ monitor_flash_len = _edata - _text;
+
+ /* Perform initialization sequence */
+ cpu_init();
+ timer_init();
+ env_init();
+ init_baudrate();
+ serial_init();
+ console_init_f();
+ display_banner();
+
+ board_init_memories();
+ mem_malloc_init();
+
+ gd->bd = malloc(sizeof(bd_t));
+ memset(gd->bd, 0, sizeof(bd_t));
+ gd->bd->bi_baudrate = gd->baudrate;
+ gd->bd->bi_dram[0].start = CFG_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->sdram_size;
+
+ board_init_info();
+ flash_init();
+
+ if (gd->bd->bi_flashsize)
+ display_flash_config();
+ if (gd->bd->bi_dram[0].size)
+ display_dram_config();
+
+ gd->bd->bi_boot_params = malloc(CFG_BOOTPARAMS_LEN);
+ if (!gd->bd->bi_boot_params)
+ puts("WARNING: Cannot allocate space for boot parameters\n");
+
+ /* initialize environment */
+ env_relocate();
+
+ devices_init();
+ jumptable_init();
+ console_init_r();
+
+ for (;;) {
+ main_loop();
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ *
+ * Based on former do_div() implementation from asm-parisc/div64.h:
+ * Copyright (C) 1999 Hewlett-Packard Co
+ * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ *
+ * Generic C version of 64bit/32bit division and modulo, with
+ * 64bit result and 32bit remainder.
+ *
+ * The fast case for (n>>32 == 0) is handled inline by do_div().
+ *
+ * Code generated for this function might be very inefficient
+ * for some CPUs. __div64_32() can be overridden by linking arch-specific
+ * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S.
+ */
+
+#include <linux/types.h>
+
+#include <asm/div64.h>
+
+uint32_t __div64_32(uint64_t *n, uint32_t base)
+{
+ uint64_t rem = *n;
+ uint64_t b = base;
+ uint64_t res, d = 1;
+ uint32_t high = rem >> 32;
+
+ /* Reduce the thing a bit first */
+ res = 0;
+ if (high >= base) {
+ high /= base;
+ res = (uint64_t) high << 32;
+ rem -= (uint64_t) (high*base) << 32;
+ }
+
+ while ((int64_t)b > 0 && b < rem) {
+ b = b+b;
+ d = d+d;
+ }
+
+ do {
+ if (rem >= b) {
+ rem -= b;
+ res += d;
+ }
+ b >>= 1;
+ d >>= 1;
+ } while (d);
+
+ *n = res;
+ return rem;
+}
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+
+void enable_interrupts(void)
+{
+ asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
+}
+
+int disable_interrupts(void)
+{
+ unsigned long sr;
+
+ sr = sysreg_read(SR);
+ asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET));
+
+ return SYSREG_BFEXT(GM, sr);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ /*
+ * r12: void *b
+ * r11: int c
+ * r10: size_t len
+ *
+ * Returns b in r12
+ */
+ .text
+
+ .global memset
+ .type memset, @function
+ .align 2
+memset:
+ mov r9, r12
+ mov r8, r12
+ or r11, r11, r11 << 8
+ andl r9, 3, COH
+ brne 1f
+
+2: or r11, r11, r11 << 16
+ sub r10, 4
+ brlt 5f
+
+ /* Let's do some real work */
+4: st.w r8++, r11
+ sub r10, 4
+ brge 4b
+
+ /*
+ * When we get here, we've got less than 4 bytes to set. r10
+ * might be negative.
+ */
+5: sub r10, -4
+ reteq r12
+
+ /* Fastpath ends here, exactly 32 bytes from memset */
+
+ /* Handle unaligned count or pointer */
+ bld r10, 1
+ brcc 6f
+ st.b r8++, r11
+ st.b r8++, r11
+ bld r10, 0
+ retcc r12
+6: st.b r8++, r11
+ mov pc, lr
+
+ /* Handle unaligned pointer */
+1: sub r10, 4
+ brlt 5b
+ add r10, r9
+ lsl r9, 1
+ add pc, r9
+ st.b r8++, r11
+ st.b r8++, r11
+ st.b r8++, r11
+ rjmp 2b
+
+ .size memset, . - memset
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#endif
#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
- defined(CONFIG_E500)
+ defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)
#endif /* CFG_EXTBDINFO */
s = getenv ("ethaddr");
-#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210)
+#if defined (CONFIG_MBX) || \
+ defined (CONFIG_RPXCLASSIC) || \
+ defined(CONFIG_IAD210) || \
+ defined(CONFIG_V38B)
if (s == NULL)
board_get_enetaddr (bd->bi_enetaddr);
else
}
#endif
+#ifdef CFG_ID_EEPROM
+ mac_read_from_eeprom();
+#endif
+
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
load_sernum_ethaddr ();
#
include $(TOPDIR)/config.mk
-include board/$(BOARDDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-LDSCRIPT= board/$(BOARDDIR)/u-boot.lds
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = nand_boot.o ndfc.o sdram.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
-ALL = u-boot-spl u-boot-spl.bin u-boot-spl-16k.bin
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
-u-boot-spl-16k.bin: u-boot-spl
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-u-boot-spl.bin: u-boot-spl
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-u-boot-spl: $(OBJS)
- $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
- -Map u-boot-spl.map -o u-boot-spl
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
# create symbolic links for common files
# from cpu directory
-ndfc.c:
- @rm -f ndfc.c
- ln -s ../cpu/ppc4xx/ndfc.c ndfc.c
+$(obj)ndfc.c:
+ @rm -f $(obj)ndfc.c
+ ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
-resetvec.S:
- @rm -f resetvec.S
- ln -s ../cpu/ppc4xx/resetvec.S resetvec.S
+$(obj)resetvec.S:
+ @rm -f $(obj)resetvec.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
-start.S:
- @rm -f start.S
- ln -s ../cpu/ppc4xx/start.S start.S
+$(obj)start.S:
+ @rm -f $(obj)start.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
-init.S:
- @rm -f init.S
- ln -s ../board/amcc/sequoia/init.S init.S
+$(obj)init.S:
+ @rm -f $(obj)init.S
+ ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S
+
+$(obj)sdram.c:
+ @rm -f $(obj)sdram.c
+ ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
-sdram.c:
- @rm -f sdram.c
- ln -s ../board/amcc/sequoia/sdram.c sdram.c
+# from nand_spl directory
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
#########################################################################
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
# endif
#endif
+#if defined(CONFIG_MPC86XX_TSEC1)
+ tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC2)
+ tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC3)
+ tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC4)
+ tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME);
+#endif
+
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
{ IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", },
{ IH_TYPE_SCRIPT, "script", "Script", },
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
+ { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", },
{ -1, "", "", },
};
projects / platform / kernel / u-boot.git / commitdiff