Changes since U-Boot 1.1.4:
======================================================================
-* Merge the new NAND code (testing-NAND brach)
-
++* Merge the new NAND code (testing-NAND brach); see doc/README.nand
+ Rewrite of NAND code based on what is in 2.6.12 Linux kernel
+ Patch by Ladislav Michl, 29 Jun 2005
+
+* Add lowboot target to mcc200 board
+ Patch by Stefan Roese, 4 Mar 2006
+
+* Fix problem with flash_get_size() from CFI driver update
+ Patch by Stefan Roese, 1 Mar 2006
+
+* Make CFG_NO_FLASH work on ARM systems
+ Patch by Markus Klotzbuecher, 27 Feb 2006
+
+* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
+ use hush shell.
+
+* Convert mcc200 to use common CFI flash driver
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Add env-variable "unlock" to handle initial state of sectors
+ (locked/unlocked).
+
+ Only the U-Boot image and it's environment is protected,
+ all other sectors are unprotected (unlocked) if flash
+ hardware protection is used (CFG_FLASH_PROTECTION) and
+ the environment variable "unlock" is set to "yes".
+
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Update drivers/cfi_flash.c:
+ - find_sector() called in both versions of flash_write_cfiword()
+ Patch by Peter Pearse, 27th Feb 2006
+
+* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
+ Patch by Jose Maria Lopez, 16 Jan 2006
+
+* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
+ Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
+
+* Changes/fixes for drivers/cfi_flash.c:
+ We *should* check if there are any error bits if the previous call
+ returned ERR_OK (Otherwise we will have output an error message in
+ flash_status_check() already.) The original code would only check for
+ error bits if flash_status_check() returns ERR_TIMEOUT.
+ Patch by Marcus Hall, 23 Aug 2005
+
+* Changes/fixes for drivers/cfi_flash.c:
+ - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
+ - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
+ Patch by Sangmoon Kim, 19 Aug 2005
+
+* Fixes for drivers/cfi_flash.c:
+ - Fix wrong timeout value usage in flash_status_check()
+ - Round write_tout up when converting to msec in flash_get_size()
+ - Remove clearing flash status at the end of flash_write_cfibuffer()
+ which sets Intel 28F640J3 flash back to command mode on CSB472
+ Patch by Tolunay Orkun, 02 July 2005
+
+* Add basic support for the SMMACO4 Board from PanDaCom.
+ Patch by Heiko Schocher, 20 Feb 2006
+
+* Add GIT version information (commid ID) to untagged U-Boot versions
+
+ As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
+ of all unreleased (untagged) U-Boot images will be automatically
+ extended upon compiletime with a part of the GIT commit ID and
+ possibly with "dirty" if uncommited changes are detected.
+
+ Here an example for the resulting version:
+ "U-Boot 1.1.4-g3457ac18-dirty"
+
+ The version is now maintained in the toplevel Makefile and the
+ version headers are autogenerated.
+
+ Patch by Stefan Roese, 9 Feb 2006
+
* Update default environment for INKA4x00 board.
+* Convert CPCI750 to use common CFI flash driver
+ Patch by Reinhard Arlt, 8 Feb 2006
+
+* Various changes to esd HH405 board specific files
+ Patch by Matthias Fuchs, 07 Feb 2006
+
* Cleanup U-Boot boot messages on ARM.
To match the U-Boot user interface on ARM platforms to the U-Boot
LIST_5xxx=" \
cpci5200 icecube_5100 icecube_5200 EVAL5200 \
- pf5200 PM520 Total5100 Total5200 \
- Total5200_Rev2 TQM5200_auto o2dnt \
+ mcc200 o2dnt pf5200 PM520 \
+ Total5100 Total5200 Total5200_Rev2 TQM5200_auto \
"
#########################################################################
ap920t ap922_XA10 ap926ejs ap946es \
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
- mx1ads mx1fs2 omap1510inn omap1610h2 \
- omap1610inn omap730p2 scb9328 smdk2400 \
- smdk2410 trab VCMA9 versatile \
- versatileab versatilepb voiceblue
+ mx1ads mx1fs2 netstar omap1510inn \
+ omap1610h2 omap1610inn omap730p2 scb9328 \
+ smdk2400 smdk2410 trab VCMA9 \
+ versatile versatileab versatilepb voiceblue
"
#########################################################################
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# MA 02111-1307 USA
#
+VERSION = 1
+PATCHLEVEL = 1
+SUBLEVEL = 4
+EXTRAVERSION =
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+VERSION_FILE = include/version_autogenerated.h
+
HOSTARCH := $(shell uname -m | \
sed -e s/i.86/i386/ \
-e s/sun4u/sparc64/ \
LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/cpu/libcpu.a
LIBS += common/libcommon.a
+ LIBS += $(BOARDLIBS)
.PHONY : $(LIBS)
# Add GCC lib
u-boot.img: u-boot.bin
./tools/mkimage -A $(ARCH) -T firmware -C none \
-a $(TEXT_BASE) -e 0 \
- -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
-u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
+u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
--start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
$(SUBDIRS):
$(MAKE) -C $@ all
+version:
+ @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
+ echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
+ echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
+ $(TOPDIR)) >> $(VERSION_FILE); \
+ echo "\"" >> $(VERSION_FILE)
+
gdbtools:
$(MAKE) -C tools/gdb || exit 1
}
@./mkconfig -a IceCube ppc mpc5xxx icecube
-inka4x0_config: unconfig
+inka4x0_config: unconfig
@./mkconfig inka4x0 ppc mpc5xxx inka4x0
+mcc200_config \
+mcc200_lowboot_config: unconfig
+ @ >include/config.h
+ @[ -z "$(findstring lowboot_,$@)" ] || \
+ { echo "TEXT_BASE = 0xFE000000" >board/mcc200/config.tmp ; \
+ echo "... with lowboot configuration" ; \
+ }
+ @./mkconfig mcc200 ppc mpc5xxx mcc200
+
o2dnt_config:
- @./mkconfig -a o2dnt ppc mpc5xxx o2dnt
+ @./mkconfig o2dnt ppc mpc5xxx o2dnt
pf5200_config: unconfig
- @./mkconfig -a pf5200 ppc mpc5xxx pf5200 esd
+ @./mkconfig pf5200 ppc mpc5xxx pf5200 esd
PM520_config \
PM520_DDR_config \
}
@./mkconfig -a PM520 ppc mpc5xxx pm520
+smmaco4_config: unconfig
+ @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
+
+spieval_config: unconfig
+ echo "#define CONFIG_CS_AUTOCONF">>include/config.h
+ echo "... with automatic CS configuration"
+ @./mkconfig -a spieval ppc mpc5xxx tqm5200
+
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
}
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
-spieval_config: unconfig
- echo "#define CONFIG_CS_AUTOCONF">>include/config.h
- echo "... with automatic CS configuration"
- @./mkconfig -a spieval ppc mpc5xxx tqm5200
-
#########################################################################
## MPC8xx Systems
#########################################################################
mx1fs2_config : unconfig
@./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx
+ netstar_32_config \
+ netstar_config: unconfig
+ @if [ "$(findstring _32_,$@)" ] ; then \
+ echo "... 32MB SDRAM" ; \
+ echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>include/config.h ; \
+ else \
+ echo "... 64MB SDRAM" ; \
+ echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>include/config.h ; \
+ fi
+ @./mkconfig -a netstar arm arm925t netstar
+
omap1510inn_config : unconfig
@./mkconfig $(@:_config=) arm arm925t omap1510inn
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-print0 \
| xargs -0 rm -f
- rm -f $(OBJS) *.bak tags TAGS
+ rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
rm -fr *.*~
rm -f u-boot u-boot.map u-boot.hex $(ALL)
rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <pci.h>
#include <sm501.h>
-
#ifdef CONFIG_VIDEO_SM501
#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+/*
+ * Get version of HH405 board from GPIO's
+ */
int board_revision(void)
{
unsigned long osrh_reg;
unsigned long value;
/*
- * Get version of HH405 board from GPIO's
- */
-
- /*
* Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
*/
osrh_reg = in32(GPIO0_OSRH);
if (value & 0x80000000) {
/* Revision 1.0 or 1.1 detected */
- return 0x0101;
+ return 1;
} else {
if (value & 0x00400000) {
/* unused */
- return 0x0103;
+ return 3;
} else {
- /* Revision >= 2.0 detected */
- /* rev. 2.x uses four SM501 GPIOs for revision coding */
- return 0x0200;
+ return 2;
}
}
}
return 0;
}
+int cf_enable(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int i;
+
+ volatile unsigned short *fpga_ctrl =
+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ volatile unsigned short *fpga_status =
+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
+
+ if (gd->board_type >= 2) {
+ if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
+ if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
+ *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
+
+ for (i=0; i<300; i++)
+ udelay(1000);
+
+ *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
+
+ for (i=0; i<20; i++)
+ udelay(1000);
+ }
+ } else {
+ *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
+ *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
+ }
+ }
+
+ return 0;
+}
int misc_init_r (void)
{
* Write Board revision into FPGA
*/
*fpga_ctrl |= gd->board_type & 0x0003;
- if (gd->board_type >= 0x0200) {
- *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
- }
/*
* Setup and enable EEPROM write protection
contrast0 = simple_strtol(str, NULL, 16);
if (contrast0 > 255) {
printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
- contrast0 = 0;
+ contrast0 = 0xffffffff;
}
}
*/
*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
/*
- * Set lcd clock (small epson)
+ * Set lcd clock (small epson), enable 1-wire interface
*/
- *fpga_ctrl |= LCD_CLK_08330;
+ *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
lcd_setup(0, 1);
lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
puts("VGA: SM501 with 8 MB ");
if (strcmp(str, "ppc221") == 0) {
printf("(800*600, %dbpp)\n", BPP);
+ *lcd_backlight = 0x002d; /* max. allowed brightness */
} else if (strcmp(str, "ppc231") == 0) {
printf("(1024*768, %dbpp)\n", BPP);
+ *lcd_backlight = 0x0000;
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
#endif /* CONFIG_VIDEO_SM501 */
}
+ cf_enable();
+
return (0);
}
}
gd->board_type = board_revision();
- printf(", Rev %ld.%ld)\n",
- (gd->board_type >> 8) & 0xff,
- gd->board_type & 0xff);
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
+ printf(", Rev %ld.x)\n", gd->board_type);
return 0;
}
}
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
+ DECLARE_GLOBAL_DATA_PTR;
+
volatile unsigned short *fpga_mode =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ volatile unsigned short *fpga_status =
+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) { /* assert RESET */
- *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
- } else { /* release RESET */
- *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+ if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
+ (gd->board_type < 2)) {
+ /*
+ * Assert or deassert CompactFlash Reset Pin
+ */
+ if (on) { /* assert RESET */
+ cf_enable();
+ *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+ } else { /* release RESET */
+ *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+ }
}
}
#endif /* CONFIG_IDE_RESET */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
- #include <linux/mtd/nand.h>
+ #include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
strcat(str, " (Missing bd_type!");
}
- sprintf(str2, ", Rev %ld.%ld)",
- (gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
+ sprintf(str2, ", Rev %ld.x)", gd->board_type);
strcat(str, str2);
strcpy(info, str);
} else {
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
- return (addr & 0xfffffffe);
+ addr &= 0xfffffffe;
+#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
+ addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
+#endif
+ return addr;
}
return 0;
}
#endif /* CONFIG_VIDEO_SM501 */
+
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
NAND FLASH commands and notes
++
++See NOTE below!!!
++
++
# (C) Copyright 2003
# Dave Ellis, SIXNET, dge@sixnetio.com
#
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
++
++
++
++NOTE:
++=====
++
++We now use a complete rewrite of the NAND code based on what is in
++2.6.12 Linux kernel.
++
++The old NAND handling code has been re-factored and is now confined
++to only board-specific files and - unfortunately - to the DoC code
++(see below). A new configuration variable has been introduced:
++CFG_NAND_LEGACY, which has to be defined in the board config file if
++that board uses legacy code. If CFG_NAND_LEGACY is defined, the board
++specific config.mk file should also have "BOARDLIBS =
++drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND
++approach (PPChameleon and netstar at the moment) no variable is
++necessary, but the config.mk should have "BOARDLIBS =
++drivers/nand/libnand.a".
++
++The necessary changes have been made to all affected boards, and no
++build breakage has been introduced, except for NETTA and NETTA_ISDN
++targets from MAKEALL. This is due to the fact that these two boards
++use JFFS, which has been adopted to use the new NAND, and at the same
++time use NAND in legacy mode. The breakage will disappear when the
++board-specific code is changed to the new NAND.
++
++As mentioned above, the legacy code is still used by the DoC subsystem.
++The consequence of this is that the legacy NAND can't be removed from
++the tree until the DoC is ported to use the new NAND support (or boards
++with DoC will break).
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#else
#define CONFIG_VIDEO_SM501_16BPP
#endif
+#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+ #define CFG_NAND_LEGACY
+
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
#define CFG_FPGA_CTRL_CF_RESET 0x0040
#define CFG_FPGA_CTRL_PS2_PWR 0x0080
-#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */
+#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */
#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
#define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
+#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
+
+#define CFG_FPGA_STATUS_CF_DETECT 0x8000
#define LCD_CLK_OFF 0x0000 /* Off */
#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
projects / kernel / u-boot.git / commitdiff