static u32 gi_l5f3_set_column_add[] = {0x0100002a, 0x0000003f};
static u32 gi_l5f3_set_row_add[] = {0x0100002b, 0x000000df};
/* static u32 gi_l5f3_set_address_mode[] = {0x00004036}; */
-static u32 gi_l5f3_set_address_mode[] = {0x0000C036};
+static u32 gi_l5f3_set_address_mode[] = {0x00000036};
static u32 gi_l5f3_set_pixel_format[] = {0x0000773a};
static u32 gi_l5f3_set_te_scanline[] = {0x00000044};
static u32 gi_l5f3_set_tear_on[] = {0x00000035};
hw_ctx->eot_disable = 0x0;
hw_ctx->lp_byteclk = 0x0;
hw_ctx->clk_lane_switch_time_cnt = 0xa0014;
- hw_ctx->dphy_param = 0x150a600f;
+ hw_ctx->dphy_param = 0x120a2b07;
hw_ctx->dbi_bw_ctrl = 0x820;
-
if (dev_priv->platform_rev_id == MDFLD_PNW_A0)
- hw_ctx->mipi = PASS_FROM_SPHY_TO_AFE |
- SEL_FLOPPED_HSTX | TE_TRIGGER_GPIO_PIN;
+ hw_ctx->mipi = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
else
- hw_ctx->mipi = PASS_FROM_SPHY_TO_AFE | TE_TRIGGER_GPIO_PIN;
+ hw_ctx->mipi = PASS_FROM_SPHY_TO_AFE;
/*set up func_prg*/
hw_ctx->dsi_func_prg = (0xa000 | lane_count);
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
OSPM_UHB_FORCE_POWER_ON))
return -EAGAIN;
+
/* HW-Reset */
if (p_funcs && p_funcs->reset)
p_funcs->reset(dsi_config, RESET_FROM_OSPM_RESUME);
/* Enable DSI Controller */
REG_WRITE(regs->device_ready_reg, BIT0);
- /*panel drvIC init*/
- if (p_funcs->drv_ic_init)
- p_funcs->drv_ic_init(dsi_config, 0);
-
/*
* Different panel may have different ways to have
* panel turned on. Support it!
goto power_on_err;
}
}
+
power_on_err:
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
return err;
0,
CMD_DATA_SRC_PIPE,
MDFLD_DSI_SEND_PACKAGE);
+
+ mdfld_dsi_gen_fifo_ready(dev, GEN_FIFO_STAT_REG,
+ HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
+ REG_WRITE(HS_GEN_CTRL_REG, (1 << WORD_COUNTS_POS) | GEN_READ_0);
+
dbi_output->dsr_fb_update_done = true;
- mdfld_dsi_cmds_kick_out(sender);
update_fb_out0:
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
{
static bool b_gpio_required[PSB_NUM_PIPE] = {0};
int ret = 0;
- struct mdfld_dsi_hw_registers *regs = NULL;
- struct drm_device *dev = dsi_config->dev;
-
- PSB_DEBUG_ENTRY("\n");
-
- regs = &dsi_config->regs;
if (reset_from == RESET_FROM_BOOT_UP) {
b_gpio_required[dsi_config->pipe] = false;
}
b_gpio_required[dsi_config->pipe] = true;
-
- /* if FW initialized in video mode , use power off/on,
- display island to reset total display controller*/
- if (!(REG_READ(regs->pipeconf_reg) & BIT26) &&
- (REG_READ(regs->mipi_reg) & BIT31)) {
- /*reset the display island
- to switch DPI to DBI*/
- printk(KERN_INFO "power on/off to reset\n");
- ospm_power_island_down(OSPM_DISPLAY_ISLAND);
- ospm_power_island_up(OSPM_DISPLAY_ISLAND);
+#if 0
+ /*
+ * for get date from panel side is not easy, so here use
+ * display side setting to judge wheather panel have enabled or
+ * not by FW
+ */
+ if ((REG_READ(regs->dpll_reg) & BIT31) &&
+ (REG_READ(regs->pipeconf_reg) & BIT30) &&
+ (REG_READ(regs->mipi_reg) & BIT31)) {
+ PSB_DEBUG_ENTRY("FW has initialized the panel, skip"
+ "reset during boot up\n.");
+ psb_enable_vblank(dev, dsi_config->pipe);
+ goto fun_exit;
}
+#endif
}
if (b_gpio_required[dsi_config->pipe]) {
mdfld_ms_delay(MSLEEP, 50);
- /*mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info);*/
+ mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info);
power_err:
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
return err;
struct mdfld_dsi_pkg_sender *sender = NULL;
int ret = IMG_TRUE;
int err = 0;
- u32 damage_mask = 0;
u32 dsplinoff_reg = DSPALINOFF;
u32 dspsurf_reg = DSPASURF;
goto fun_exit;
}
- if (pipe == 0)
- damage_mask = dev_priv->dsr_fb_update & MDFLD_DSR_DAMAGE_MASK_0;
- else if (pipe == 2)
- damage_mask = dev_priv->dsr_fb_update & MDFLD_DSR_DAMAGE_MASK_2;
- else
- goto fun_exit;
-
- if (damage_mask) {
- sender = mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
+ sender = mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
- /* refresh plane changes */
- REG_WRITE(dsplinoff_reg, REG_READ(dsplinoff_reg));
- REG_WRITE(dspsurf_reg, REG_READ(dspsurf_reg));
- REG_READ(dspsurf_reg);
+ /* refresh plane changes */
+ REG_WRITE(dsplinoff_reg, REG_READ(dsplinoff_reg));
+ REG_WRITE(dspsurf_reg, REG_READ(dspsurf_reg));
+ REG_READ(dspsurf_reg);
- err = mdfld_dsi_send_dcs(sender,
- write_mem_start,
- NULL,
- 0,
- CMD_DATA_SRC_PIPE,
- MDFLD_DSI_SEND_PACKAGE);
+ err = mdfld_dsi_send_dcs(sender,
+ write_mem_start,
+ NULL,
+ 0,
+ CMD_DATA_SRC_PIPE,
+ MDFLD_DSI_SEND_PACKAGE);
- if (err) {
- DRM_ERROR(
- "Error returned from mdfld_dsi_send_dcs: %d\n", ret);
- ret = IMG_FALSE;
- goto fun_exit;
- }
- dev_priv->dsr_fb_update &= ~damage_mask;
+ if (err) {
+ DRM_ERROR(
+ "Error returned from mdfld_dsi_send_dcs: %d\n", ret);
+ ret = IMG_FALSE;
+ goto fun_exit;
}
fun_exit:
PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
- if (is_panel_vid_or_cmd(dev) == MDFLD_DSI_ENCODER_DPI) {
- if (arg->overlay.b_wait_vblank)
- overlay_wait_vblank(dev,
- file_priv,
- arg->overlay.OVADD);
- }
+ if (arg->overlay.b_wait_vblank)
+ overlay_wait_vblank(dev,
+ file_priv,
+ arg->overlay.OVADD);
if (IS_MDFLD(dev)) {
- if (is_panel_vid_or_cmd(dev) == MDFLD_DSI_ENCODER_DBI) {
- if ((((arg->overlay.OVADD & OV_PIPE_SELECT) >>
- OV_PIPE_SELECT_POS) == OV_PIPE_A)) {
+ if ((((arg->overlay.OVADD & OV_PIPE_SELECT) >> OV_PIPE_SELECT_POS) == OV_PIPE_A)
+ && (!(dev_priv->dsr_fb_update & MDFLD_DSR_OVERLAY_0))) {
#ifndef CONFIG_MDFLD_DSI_DPU
- mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_0, 0, 0);
- if (dev_priv->b_async_flip_enable &&
- dev_priv->async_flip_update_fb)
- dev_priv->async_flip_update_fb(dev, 0);
+ mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_0, 0, 0);
#else
- /*TODO: report overlay damage*/
+ /*TODO: report overlay damage*/
#endif
- }
+ }
- if ((((arg->overlay.OVADD & OV_PIPE_SELECT) >>
- OV_PIPE_SELECT_POS) == OV_PIPE_C)) {
+ if ((((arg->overlay.OVADD & OV_PIPE_SELECT) >> OV_PIPE_SELECT_POS) == OV_PIPE_C)
+ && (!(dev_priv->dsr_fb_update & MDFLD_DSR_OVERLAY_2))) {
#ifndef CONFIG_MDFLD_DSI_DPU
- mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_2, 0, 0);
- if (dev_priv->b_async_flip_enable &&
- dev_priv->async_flip_update_fb)
- dev_priv->async_flip_update_fb(dev, 2);
+ mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_OVERLAY_2, 0, 0);
#else
- /*TODO: report overlay damage*/
+ /*TODO: report overlay damage*/
#endif
- }
}
if (arg->overlay.IEP_ENABLED) {
case DRM_MODE_DPMS_SUSPEND:
/* Enable the DPLL */
temp = REG_READ(dpll_reg);
+
if ((temp & DPLL_VCO_ENABLE) == 0) {
/* When ungating power of DPLL, needs to wait 0.5us before enable the VCO */
if (temp & MDFLD_PWR_GATE_EN) {
* FIXME: better to move it into the MIPI
* encoder DPMS off process.
*/
- if ((get_panel_type(dev, pipe) == AUO_SC1_CMD) &&
- pipe < sizeof(dev_priv->dsi_configs)/sizeof(*(dev_priv->dsi_configs))) {
+ if (get_panel_type(dev, pipe) == AUO_SC1_CMD && pipe < sizeof(dev_priv->dsi_configs)/sizeof(*(dev_priv->dsi_configs))) {
dsi_config =
dev_priv->dsi_configs[pipe];
regs = &dsi_config->regs;
}
#endif
}
- if (get_panel_type(dev, pipe) == GI_SONY_CMD) {
- /*reset the display island to switch DPI to DBI*/
- ospm_power_island_down(OSPM_DISPLAY_ISLAND);
- ospm_power_island_up(OSPM_DISPLAY_ISLAND);
- }
}
break;
}
PSB_DEBUG_ENTRY("\n");
if (IS_MDFLD(dev) && (dev_priv->platform_rev_id != MDFLD_PNW_A0) &&
- !is_panel_vid_or_cmd(dev))
+ !is_panel_vid_or_cmd(dev) &&
+ (get_panel_type(dev, pipe) != GI_SONY_CMD))
return mdfld_enable_te(dev, pipe);
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) {
PSB_DEBUG_ENTRY("\n");
if (IS_MDFLD(dev) && (dev_priv->platform_rev_id != MDFLD_PNW_A0) &&
- !is_panel_vid_or_cmd(dev))
+ !is_panel_vid_or_cmd(dev) &&
+ (get_panel_type(dev, pipe) != GI_SONY_CMD))
mdfld_disable_te(dev, pipe);
dev_priv->b_vblank_enable = false;