;;
;; Normal loads with a 16bit destination.
;;
-;; Yes, both cases are needed.
-;;
+
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=&r")
(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
(const_int 1)
(match_operand:HI 2 "immediate_operand" "n")))]
- ""
- "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
- [(set_attr "cc" "clobber")
- (set_attr "length" "6")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=&r")
- (subreg:HI (zero_extract:SI
- (match_operand:HI 1 "register_operand" "r")
- (const_int 1)
- (match_operand:HI 2 "immediate_operand" "n")) 2))]
- ""
+ "TARGET_H8300"
"sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
[(set_attr "cc" "clobber")
(set_attr "length" "6")])
;;
;; Inverted loads with a 16bit destination.
;;
-;; Yes, all four cases are needed.
-;;
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=&r")
(match_operand:HI 3 "p_operand" "P"))
(const_int 1)
(match_operand:HI 2 "const_int_operand" "n")))]
- "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
- "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
- [(set_attr "cc" "clobber")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=&r")
- (and:HI (not:HI
- (lshiftrt:HI
- (match_operand:HI 1 "bit_operand" "Ur")
- (match_operand:HI 2 "const_int_operand" "n")))
- (const_int 1)))]
- ""
- "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
- [(set_attr "cc" "clobber")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=&r")
- (and:HI (not:HI
- (subreg:HI
- (lshiftrt:SI
- (match_operand:SI 1 "register_operand" "Ur")
- (match_operand:SI 2 "const_int_operand" "n")) 2))
- (const_int 1)))]
- "INTVAL (operands[2]) < 16"
- "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
- [(set_attr "cc" "clobber")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=&r")
- (and:HI (not:HI
- (subreg:HI
- (lshiftrt:SI
- (match_operand:SI 1 "bit_operand" "Ur")
- (match_operand:SI 2 "const_int_operand" "n")) 0))
- (const_int 1)))]
- "(TARGET_H8300H || TARGET_H8300S)
- && INTVAL (operands[2]) < 16"
+ "TARGET_H8300
+ && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
"sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
[(set_attr "cc" "clobber")
(set_attr "length" "8")])