}
break;
}
+ case nir_op_iadd_sat: {
+ Temp src0 = get_alu_src(ctx, instr->src[0]);
+ Temp src1 = as_vgpr(ctx, get_alu_src(ctx, instr->src[1]));
+ if (dst.regClass() == v2b) {
+ Instruction* add_instr =
+ bld.vop3(aco_opcode::v_add_i16, Definition(dst), src0, src1).instr;
+ add_instr->vop3().clamp = 1;
+ } else if (dst.regClass() == v1) {
+ Instruction* add_instr =
+ bld.vop3(aco_opcode::v_add_i32, Definition(dst), src0, src1).instr;
+ add_instr->vop3().clamp = 1;
+ } else {
+ isel_err(&instr->instr, "Unimplemented NIR instr bit size");
+ }
+ break;
+ }
case nir_op_uadd_carry: {
Temp src0 = get_alu_src(ctx, instr->src[0]);
Temp src1 = get_alu_src(ctx, instr->src[1]);
case nir_op_frexp_exp:
case nir_op_cube_face_index_amd:
case nir_op_cube_face_coord_amd:
- case nir_op_sad_u8x4: type = RegType::vgpr; break;
+ case nir_op_sad_u8x4:
+ case nir_op_iadd_sat: type = RegType::vgpr; break;
case nir_op_f2i16:
case nir_op_f2u16:
case nir_op_f2i32:
.lower_fpow = true,
.lower_mul_2x32_64 = true,
.lower_rotate = true,
+ .lower_iadd_sat = device->rad_info.chip_class <= GFX8,
.has_fsub = true,
.has_isub = true,
.use_scoped_barrier = true,