clk: g12a: add gen clock [1/1]

PD#OTT-1025

Problem:
not support gen clock

Solution:
add gen clock

Verify:
test passed on g12a u200

Change-Id: I5199289d3cd1483fffbbd41f8d104369214ba302
Signed-off-by: Jian Hu <jian.hu@amlogic.com>

diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c
index 9cf950f..1364835 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a.c
+++ b/drivers/amlogic/clk/g12a/g12a.c
@@ -560,6 +560,55 @@ static struct clk_gate g12a_12m_gate = {
        },
 };
 
+static u32 mux_table_gen_clk[] = { 0, 5, 6, 7, 20, 21, 22,
+                               23, 24, 25, 26, 27, 28, };
+static const char * const gen_clk_parent_names[] = {
+       "xtal", "gp0_pll", "gp1_pll", "hifi_pll", "fclk_div2", "fclk_div3",
+       "fclk_div4", "fclk_div5", "fclk_div7", "mpll0", "mpll1",
+       "mpll2", "mpll3"
+};
+
+static struct clk_mux g12a_gen_clk_sel = {
+       .reg = (void *)HHI_GEN_CLK_CNTL,
+       .mask = 0x1f,
+       .shift = 12,
+       .table = mux_table_gen_clk,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "gen_clk_sel",
+               .ops = &clk_mux_ops,
+               .parent_names = gen_clk_parent_names,
+               .num_parents = ARRAY_SIZE(gen_clk_parent_names),
+       },
+};
+
+static struct clk_divider g12a_gen_clk_div = {
+       .reg = (void *)HHI_GEN_CLK_CNTL,
+       .shift = 0,
+       .width = 11,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "gen_clk_div",
+               .ops = &clk_divider_ops,
+               .parent_names = (const char *[]){ "gen_clk_sel" },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
+static struct clk_gate g12a_gen_clk = {
+       .reg = (void *)HHI_GEN_CLK_CNTL,
+       .bit_idx = 11,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "gen_clk",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "gen_clk_div" },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
 
 /* Everything Else (EE) domain gates */
 static struct clk_gate g12a_spicc_0 = {
@@ -752,6 +801,10 @@ static struct clk_hw *g12a_clk_hws[] = {
        [CLKID_24M]             = &g12a_24m.hw,
        [CLKID_12M_DIV]         = &g12a_12m_div.hw,
        [CLKID_12M_GATE]        = &g12a_12m_gate.hw,
+       [CLKID_GEN_CLK_SEL]     = &g12a_gen_clk_sel.hw,
+       [CLKID_GEN_CLK_DIV]     = &g12a_gen_clk_div.hw,
+       [CLKID_GEN_CLK]         = &g12a_gen_clk.hw,
+
 };
 /* Convenience tables to populate base addresses in .probe */
 
@@ -838,6 +891,7 @@ static struct clk_gate *g12a_clk_gates[] = {
        &g12a_efuse,
        &g12a_24m,
        &g12a_12m_gate,
+       &g12a_gen_clk,
 };
 
 static void __init g12a_clkc_init(struct device_node *np)
@@ -892,7 +946,10 @@ static void __init g12a_clkc_init(struct device_node *np)
 
        g12a_12m_div.reg = clk_base
                                        + (unsigned long)g12a_12m_div.reg;
-
+       g12a_gen_clk_sel.reg = clk_base
+                                       + (unsigned long)g12a_gen_clk_sel.reg;
+       g12a_gen_clk_div.reg = clk_base
+                                       + (unsigned long)g12a_gen_clk_div.reg;
        /* Populate base address for gates */
        for (i = 0; i < ARRAY_SIZE(g12a_clk_gates); i++)
                g12a_clk_gates[i]->reg = clk_base +

diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h
index 6cf7109..8812a2d 100644 (file)
--- a/include/dt-bindings/clock/amlogic,g12a-clkc.h
+++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h
@@ -265,9 +265,13 @@
 #define CLKID_24M               (CLKID_MISC_BASE + 9)
 #define CLKID_12M_DIV           (CLKID_MISC_BASE + 10)
 #define CLKID_12M_GATE          (CLKID_MISC_BASE + 11)
+/* gen clock */
+#define CLKID_GEN_CLK_SEL      (CLKID_MISC_BASE + 12)
+#define        CLKID_GEN_CLK_DIV       (CLKID_MISC_BASE + 13)
+#define CLKID_GEN_CLK          (CLKID_MISC_BASE + 14)
 
 /*G12B clk*/
-#define CLKID_G12B_ADD_BASE           (CLKID_MISC_BASE + 12)
+#define CLKID_G12B_ADD_BASE           (CLKID_MISC_BASE + 15)
 #define CLKID_CPUB_FCLK_P             (CLKID_G12B_ADD_BASE + 0)
 #define CLKID_CPUB_CLK                (CLKID_G12B_ADD_BASE + 1)
 /*G12B gate*/