default:
++I;
continue;
- case Mips::SETGP2:
- // Convert "setgp2 $globalreg, $t9" to "addu $globalreg, $v0, $t9"
- BuildMI(MBB, I, I->getDebugLoc(), TII->get(Mips::ADDu),
- I->getOperand(0).getReg())
- .addReg(Mips::V0).addReg(I->getOperand(1).getReg());
- break;
case Mips::BuildPairF64:
ExpandBuildPairF64(MBB, I);
break;
def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
".cprestore\t$loc", []>;
-// For O32 ABI & PIC & non-fixed global base register, the following instruction
-// seqeunce is emitted to set the global base register:
-//
-// 0. lui $2, %hi(_gp_disp)
-// 1. addiu $2, $2, %lo(_gp_disp)
-// 2. addu $globalbasereg, $2, $t9
-//
-// SETGP01 is emitted during Prologue/Epilogue insertion and then converted to
-// instructions 0 and 1 in the sequence above during MC lowering.
-// SETGP2 is emitted just before register allocation and converted to
-// instruction 2 just prior to post-RA scheduling.
-//
-// These pseudo instructions are needed to ensure no instructions are inserted
-// before or between instructions 0 and 1, which is a limitation imposed by
-// GNU linker.
-
-let isTerminator = 1, isBarrier = 1 in
-def SETGP01 : MipsPseudo<(outs CPURegs:$dst), (ins), "", []>;
-
-let neverHasSideEffects = 1 in
-def SETGP2 : MipsPseudo<(outs CPURegs:$globalreg), (ins CPURegs:$picreg), "",
- []>;
-
let usesCustomInserter = 1 in {
defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;