PCI: microchip: Align register, offset, and mask names with HW docs

Minor code re-organisation so that macros representing registers ascend in
numerical order and use the same names as their hardware documentation.
Removed registers not used by the driver.

Link: https://lore.kernel.org/r/20230728131401.1615724-4-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 5c89caa..30153fd 100644 (file)
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -30,66 +30,7 @@
 #define MC_PCIE_BRIDGE_ADDR                    (MC_PCIE1_BRIDGE_ADDR)
 #define MC_PCIE_CTRL_ADDR                      (MC_PCIE1_CTRL_ADDR)
 
-/* PCIe Controller Phy Regs */
-#define SEC_ERROR_CNT                          0x20
-#define DED_ERROR_CNT                          0x24
-#define SEC_ERROR_INT                          0x28
-#define  SEC_ERROR_INT_TX_RAM_SEC_ERR_INT      GENMASK(3, 0)
-#define  SEC_ERROR_INT_RX_RAM_SEC_ERR_INT      GENMASK(7, 4)
-#define  SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT        GENMASK(11, 8)
-#define  SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT        GENMASK(15, 12)
-#define  NUM_SEC_ERROR_INTS                    (4)
-#define SEC_ERROR_INT_MASK                     0x2c
-#define DED_ERROR_INT                          0x30
-#define  DED_ERROR_INT_TX_RAM_DED_ERR_INT      GENMASK(3, 0)
-#define  DED_ERROR_INT_RX_RAM_DED_ERR_INT      GENMASK(7, 4)
-#define  DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT        GENMASK(11, 8)
-#define  DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT        GENMASK(15, 12)
-#define  NUM_DED_ERROR_INTS                    (4)
-#define DED_ERROR_INT_MASK                     0x34
-#define ECC_CONTROL                            0x38
-#define  ECC_CONTROL_TX_RAM_INJ_ERROR_0                BIT(0)
-#define  ECC_CONTROL_TX_RAM_INJ_ERROR_1                BIT(1)
-#define  ECC_CONTROL_TX_RAM_INJ_ERROR_2                BIT(2)
-#define  ECC_CONTROL_TX_RAM_INJ_ERROR_3                BIT(3)
-#define  ECC_CONTROL_RX_RAM_INJ_ERROR_0                BIT(4)
-#define  ECC_CONTROL_RX_RAM_INJ_ERROR_1                BIT(5)
-#define  ECC_CONTROL_RX_RAM_INJ_ERROR_2                BIT(6)
-#define  ECC_CONTROL_RX_RAM_INJ_ERROR_3                BIT(7)
-#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0  BIT(8)
-#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1  BIT(9)
-#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2  BIT(10)
-#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3  BIT(11)
-#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0  BIT(12)
-#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1  BIT(13)
-#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2  BIT(14)
-#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3  BIT(15)
-#define  ECC_CONTROL_TX_RAM_ECC_BYPASS         BIT(24)
-#define  ECC_CONTROL_RX_RAM_ECC_BYPASS         BIT(25)
-#define  ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS   BIT(26)
-#define  ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS   BIT(27)
-#define LTSSM_STATE                            0x5c
-#define  LTSSM_L0_STATE                                0x10
-#define PCIE_EVENT_INT                         0x14c
-#define  PCIE_EVENT_INT_L2_EXIT_INT            BIT(0)
-#define  PCIE_EVENT_INT_HOTRST_EXIT_INT                BIT(1)
-#define  PCIE_EVENT_INT_DLUP_EXIT_INT          BIT(2)
-#define  PCIE_EVENT_INT_MASK                   GENMASK(2, 0)
-#define  PCIE_EVENT_INT_L2_EXIT_INT_MASK       BIT(16)
-#define  PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK   BIT(17)
-#define  PCIE_EVENT_INT_DLUP_EXIT_INT_MASK     BIT(18)
-#define  PCIE_EVENT_INT_ENB_MASK               GENMASK(18, 16)
-#define  PCIE_EVENT_INT_ENB_SHIFT              16
-#define  NUM_PCIE_EVENTS                       (3)
-
 /* PCIe Bridge Phy Regs */
-#define PCIE_PCI_IDS_DW1                       0x9c
-
-/* PCIe Config space MSI capability structure */
-#define MC_MSI_CAP_CTRL_OFFSET                 0xe0u
-#define  MC_MSI_MAX_Q_AVAIL                    (MC_NUM_MSI_IRQS_CODED << 1)
-#define  MC_MSI_Q_SIZE                         (MC_NUM_MSI_IRQS_CODED << 4)
-
 #define IMASK_LOCAL                            0x180
 #define  DMA_END_ENGINE_0_MASK                 0x00000000u
 #define  DMA_END_ENGINE_0_SHIFT                        0
@@ -137,7 +78,8 @@
 #define ISTATUS_LOCAL                          0x184
 #define IMASK_HOST                             0x188
 #define ISTATUS_HOST                           0x18c
-#define MSI_ADDR                               0x190
+#define IMSI_ADDR                              0x190
+#define  MSI_ADDR                              0x190
 #define ISTATUS_MSI                            0x194
 
 /* PCIe Master table init defines */
@@ -162,6 +104,62 @@
 
 #define ATR_ENTRY_SIZE                         32
 
+/* PCIe Controller Phy Regs */
+#define SEC_ERROR_EVENT_CNT                    0x20
+#define DED_ERROR_EVENT_CNT                    0x24
+#define SEC_ERROR_INT                          0x28
+#define  SEC_ERROR_INT_TX_RAM_SEC_ERR_INT      GENMASK(3, 0)
+#define  SEC_ERROR_INT_RX_RAM_SEC_ERR_INT      GENMASK(7, 4)
+#define  SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT        GENMASK(11, 8)
+#define  SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT        GENMASK(15, 12)
+#define  NUM_SEC_ERROR_INTS                    (4)
+#define SEC_ERROR_INT_MASK                     0x2c
+#define DED_ERROR_INT                          0x30
+#define  DED_ERROR_INT_TX_RAM_DED_ERR_INT      GENMASK(3, 0)
+#define  DED_ERROR_INT_RX_RAM_DED_ERR_INT      GENMASK(7, 4)
+#define  DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT        GENMASK(11, 8)
+#define  DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT        GENMASK(15, 12)
+#define  NUM_DED_ERROR_INTS                    (4)
+#define DED_ERROR_INT_MASK                     0x34
+#define ECC_CONTROL                            0x38
+#define  ECC_CONTROL_TX_RAM_INJ_ERROR_0                BIT(0)
+#define  ECC_CONTROL_TX_RAM_INJ_ERROR_1                BIT(1)
+#define  ECC_CONTROL_TX_RAM_INJ_ERROR_2                BIT(2)
+#define  ECC_CONTROL_TX_RAM_INJ_ERROR_3                BIT(3)
+#define  ECC_CONTROL_RX_RAM_INJ_ERROR_0                BIT(4)
+#define  ECC_CONTROL_RX_RAM_INJ_ERROR_1                BIT(5)
+#define  ECC_CONTROL_RX_RAM_INJ_ERROR_2                BIT(6)
+#define  ECC_CONTROL_RX_RAM_INJ_ERROR_3                BIT(7)
+#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0  BIT(8)
+#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1  BIT(9)
+#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2  BIT(10)
+#define  ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3  BIT(11)
+#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0  BIT(12)
+#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1  BIT(13)
+#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2  BIT(14)
+#define  ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3  BIT(15)
+#define  ECC_CONTROL_TX_RAM_ECC_BYPASS         BIT(24)
+#define  ECC_CONTROL_RX_RAM_ECC_BYPASS         BIT(25)
+#define  ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS   BIT(26)
+#define  ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS   BIT(27)
+#define PCIE_EVENT_INT                         0x14c
+#define  PCIE_EVENT_INT_L2_EXIT_INT            BIT(0)
+#define  PCIE_EVENT_INT_HOTRST_EXIT_INT                BIT(1)
+#define  PCIE_EVENT_INT_DLUP_EXIT_INT          BIT(2)
+#define  PCIE_EVENT_INT_MASK                   GENMASK(2, 0)
+#define  PCIE_EVENT_INT_L2_EXIT_INT_MASK       BIT(16)
+#define  PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK   BIT(17)
+#define  PCIE_EVENT_INT_DLUP_EXIT_INT_MASK     BIT(18)
+#define  PCIE_EVENT_INT_ENB_MASK               GENMASK(18, 16)
+#define  PCIE_EVENT_INT_ENB_SHIFT              16
+#define  NUM_PCIE_EVENTS                       (3)
+
+/* PCIe Config space MSI capability structure */
+#define MC_MSI_CAP_CTRL_OFFSET                 0xe0u
+#define  MC_MSI_MAX_Q_AVAIL                    (MC_NUM_MSI_IRQS_CODED << 1)
+#define  MC_MSI_Q_SIZE                         (MC_NUM_MSI_IRQS_CODED << 4)
+
+/* Events */
 #define EVENT_PCIE_L2_EXIT                     0
 #define EVENT_PCIE_HOTRST_EXIT                 1
 #define EVENT_PCIE_DLUP_EXIT                   2
@@ -1086,7 +1084,7 @@ static int mc_platform_init(struct pci_config_window *cfg)
              SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
        writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT);
        writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK);
-       writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT);
+       writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT);
 
        val = DED_ERROR_INT_TX_RAM_DED_ERR_INT |
              DED_ERROR_INT_RX_RAM_DED_ERR_INT |
@@ -1094,7 +1092,7 @@ static int mc_platform_init(struct pci_config_window *cfg)
              DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
        writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT);
        writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK);
-       writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT);
+       writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT);
 
        writel_relaxed(0, bridge_base_addr + IMASK_HOST);
        writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);