[AArch64] Fix incorrect mask when decoding b.cond instruction

The encoding of the b.cond instruction is described in the architecture
reference manual as:

b.cond  0101 0100 iiii iiii iiii iiii iii0 cccc

So the mask should be 0xff000010.

gdb/ChangeLog:

	* aarch64-tdep.c (decode_bcond): Fix incorrect mask.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 705b7eb..0942986 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2015-09-11  Pierre Langlois  <pierre.langlois@arm.com>
+
+       * aarch64-tdep.c (decode_bcond): Fix incorrect mask.
+
 2015-09-11  Mihail-Marian Nistor  <mihail.nistor@freescale.com>
 
        PR gdb/18947

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 9a44446..a4d8186 100644 (file)
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -339,7 +339,8 @@ decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
 static int
 decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
 {
-  if (decode_masked_match (insn, 0xfe000000, 0x54000000))
+  /* b.cond  0101 0100 iiii iiii iiii iiii iii0 cccc */
+  if (decode_masked_match (insn, 0xff000010, 0x54000000))
     {
       *cond = (insn >> 0) & 0xf;
       *offset = extract_signed_bitfield (insn, 19, 5) << 2;