+2002-02-25 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * config/tc-mips.c (set_at): Fix handling of 64bit register loads.
+ (macro): Likewise. Fix la/dla address expansions for EMBEDDED_PIC
+ and NO_PIC cases. Code cleanup.
+ (macro2): Fix handling of 64bit register loads.
+
2002-02-25 David Mosberger <davidm@hpl.hp.com>
* doc/as.texinfo: Add entry for IA64.
"t,r,j", AT, reg, (int) BFD_RELOC_LO16);
else
{
- load_register (counter, AT, &imm_expr, 0);
+ load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
unsignedp ? "sltu" : "slt",
"d,v,t", AT, reg, AT);
0);
return;
}
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
break;
macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
tempreg, (int) BFD_RELOC_PCREL_HI16_S);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
+ (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
"d,v,t", tempreg, tempreg, breg);
}
macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
"t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
if (! used_at)
return;
}
if (offset_expr.X_op == O_constant)
- load_register (&icnt, tempreg, &offset_expr, dbl);
+ load_register (&icnt, tempreg, &offset_expr,
+ ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
+ ? (dbl || HAVE_64BIT_ADDRESSES)
+ : HAVE_64BIT_ADDRESSES));
else if (mips_pic == NO_PIC)
{
/* If this is a reference to a GP relative symbol, we want
&& ! nopic_need_relax (offset_expr.X_add_symbol, 1))
{
frag_grow (20);
- macro_build ((char *) NULL, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
"t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16);
p = frag_var (rs_machine_dependent, 8, 0,
RELAX_ENCODE (4, 8, 0, 4, 0,
macro_build_lui (p, &icnt, &offset_expr, tempreg);
if (p != NULL)
p += 4;
- macro_build (p, &icnt, &offset_expr,
- HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
+ macro_build (p, &icnt, &offset_expr, "addiu",
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
}
}
frag_grow (32);
if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
- macro_build ((char *) NULL, &icnt, &offset_expr, dbl ? "ld" : "lw",
+ macro_build ((char *) NULL, &icnt, &offset_expr,
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, lw_reloc_type, GP);
if (expr1.X_add_number == 0)
{
HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
- dbl ? "ld" : "lw",
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, lw_reloc_type, tempreg);
if (expr1.X_add_number == 0)
{
p += 4;
}
macro_build (p, &icnt, &offset_expr,
- dbl ? "ld" : "lw",
+ HAVE_32BIT_ADDRESSES ? "lw" : "ld",
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
if (expr1.X_add_number >= -0x8000
abort ();
if (breg != 0)
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
- "d,v,t", treg, tempreg, breg);
+ {
+ char *s;
+
+ if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
+ s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
+ else
+ s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
+
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
+ "d,v,t", treg, tempreg, breg);
+ }
if (! used_at)
return;
}
else
{
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
"d,v,t", dreg, sreg, AT);
used_at = 1;
}
else
{
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
AT);
case M_SGTU_I:
s = "sltu";
sgti:
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
dreg, AT, sreg);
break;
case M_SLEU_I:
s = "sltu";
slei:
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
dreg, AT, sreg);
macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
dreg, sreg, (int) BFD_RELOC_LO16);
return;
}
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
dreg, sreg, AT);
break;
dreg, sreg, (int) BFD_RELOC_LO16);
return;
}
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
"d,v,t", dreg, sreg, AT);
break;
}
else
{
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
"d,v,t", dreg, sreg, AT);
used_at = 1;
case M_TNE_I:
s = "tne";
trap:
- load_register (&icnt, AT, &imm_expr, 0);
+ load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
AT);
break;
+2002-02-25 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-gp64-fp32-pic.d: Fix test of 64bit register loads.
+ * mips-gp64-fp32-pic.s: Likewise.
+ * mips-gp64-fp32.d: Likewise.
+ * mips-gp64-fp32.s: Likewise.
+ * mips-gp64-fp64-pic.d: Likewise.
+ * mips-gp64-fp64-pic.s: Likewise.
+ * mips-gp64-fp64.d: Likewise.
+ * mips-gp64-fp64.s: Likewise.
+
2002-02-25 Alan Modra <amodra@bigpond.net.au>
* gas/hppa/reloc/reloc.exp: Update copyright date.
30: 24840000 addiu a0,a0,0
34: 8f840000 lw a0,0\(gp\)
38: 00000000 nop
- 3c: 24840228 addiu a0,a0,552
- 40: 10000079 b 228 <[^>]*>
+ 3c: 24840230 addiu a0,a0,560
+ 40: 1000007b b 230 <[^>]*>
44: 00000000 nop
48: 8f990000 lw t9,0\(gp\)
4c: 00000000 nop
- 50: 27390228 addiu t9,t9,552
+ 50: 27390230 addiu t9,t9,560
54: 0320f809 jalr t9
58: 00000000 nop
5c: 8fbc0008 lw gp,8\(sp\)
7c: 8c840000 lw a0,0\(a0\)
80: 8f840000 lw a0,0\(gp\)
84: 00000000 nop
- 88: 24840228 addiu a0,a0,552
+ 88: 24840230 addiu a0,a0,560
8c: 8c840000 lw a0,0\(a0\)
90: 8f840000 lw a0,0\(gp\)
94: 00000000 nop
ac: dc840000 ld a0,0\(a0\)
b0: 8f840000 lw a0,0\(gp\)
b4: 00000000 nop
- b8: 24840228 addiu a0,a0,552
+ b8: 24840230 addiu a0,a0,560
bc: dc840000 ld a0,0\(a0\)
c0: 8f810000 lw at,0\(gp\)
c4: 00000000 nop
194: 64a40064 daddiu a0,a1,100
198: 0004202b sltu a0,zero,a0
19c: 00a0202d move a0,a1
- 1a0: df840000 ld a0,0\(gp\)
+ 1a0: 8f840000 lw a0,0\(gp\)
1a4: 00000000 nop
1a8: 24840000 addiu a0,a0,0
- 1ac: df840000 ld a0,0\(gp\)
+ 1ac: 8f840000 lw a0,0\(gp\)
1b0: 00000000 nop
1b4: 24840000 addiu a0,a0,0
1b8: 8f810000 lw at,0\(gp\)
1d4: 24210000 addiu at,at,0
1d8: b0240000 sdl a0,0\(at\)
1dc: b4240007 sdr a0,7\(at\)
- 1e0: 3c018000 lui at,0x8000
- 1e4: 0081082a slt at,a0,at
- 1e8: 1020000f beqz at,228 <[^>]*>
- 1ec: 00000000 nop
- 1f0: 34018000 li at,0x8000
- 1f4: 00010c78 dsll at,at,0x11
- 1f8: 0081082b sltu at,a0,at
- 1fc: 1020000a beqz at,228 <[^>]*>
- 200: 00000000 nop
- 204: 3c018000 lui at,0x8000
- 208: 0081082a slt at,a0,at
- 20c: 14200006 bnez at,228 <[^>]*>
- 210: 00000000 nop
- 214: 34018000 li at,0x8000
- 218: 00010c78 dsll at,at,0x11
- 21c: 0081082b sltu at,a0,at
- 220: 14200001 bnez at,228 <[^>]*>
- 224: 00000000 nop
+ 1e0: 34018000 li at,0x8000
+ 1e4: 00010c38 dsll at,at,0x10
+ 1e8: 0081082a slt at,a0,at
+ 1ec: 10200010 beqz at,230 <[^>]*>
+ 1f0: 00000000 nop
+ 1f4: 34018000 li at,0x8000
+ 1f8: 00010c78 dsll at,at,0x11
+ 1fc: 0081082b sltu at,a0,at
+ 200: 1020000b beqz at,230 <[^>]*>
+ 204: 00000000 nop
+ 208: 34018000 li at,0x8000
+ 20c: 00010c38 dsll at,at,0x10
+ 210: 0081082a slt at,a0,at
+ 214: 14200006 bnez at,230 <[^>]*>
+ 218: 00000000 nop
+ 21c: 34018000 li at,0x8000
+ 220: 00010c78 dsll at,at,0x11
+ 224: 0081082b sltu at,a0,at
+ 228: 14200001 bnez at,230 <[^>]*>
+ 22c: 00000000 nop
-0+0228 <[^>]*>:
+0+0230 <[^>]*>:
...
# 0198 sltu a0,zero,a0
move $4, $5 # 019c move a0,a1
- dla $4, shared # 01a0 ld a0,got(.sdata)(gp)
+ dla $4, shared # 01a0 lw a0,got(.sdata)(gp)
# 01a4 nop
# 01a8 addiu a0,a0,lo(shared)
- dla $4, unshared # 01ac ld a0,got(.data)(gp)
+ dla $4, unshared # 01ac lw a0,got(.data)(gp)
# 01b0 nop
# 01b4 addiu a0,a0,lo(unshared)
uld $4, unshared # 01b8 lw at,got(.data)(gp)
# 01d8 sdl a0,0(at)
# 01dc sdr a0,7(at)
- bgt $4, 0x7fffffff, end # 01e0 lui at,0x8000
- # 01e4 slt at,a0,at
- # 01e8 beqz at,end
- # 01ec nop
- bgtu $4, 0xffffffff, end # 01f0 li at,0x8000
- # 01f4 dsll at,at,17
- # 01f8 sltu at,a0,at
- # 01fc beqz at,end
- # 0200 nop
- ble $4, 0x7fffffff, end # 0204 lui at,0x8000
- # 0208 slt at,a0,at
- # 020c bnez at,end
- # 0210 nop
- bleu $4, 0xffffffff, end # 0214 li at,0x8000
- # 0218 dsll at,at,17
- # 021c sltu at,a0,at
- # 0220 bnez at,end
- # 0224 nop
+ bgt $4, 0x7fffffff, end # 01e0 li at,0x8000
+ # 01e4 dsll at,at,0x10
+ # 01e8 slt at,a0,at
+ # 01ec beqz at,end
+ # 01f0 nop
+ bgtu $4, 0xffffffff, end # 01f4 li at,0x8000
+ # 01f8 dsll at,at,17
+ # 01fc sltu at,a0,at
+ # 0200 beqz at,end
+ # 0204 nop
+ ble $4, 0x7fffffff, end # 0208 li at,0x8000
+ # 020c dsll at,at,0x10
+ # 0210 slt at,a0,at
+ # 0214 bnez at,end
+ # 0218 nop
+ bleu $4, 0xffffffff, end # 021c li at,0x8000
+ # 0220 dsll at,at,17
+ # 0224 sltu at,a0,at
+ # 0228 bnez at,end
+ # 022c nop
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
c: 3c040000 lui a0,0x0
10: 24840000 addiu a0,a0,0
14: 3c040000 lui a0,0x0
- 18: 24840154 addiu a0,a0,340
- 1c: 08000055 j 154 <[^>]*>
- 20: 0c000055 jal 154 <[^>]*>
+ 18: 2484015c addiu a0,a0,348
+ 1c: 08000057 j 15c <[^>]*>
+ 20: 0c000057 jal 15c <[^>]*>
24: 8f84c000 lw a0,-16384\(gp\)
28: 3c040000 lui a0,0x0
2c: 8c840000 lw a0,0\(a0\)
30: 3c040000 lui a0,0x0
- 34: 8c840154 lw a0,340\(a0\)
+ 34: 8c84015c lw a0,348\(a0\)
38: df84c000 ld a0,-16384\(gp\)
3c: 3c040000 lui a0,0x0
40: dc840000 ld a0,0\(a0\)
44: 3c040000 lui a0,0x0
- 48: dc840154 ld a0,340\(a0\)
+ 48: dc84015c ld a0,348\(a0\)
4c: af84c000 sw a0,-16384\(gp\)
50: 3c010000 lui at,0x0
54: ac240000 sw a0,0\(at\)
110: 24210000 addiu at,at,0
114: b0240000 sdl a0,0\(at\)
118: b4240007 sdr a0,7\(at\)
- 11c: 3c018000 lui at,0x8000
- 120: 0081082a slt at,a0,at
- 124: 1020000b beqz at,154 <[^>]*>
- 128: 34018000 li at,0x8000
- 12c: 00010c78 dsll at,at,0x11
- 130: 0081082b sltu at,a0,at
- 134: 10200007 beqz at,154 <[^>]*>
- 138: 3c018000 lui at,0x8000
- 13c: 0081082a slt at,a0,at
- 140: 14200004 bnez at,154 <[^>]*>
- 144: 34018000 li at,0x8000
- 148: 00010c78 dsll at,at,0x11
- 14c: 0081082b sltu at,a0,at
- 150: 14200000 bnez at,154 <[^>]*>
+ 11c: 34018000 li at,0x8000
+ 120: 00010c38 dsll at,at,0x10
+ 124: 0081082a slt at,a0,at
+ 128: 1020000c beqz at,15c <[^>]*>
+ 12c: 34018000 li at,0x8000
+ 130: 00010c78 dsll at,at,0x11
+ 134: 0081082b sltu at,a0,at
+ 138: 10200008 beqz at,15c <[^>]*>
+ 13c: 34018000 li at,0x8000
+ 140: 00010c38 dsll at,at,0x10
+ 144: 0081082a slt at,a0,at
+ 148: 14200004 bnez at,15c <[^>]*>
+ 14c: 34018000 li at,0x8000
+ 150: 00010c78 dsll at,at,0x11
+ 154: 0081082b sltu at,a0,at
+ 158: 14200000 bnez at,15c <[^>]*>
-0+0154 <[^>]*>:
+0+015c <[^>]*>:
...
# 0114 sdl a0,0(at)
# 0118 sdr a0,7(at)
- bgt $4, 0x7fffffff, end # 011c lui at,0x8000
- # 0120 slt at,a0,at
- # 0124 beqz at,end
- bgtu $4, 0xffffffff, end # 0128 li at,0x8000
- # 012c dsll at,at,17
- # 0130 sltu at,a0,at
- # 0134 beqz at,end
- ble $4, 0x7fffffff, end # 0138 lui at,0x8000
- # 013c slt at,a0,at
- # 0140 bnez at,end
- bleu $4, 0xffffffff, end # 0144 li at,0x8000
- # 0148 dsll at,at,17
- # 014c sltu at,a0,at
- # 0150 bnez at,end
+ bgt $4, 0x7fffffff, end # 011c li at,0x8000
+ # 0120 dsll at,at,0x10
+ # 0124 slt at,a0,at
+ # 0128 beqz at,end
+ bgtu $4, 0xffffffff, end # 012c li at,0x8000
+ # 0130 dsll at,at,17
+ # 0134 sltu at,a0,at
+ # 0138 beqz at,end
+ ble $4, 0x7fffffff, end # 013c li at,0x8000
+ # 0140 dsll at,at,0x10
+ # 0144 slt at,a0,at
+ # 0148 bnez at,end
+ bleu $4, 0xffffffff, end # 014c li at,0x8000
+ # 0150 dsll at,at,17
+ # 0154 sltu at,a0,at
+ # 0158 bnez at,end
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
30: 24840000 addiu a0,a0,0
34: 8f840000 lw a0,0\(gp\)
38: 00000000 nop
- 3c: 2484022c addiu a0,a0,556
- 40: 1000007a b 22c <[^>]*>
+ 3c: 24840234 addiu a0,a0,564
+ 40: 1000007c b 234 <[^>]*>
44: 00000000 nop
48: 8f990000 lw t9,0\(gp\)
4c: 00000000 nop
- 50: 2739022c addiu t9,t9,556
+ 50: 27390234 addiu t9,t9,564
54: 0320f809 jalr t9
58: 00000000 nop
5c: 8fbc0008 lw gp,8\(sp\)
7c: 8c840000 lw a0,0\(a0\)
80: 8f840000 lw a0,0\(gp\)
84: 00000000 nop
- 88: 2484022c addiu a0,a0,556
+ 88: 24840234 addiu a0,a0,564
8c: 8c840000 lw a0,0\(a0\)
90: 8f840000 lw a0,0\(gp\)
94: 00000000 nop
ac: dc840000 ld a0,0\(a0\)
b0: 8f840000 lw a0,0\(gp\)
b4: 00000000 nop
- b8: 2484022c addiu a0,a0,556
+ b8: 24840234 addiu a0,a0,564
bc: dc840000 ld a0,0\(a0\)
c0: 8f810000 lw at,0\(gp\)
c4: 00000000 nop
194: 64a40064 daddiu a0,a1,100
198: 0004202b sltu a0,zero,a0
19c: 00a0202d move a0,a1
- 1a0: df840000 ld a0,0\(gp\)
+ 1a0: 8f840000 lw a0,0\(gp\)
1a4: 00000000 nop
1a8: 24840000 addiu a0,a0,0
- 1ac: df840000 ld a0,0\(gp\)
+ 1ac: 8f840000 lw a0,0\(gp\)
1b0: 00000000 nop
1b4: 24840000 addiu a0,a0,0
1b8: 8f810000 lw at,0\(gp\)
1d4: 24210000 addiu at,at,0
1d8: b0240000 sdl a0,0\(at\)
1dc: b4240007 sdr a0,7\(at\)
- 1e0: 3c018000 lui at,0x8000
- 1e4: 0081082a slt at,a0,at
- 1e8: 10200010 beqz at,22c <[^>]*>
- 1ec: 00000000 nop
- 1f0: 34018000 li at,0x8000
- 1f4: 00010c78 dsll at,at,0x11
- 1f8: 0081082b sltu at,a0,at
- 1fc: 1020000b beqz at,22c <[^>]*>
- 200: 00000000 nop
- 204: 3c018000 lui at,0x8000
- 208: 0081082a slt at,a0,at
- 20c: 14200007 bnez at,22c <[^>]*>
- 210: 00000000 nop
- 214: 34018000 li at,0x8000
- 218: 00010c78 dsll at,at,0x11
- 21c: 0081082b sltu at,a0,at
- 220: 14200002 bnez at,22c <[^>]*>
- 224: 00000000 nop
- 228: 46231040 add.d \$f1,\$f2,\$f3
+ 1e0: 34018000 li at,0x8000
+ 1e4: 00010c38 dsll at,at,0x10
+ 1e8: 0081082a slt at,a0,at
+ 1ec: 10200011 beqz at,234 <[^>]*>
+ 1f0: 00000000 nop
+ 1f4: 34018000 li at,0x8000
+ 1f8: 00010c78 dsll at,at,0x11
+ 1fc: 0081082b sltu at,a0,at
+ 200: 1020000c beqz at,234 <[^>]*>
+ 204: 00000000 nop
+ 208: 34018000 li at,0x8000
+ 20c: 00010c38 dsll at,at,0x10
+ 210: 0081082a slt at,a0,at
+ 214: 14200007 bnez at,234 <[^>]*>
+ 218: 00000000 nop
+ 21c: 34018000 li at,0x8000
+ 220: 00010c78 dsll at,at,0x11
+ 224: 0081082b sltu at,a0,at
+ 228: 14200002 bnez at,234 <[^>]*>
+ 22c: 00000000 nop
+ 230: 46231040 add.d \$f1,\$f2,\$f3
-0+022c <[^>]*>:
+0+0234 <[^>]*>:
...
# 0198 sltu a0,zero,a0
move $4, $5 # 019c move a0,a1
- dla $4, shared # 01a0 ld a0,got(.sdata)(gp)
+ dla $4, shared # 01a0 lw a0,got(.sdata)(gp)
# 01a4 nop
# 01a8 addiu a0,a0,lo(shared)
- dla $4, unshared # 01ac ld a0,got(.data)(gp)
+ dla $4, unshared # 01ac lw a0,got(.data)(gp)
# 01b0 nop
# 01b4 addiu a0,a0,lo(unshared)
uld $4, unshared # 01b8 lw at,got(.data)(gp)
# 01d8 sdl a0,0(at)
# 01dc sdr a0,7(at)
- bgt $4, 0x7fffffff, end # 01e0 lui at,0x8000
- # 01e4 slt at,a0,at
- # 01e8 beqz at,end
- # 01ec nop
- bgtu $4, 0xffffffff, end # 01f0 li at,0x8000
- # 01f4 dsll at,at,17
- # 01f8 sltu at,a0,at
- # 01fc beqz at,end
- # 0200 nop
- ble $4, 0x7fffffff, end # 0204 lui at,0x8000
- # 0208 slt at,a0,at
- # 020c bnez at,end
- # 0210 nop
- bleu $4, 0xffffffff, end # 0214 li at,0x8000
- # 0218 dsll at,at,17
- # 021c sltu at,a0,at
- # 0220 bnez at,end
- # 0224 nop
+ bgt $4, 0x7fffffff, end # 01e0 li at,0x8000
+ # 01e4 dsll at,at,0x10
+ # 01e8 slt at,a0,at
+ # 01ec beqz at,end
+ # 01f0 nop
+ bgtu $4, 0xffffffff, end # 01f4 li at,0x8000
+ # 01f8 dsll at,at,17
+ # 01fc sltu at,a0,at
+ # 0200 beqz at,end
+ # 0204 nop
+ ble $4, 0x7fffffff, end # 0208 li at,0x8000
+ # 020c dsll at,at,0x10
+ # 0210 slt at,a0,at
+ # 0214 bnez at,end
+ # 0218 nop
+ bleu $4, 0xffffffff, end # 021c li at,0x8000
+ # 0220 dsll at,at,17
+ # 0224 sltu at,a0,at
+ # 0228 bnez at,end
+ # 022c nop
- add.d $f1, $f2, $f3 # 0228 add.d $f1,$f2,$f3
+ add.d $f1, $f2, $f3 # 0230 add.d $f1,$f2,$f3
.end func
end:
c: 3c040000 lui a0,0x0
10: 24840000 addiu a0,a0,0
14: 3c040000 lui a0,0x0
- 18: 24840158 addiu a0,a0,344
- 1c: 08000056 j 158 <[^>]*>
- 20: 0c000056 jal 158 <[^>]*>
+ 18: 24840160 addiu a0,a0,352
+ 1c: 08000058 j 160 <[^>]*>
+ 20: 0c000058 jal 160 <[^>]*>
24: 8f84c000 lw a0,-16384\(gp\)
28: 3c040000 lui a0,0x0
2c: 8c840000 lw a0,0\(a0\)
30: 3c040000 lui a0,0x0
- 34: 8c840158 lw a0,344\(a0\)
+ 34: 8c840160 lw a0,352\(a0\)
38: df84c000 ld a0,-16384\(gp\)
3c: 3c040000 lui a0,0x0
40: dc840000 ld a0,0\(a0\)
44: 3c040000 lui a0,0x0
- 48: dc840158 ld a0,344\(a0\)
+ 48: dc840160 ld a0,352\(a0\)
4c: af84c000 sw a0,-16384\(gp\)
50: 3c010000 lui at,0x0
54: ac240000 sw a0,0\(at\)
110: 24210000 addiu at,at,0
114: b0240000 sdl a0,0\(at\)
118: b4240007 sdr a0,7\(at\)
- 11c: 3c018000 lui at,0x8000
- 120: 0081082a slt at,a0,at
- 124: 1020000c beqz at,158 <[^>]*>
- 128: 34018000 li at,0x8000
- 12c: 00010c78 dsll at,at,0x11
- 130: 0081082b sltu at,a0,at
- 134: 10200008 beqz at,158 <[^>]*>
- 138: 3c018000 lui at,0x8000
- 13c: 0081082a slt at,a0,at
- 140: 14200005 bnez at,158 <[^>]*>
- 144: 34018000 li at,0x8000
- 148: 00010c78 dsll at,at,0x11
- 14c: 0081082b sltu at,a0,at
- 150: 14200001 bnez at,158 <[^>]*>
- 154: 46231040 add.d \$f1,\$f2,\$f3
+ 11c: 34018000 li at,0x8000
+ 120: 00010c38 dsll at,at,0x10
+ 124: 0081082a slt at,a0,at
+ 128: 1020000d beqz at,160 <[^>]*>
+ 12c: 34018000 li at,0x8000
+ 130: 00010c78 dsll at,at,0x11
+ 134: 0081082b sltu at,a0,at
+ 138: 10200009 beqz at,160 <[^>]*>
+ 13c: 34018000 li at,0x8000
+ 140: 00010c38 dsll at,at,0x10
+ 144: 0081082a slt at,a0,at
+ 148: 14200005 bnez at,160 <[^>]*>
+ 14c: 34018000 li at,0x8000
+ 150: 00010c78 dsll at,at,0x11
+ 154: 0081082b sltu at,a0,at
+ 158: 14200001 bnez at,160 <[^>]*>
+ 15c: 46231040 add.d \$f1,\$f2,\$f3
-0+0158 <[^>]*>:
+0+0160 <[^>]*>:
...
# 0114 sdl a0,0(at)
# 0118 sdr a0,7(at)
- bgt $4, 0x7fffffff, end # 011c lui at,0x8000
- # 0120 slt at,a0,at
- # 0124 beqz at,end
- bgtu $4, 0xffffffff, end # 0128 li at,0x8000
- # 012c dsll at,at,17
- # 0130 sltu at,a0,at
- # 0134 beqz at,end
- ble $4, 0x7fffffff, end # 0138 lui at,0x8000
- # 013c slt at,a0,at
- # 0140 bnez at,end
- bleu $4, 0xffffffff, end # 0144 li at,0x8000
- # 0148 dsll at,at,17
- # 014c sltu at,a0,at
- # 0150 bnez at,end
+ bgt $4, 0x7fffffff, end # 011c li at,0x8000
+ # 0120 dsll at,at,0x10
+ # 0124 slt at,a0,at
+ # 0128 beqz at,end
+ bgtu $4, 0xffffffff, end # 012c li at,0x8000
+ # 0130 dsll at,at,17
+ # 0134 sltu at,a0,at
+ # 0138 beqz at,end
+ ble $4, 0x7fffffff, end # 013c li at,0x8000
+ # 0140 dsll at,at,0x10
+ # 0144 slt at,a0,at
+ # 0148 bnez at,end
+ bleu $4, 0xffffffff, end # 014c li at,0x8000
+ # 0150 dsll at,at,17
+ # 0154 sltu at,a0,at
+ # 0158 bnez at,end
- add.d $f1, $f2, $f3 # 0154 add.d $f1,$f2,$f3
+ add.d $f1, $f2, $f3 # 015c add.d $f1,$f2,$f3
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
projects / external / binutils.git / commitdiff