F: drivers/amlogic/media/vout/hdmitx/*
F: drivers/amlogic/media/vout/hdmitx/hdcp/*
F: include/linux/amlogic/media/vout/hdmi_tx/*
+F: drivers/amlogic/esm/*
AMLOGIC DWC_OTG USB
M: Yue Wang <yue.wang@amlogic.com>
source "drivers/amlogic/watchdog/Kconfig"
+source "drivers/amlogic/esm/Kconfig"
+
source "drivers/amlogic/wifi/Kconfig"
source "drivers/amlogic/bluetooth/Kconfig"
obj-$(CONFIG_AMLOGIC_WDT) += watchdog/
+obj-$(CONFIG_AMLOGIC_ESM) += esm/
+
obj-$(CONFIG_AMLOGIC_BT_DEVICE) += bluetooth/
obj-$(CONFIG_AMLOGIC_WIFI) += wifi/
--- /dev/null
+menu "ESM Support"
+
+if AMLOGIC_HDMITX || TVIN_HDMI
+config AMLOGIC_ESM
+ bool "Embedded Security Module Enable"
+ default y
+ help
+ Embedded Security Module(ESM) for HDCP22
+endif
+
+endmenu
--- /dev/null
+// ------------------------------------------------------------------------
+//
+// (C) COPYRIGHT 2014 - 2015 SYNOPSYS, INC.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2
+// as published by the Free Software Foundation.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+// ------------------------------------------------------------------------
+//
+// Project:
+//
+// ESM Host Library
+//
+// Description:
+//
+// ESM Host Library Driver: Linux kernel module
+//
+// ------------------------------------------------------------------------
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/random.h>
+#include <linux/miscdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+
+#include "host_lib_driver_linux_if.h"
+
+#define ELP_DEBUG() pr_info("%s[%d]\n", __func__, __LINE__)
+
+#define MAX_ESM_DEVICES 6
+
+static int verbose;
+
+static bool randomize_mem;
+module_param(randomize_mem, bool, 0644);
+MODULE_PARM_DESC(noverify, "Wipe memory allocations on startup (for debug)");
+
+struct esm_device {
+ int allocated, initialized;
+ int code_loaded;
+
+ int code_is_phys_mem;
+ dma_addr_t code_base;
+ uint32_t code_size;
+ uint8_t *code;
+
+ int data_is_phys_mem;
+ dma_addr_t data_base;
+ uint32_t data_size;
+ uint8_t *data;
+
+ struct resource *hpi_resource;
+ uint8_t __iomem *hpi;
+};
+
+static struct esm_device esm_devices[MAX_ESM_DEVICES];
+
+/* ESM_IOC_MEMINFO implementation */
+static long get_meminfo(struct esm_device *esm, void __user *arg)
+{
+ struct esm_ioc_meminfo info = {
+ .hpi_base = esm->hpi_resource->start,
+ .code_base = esm->code_base,
+ .code_size = esm->code_size,
+ .data_base = esm->data_base,
+ .data_size = esm->data_size,
+ };
+
+ if (copy_to_user(arg, &info, sizeof(info)) != 0)
+ return -EFAULT;
+
+ return 0;
+}
+
+/* ESM_IOC_LOAD_CODE implementation */
+static long load_code(struct esm_device *esm, struct esm_ioc_code __user *arg)
+{
+ struct esm_ioc_code head;
+
+ if (copy_from_user(&head, arg, sizeof(head)) != 0)
+ return -EFAULT;
+
+ if (head.len > esm->code_size)
+ return -ENOSPC;
+
+ if (esm->code_loaded)
+ return 0; /* return -EBUSY; */
+
+ if (copy_from_user(esm->code, &arg->data, head.len) != 0)
+ return -EFAULT;
+
+ esm->code_loaded = 1;
+ return 0;
+}
+
+/* ESM_IOC_WRITE_DATA implementation */
+static long write_data(struct esm_device *esm, struct esm_ioc_data __user *arg)
+{
+ struct esm_ioc_data head;
+
+ if (copy_from_user(&head, arg, sizeof(head)) != 0)
+ return -EFAULT;
+
+ if (esm->data_size < head.len)
+ return -ENOSPC;
+ if (esm->data_size - head.len < head.offset)
+ return -ENOSPC;
+
+ if (copy_from_user(esm->data + head.offset, &arg->data, head.len) != 0)
+ return -EFAULT;
+
+ return 0;
+}
+
+/* ESM_IOC_READ_DATA implementation */
+static long read_data(struct esm_device *esm, struct esm_ioc_data __user *arg)
+{
+ struct esm_ioc_data head;
+
+ if (copy_from_user(&head, arg, sizeof(head)) != 0)
+ return -EFAULT;
+
+ if (esm->data_size < head.len)
+ return -ENOSPC;
+ if (esm->data_size - head.len < head.offset)
+ return -ENOSPC;
+
+ if (copy_to_user(&arg->data, esm->data + head.offset, head.len) != 0)
+ return -EFAULT;
+
+ return 0;
+}
+
+/* ESM_IOC_MEMSET_DATA implementation */
+static long set_data(struct esm_device *esm, void __user *arg)
+{
+ union {
+ struct esm_ioc_data data;
+ unsigned char buf[sizeof(struct esm_ioc_data) + 1];
+ } u;
+
+ if (copy_from_user(&u.data, arg, sizeof(u.buf)) != 0)
+ return -EFAULT;
+
+ if (esm->data_size < u.data.len)
+ return -ENOSPC;
+ if (esm->data_size - u.data.len < u.data.offset)
+ return -ENOSPC;
+
+ memset(esm->data + u.data.offset, u.data.data[0], u.data.len);
+ return 0;
+}
+
+/* ESM_IOC_READ_HPI implementation */
+static long hpi_read(struct esm_device *esm, void __user *arg)
+{
+ struct esm_ioc_hpi_reg reg;
+
+ if (copy_from_user(®, arg, sizeof(reg)) != 0)
+ return -EFAULT;
+
+ if ((reg.offset & 3) || reg.offset >= resource_size(esm->hpi_resource))
+ return -EINVAL;
+
+ reg.value = ioread32(esm->hpi + reg.offset);
+ if (verbose)
+ pr_info("R reg.value = 0x%x, reg.offset = 0x%x\n",
+ reg.value, reg.offset);
+ if (copy_to_user(arg, ®, sizeof(reg)) != 0)
+ return -EFAULT;
+
+ return 0;
+}
+
+/* ESM_IOC_WRITE_HPI implementation */
+static long hpi_write(struct esm_device *esm, void __user *arg)
+{
+ struct esm_ioc_hpi_reg reg;
+
+ if (copy_from_user(®, arg, sizeof(reg)) != 0)
+ return -EFAULT;
+
+ if ((reg.offset & 3) || reg.offset >= resource_size(esm->hpi_resource))
+ return -EINVAL;
+ if (verbose)
+ pr_info("W reg.value = 0x%x, reg.offset = 0x%x\n",
+ reg.value, reg.offset);
+ iowrite32(reg.value, esm->hpi + reg.offset);
+ return 0;
+}
+
+static struct esm_device *alloc_esm_slot(const struct esm_ioc_meminfo *info)
+{
+ int i;
+
+ /* Check if we have a matching device (same HPI base) */
+ for (i = 0; i < MAX_ESM_DEVICES; i++) {
+ struct esm_device *slot = &esm_devices[i];
+
+ if (slot->allocated &&
+ info->hpi_base == slot->hpi_resource->start)
+ return slot;
+ }
+
+ /* Find unused slot */
+ for (i = 0; i < MAX_ESM_DEVICES; i++) {
+ struct esm_device *slot = &esm_devices[i];
+
+ if (!slot->allocated) {
+ slot->allocated = 1;
+ return slot;
+ }
+ }
+
+ return NULL;
+}
+
+static void free_dma_areas(struct esm_device *esm)
+{
+ if (!esm->code_is_phys_mem && esm->code) {
+ dma_free_coherent(NULL, esm->code_size, esm->code,
+ esm->code_base);
+ esm->code = NULL;
+ }
+
+ if (!esm->data_is_phys_mem && esm->data) {
+ dma_free_coherent(NULL, esm->data_size, esm->data,
+ esm->data_base);
+ esm->data = NULL;
+ }
+}
+
+static int alloc_dma_areas(struct esm_device *esm,
+ const struct esm_ioc_meminfo *info)
+{
+ esm->code_size = info->code_size;
+ esm->code_is_phys_mem = (info->code_base != 0);
+
+ if (esm->code_is_phys_mem) {
+ /* TODO: support highmem */
+ esm->code_base = info->code_base;
+ esm->code = phys_to_virt(esm->code_base);
+ } else {
+ esm->code = dma_alloc_coherent((struct device *)esm,
+ esm->code_size, &esm->code_base, GFP_KERNEL);
+ if (!esm->code)
+ return -ENOMEM;
+ }
+
+ esm->data_size = info->data_size;
+ esm->data_is_phys_mem = (info->data_base != 0);
+
+ if (esm->data_is_phys_mem) {
+ esm->data_base = info->data_base;
+ esm->data = phys_to_virt(esm->data_base);
+ } else {
+ esm->data = dma_alloc_coherent((struct device *)esm,
+ esm->data_size, &esm->data_base, GFP_KERNEL);
+ if (!esm->data) {
+ free_dma_areas(esm);
+ return -ENOMEM;
+ }
+ }
+
+ if (randomize_mem) {
+ prandom_bytes(esm->code, esm->code_size);
+ prandom_bytes(esm->data, esm->data_size);
+ }
+
+ return 0;
+}
+
+/* ESM_IOC_INIT implementation */
+static long init(struct file *f, void __user *arg)
+{
+ struct resource *hpi_mem;
+ struct esm_ioc_meminfo info;
+ struct esm_device *esm;
+ int rc;
+
+ if (copy_from_user(&info, arg, sizeof(info)) != 0)
+ return -EFAULT;
+
+ esm = alloc_esm_slot(&info);
+ if (!esm)
+ return -EMFILE;
+
+ if (!esm->initialized) {
+ rc = alloc_dma_areas(esm, &info);
+ if (rc < 0)
+ goto err_free;
+ pr_info("info.hpi_base = 0x%x\n", info.hpi_base);
+ hpi_mem = request_mem_region(info.hpi_base, 128, "esm-hpi");
+ if (!hpi_mem) {
+ rc = -EADDRNOTAVAIL;
+ goto err_free;
+ }
+
+ esm->hpi = ioremap_nocache(hpi_mem->start,
+ resource_size(hpi_mem));
+ if (!esm->hpi) {
+ rc = -ENOMEM;
+ goto err_release_region;
+ }
+ esm->hpi_resource = hpi_mem;
+ esm->initialized = 1;
+ }
+
+ f->private_data = esm;
+ return 0;
+
+err_release_region:
+ release_resource(hpi_mem);
+err_free:
+ free_dma_areas(esm);
+ esm->initialized = 0;
+ esm->allocated = 0;
+
+ return rc;
+}
+
+static void free_esm_slot(struct esm_device *slot)
+{
+ if (!slot->allocated)
+ return;
+
+ if (slot->initialized) {
+ iounmap(slot->hpi);
+ release_resource(slot->hpi_resource);
+ free_dma_areas(slot);
+ }
+
+ slot->initialized = 0;
+ slot->allocated = 0;
+}
+
+static long hld_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
+{
+ struct esm_device *esm = f->private_data;
+ void __user *data = (void __user *)arg;
+
+ if (cmd == ESM_IOC_INIT)
+ return init(f, data);
+ else if (!esm)
+ return -EAGAIN;
+
+ switch (cmd) {
+ case ESM_IOC_INIT:
+ return init(f, data);
+ case ESM_IOC_MEMINFO:
+ return get_meminfo(esm, data);
+ case ESM_IOC_READ_HPI:
+ return hpi_read(esm, data);
+ case ESM_IOC_WRITE_HPI:
+ return hpi_write(esm, data);
+ case ESM_IOC_LOAD_CODE:
+ return load_code(esm, data);
+ case ESM_IOC_WRITE_DATA:
+ return write_data(esm, data);
+ case ESM_IOC_READ_DATA:
+ return read_data(esm, data);
+ case ESM_IOC_MEMSET_DATA:
+ return set_data(esm, data);
+ default:
+ break;
+ }
+
+ return -ENOTTY;
+}
+
+static const struct file_operations hld_file_operations = {
+ .compat_ioctl = hld_ioctl,
+ .owner = THIS_MODULE,
+};
+
+static struct miscdevice hld_device = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = "esm",
+ .fops = &hld_file_operations,
+};
+
+static int __init hld_init(void)
+{
+ return misc_register(&hld_device);
+}
+module_init(hld_init);
+
+static void __exit hld_exit(void)
+{
+ int i;
+
+ misc_deregister(&hld_device);
+
+ for (i = 0; i < MAX_ESM_DEVICES; i++)
+ free_esm_slot(&esm_devices[i]);
+}
+module_exit(hld_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Synopsys, Inc.");
+MODULE_DESCRIPTION("ESM Linux Host Library Driver");
+
+module_param(verbose, int, 0644);
+MODULE_PARM_DESC(verbose, "Enable (1) or disable (0) the debug traces.");
--- /dev/null
+//-----------------------------------------------------------------------
+//
+// (C) COPYRIGHT 2014 - 2015 SYNOPSYS, INC.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2
+// as published by the Free Software Foundation.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+//
+// ------------------------------------------------------------------------
+//
+// Project:
+//
+// ESM Host Library
+//
+// Description:
+//
+// ESM Host Library Driver: Interface to the Linux kernel driver.
+//
+// ------------------------------------------------------------------------
+
+#ifndef ESM_HLD_LINUX_IOCTL_H_
+#define ESM_HLD_LINUX_IOCTL_H_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+/* ioctl numbers */
+enum {
+ ESM_NR_MIN = 0x10,
+ ESM_NR_INIT,
+ ESM_NR_MEMINFO,
+ ESM_NR_LOAD_CODE,
+ ESM_NR_READ_DATA,
+ ESM_NR_WRITE_DATA,
+ ESM_NR_MEMSET_DATA,
+ ESM_NR_READ_HPI,
+ ESM_NR_WRITE_HPI,
+ ESM_NR_MAX
+};
+
+/*
+ * ESM_IOC_INIT: associate file descriptor with the indicated memory. This
+ * must be called before any other ioctl on the file descriptor.
+ *
+ * - hpi_base = base address of ESM HPI registers.
+ * - code_base = base address of firmware memory (0 to allocate internally)
+ * - data_base = base address of data memory (0 to allocate internally)
+ * - code_len, data_len = length of firmware and data memory, respectively.
+ */
+#define ESM_IOC_INIT _IOW('H', ESM_NR_INIT, struct esm_ioc_meminfo)
+
+/*
+ * ESM_IOC_MEMINFO: retrieve memory information from file descriptor.
+ *
+ * Fills out the meminfo struct, returning the values passed to ESM_IOC_INIT
+ * except that the actual base addresses of internal allocations (if any) are
+ * reported.
+ */
+#define ESM_IOC_MEMINFO _IOR('H', ESM_NR_MEMINFO, struct esm_ioc_meminfo)
+
+struct esm_ioc_meminfo {
+ __u32 hpi_base;
+ __u32 code_base;
+ __u32 code_size;
+ __u32 data_base;
+ __u32 data_size;
+};
+
+/*
+ * ESM_IOC_LOAD_CODE: write the provided buffer to the firmware memory.
+ *
+ * - len = number of bytes in data buffer
+ * - data = data to write to firmware memory.
+ *
+ * This can only be done once (successfully). Subsequent attempts will
+ * return -EBUSY.
+ */
+#define ESM_IOC_LOAD_CODE _IOW('H', ESM_NR_LOAD_CODE, struct esm_ioc_code)
+
+struct esm_ioc_code {
+ __u32 len;
+ __u8 data[];
+};
+
+/*
+ * ESM_IOC_READ_DATA: copy from data memory.
+ * ESM_IOC_WRITE_DATA: copy to data memory.
+ *
+ * - offset = start copying at this byte offset into the data memory.
+ * - len = number of bytes to copy.
+ * - data = for write, buffer containing data to copy.
+ * for read, buffer to which read data will be written.
+ *
+ */
+#define ESM_IOC_READ_DATA _IOWR('H', ESM_NR_READ_DATA, struct esm_ioc_data)
+#define ESM_IOC_WRITE_DATA _IOW('H', ESM_NR_WRITE_DATA, struct esm_ioc_data)
+
+/*
+ * ESM_IOC_MEMSET_DATA: initialize data memory.
+ *
+ * - offset = start initializatoin at this byte offset into the data memory.
+ * - len = number of bytes to set.
+ * - data[0] = byte value to write to all indicated memory locations.
+ */
+#define ESM_IOC_MEMSET_DATA _IOW('H', ESM_NR_MEMSET_DATA, struct esm_ioc_data)
+
+struct esm_ioc_data {
+ __u32 offset;
+ __u32 len;
+ __u8 data[];
+};
+
+/*
+ * ESM_IOC_READ_HPI: read HPI register.
+ * ESM_IOC_WRITE_HPI: write HPI register.
+ *
+ * - offset = byte offset of HPI register to access.
+ * - value = for write, value to write.
+ * for read, location to which result is stored.
+ */
+#define ESM_IOC_READ_HPI _IOWR('H', ESM_NR_READ_HPI, struct esm_ioc_hpi_reg)
+#define ESM_IOC_WRITE_HPI _IOW('H', ESM_NR_WRITE_HPI, struct esm_ioc_hpi_reg)
+
+struct esm_ioc_hpi_reg {
+ __u32 offset;
+ __u32 value;
+};
+
+#endif
if (!t)
return NULL;
for (i = 0; all_fmt_paras[i]; i++) {
- /*
- * struct hdmi_format_para.timing.pixel_freq must divide 10
- * to match with t->pixel_clock
- */
- if ((t->pixel_clock == all_fmt_paras[i]->timing.pixel_freq / 10)
- && (t->h_active == all_fmt_paras[i]->timing.h_active) &&
+ if ((abs(all_fmt_paras[i]->timing.frac_freq / 10
+ - t->pixel_clock) <= (t->pixel_clock + 1000) / 1000) &&
+ (t->h_active == all_fmt_paras[i]->timing.h_active) &&
(t->h_blank == all_fmt_paras[i]->timing.h_blank) &&
(t->v_active == all_fmt_paras[i]->timing.v_active) &&
(t->v_blank == all_fmt_paras[i]->timing.v_blank) &&
hdmitx20-objs := hdmi_tx_main.o hdmi_tx_video.o hdmi_tx_audio.o hdmi_tx_edid.o \
hdmi_tx_audio.o hdmi_tx_hdcp.o hdmi_tx_scdc.o \
-obj-$(CONFIG_AMLOGIC_HDMITX) += hw/ hdcp22/
+obj-$(CONFIG_AMLOGIC_HDMITX) += hw/
#EXTRA_CFLAGS += -O2
+++ /dev/null
-/*
- * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/ESMHostLibDriverErrors.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _ESMDRIVERERROR_H_
-#define _ESMDRIVERERROR_H_
-
-/**
- * \defgroup HostLibErrors General Library Errors
- *
- * The following are error code definitions produced
- * by the API library.
- *
- * \addtogroup HostLibErrors
- * @{
- *
- */
-
-#define ESM_HL_DRIVER_SUCCESS 0
-#define ESM_HL_DRIVER_FAILED (-1)
-#define ESM_HL_DRIVER_NO_MEMORY (-2)
-#define ESM_HL_DRIVER_NO_ACCESS (-3)
-#define ESM_HL_DRIVER_INVALID_PARAM (-4)
-#define ESM_HL_DRIVER_TOO_MANY_ESM_DEVICES (-5)
-#define ESM_HL_DRIVER_USER_DEFINED_ERROR (-6)
-/* anything beyond this error code is user defined */
-
-/* End of APIErrors group */
-/**
- * @}
- */
-/**
- * @}
- */
-
-#endif
+++ /dev/null
-/*
- * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/ESMHostTypes.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _ESMHOSTTYPES_H_
-#define _ESMHOSTTYPES_H_
-
-#include "elliptic_std_def.h"
-#include "elliptic_system_types.h"
-
-/* return type for all functions */
-#define ESM_STATUS ELP_STATUS
-
-/**
- * \defgroup InitFlags Initialization Flags
- *
- * Options which can be set when calling ESM_Initialize().
- *
- * \addtogroup InitFlags
- * @{
- */
-#define ESM_INIT_FLAG_IRQ_SUPPORTED (1ul << 0)
-/**
- * @}
- */
-
-/**
- * \defgroup LogTypes Log message types
- *
- * These are the defined log message types.
- *
- * \addtogroup LogTypes
- * @{
- */
-#define ESM_LOG_TYPE_TEXT 0xfd /* Normal text log message. */
-#define ESM_LOG_TYPE_BINARY 0xfc /* Binary dump message. */
-/**
- * @}
- */
-
-/**
- * \details
- *
- * This structure contains the ESM's last internal status when queried.
- *
- */
-struct esm_status_t {
- /**
- * The ESM Exception vector has the following bitfields:
- *
- * <table>
- * <tr align="center">
- * <td><b>HW/SW</b></td>
- * <td><b>Exception Line Number</b></td>
- * <td><b>Exception Flag</b></td>
- * <td><b>Type</b></td>
- * </tr>
- * <tr>
- * <td>Bit 31<br>hardware = 1, software = 0</td>
- * <td>Bits 30..10</td>
- * <td>Bits 9..1<br>See \ref ExFlagDefines</td>
- * <td>Bit 0<br>notify = 1, abort = 0</td>
- * </tr>
- * </table>
- */
- uint32_t esm_exception;
- /* Indicates that the synchronization lost. */
- uint32_t esm_sync_lost;
- /* Indicates that the last AKE Start command was passed. */
- uint32_t esm_auth_pass;
- /* Indicates that the last AKE Start command has failed. */
- uint32_t esm_auth_fail;
-};
-
-/**
- * \details
- *
- * This structure will be filled when ESM firmware successfully started
- * and it contains ESM buffers configuration values.
- *
- */
-struct esm_config_t {
- /* Indicates what ESM firmware running: 0-unknown; 1-RX; 2-TX. */
- uint32_t esm_type;
- /* Indicates maximum size of a topology slot memory. */
- uint32_t topo_buffer_size;
- /* Indicates amount of topology slot memories. */
- uint8_t topo_slots;
- /* Indicates maximum size of the topology seed memory. */
- uint8_t topo_seed_buffer_size;
- /* Indicates maximum size of the logging memory. */
- uint32_t log_buffer_size;
- /* Indicates maximum size of the mailbox memory. */
- uint32_t mb_buffer_size;
- /* Indicates maximum size of the exceptions memory. */
- uint32_t exceptions_buffer_size;
- /* Indicates maximum size of the TX SRM memory. */
- uint32_t srm_buffer_size;
- /* Indicates maximum size of the TX Pairing memory.*/
- uint32_t pairing_buffer_size;
-};
-
-/**
- * \details
- *
- * This structure contains a text log message which can be displayed
- * directly to the user.
- */
-struct esm_logmsg_text_t {
- char *file; /* Firmware source filename. */
- char *msg; /* Human-readable log message. */
- uint16_t line; /* Firmware source line number. */
-};
-
-struct esm_logmsg_bin_t {
- char *msg; /* Human-readable description. */
- uint8_t *data; /* Pointer to first byte of data. */
- uint16_t datalen; /* Number of data bytes. */
-};
-
-/**
- * \details
- *
- * This structure contains a parsed log message from the ESM. The ESM
- * has different types of log messages, which are distinguished by the
- * type value. The actual message (which depends on the type) can be
- * accessed through the appropriate union member.
- */
-struct esm_logmsg_t {
- /* Raw (unparsed) message length (in bytes). */
- uint16_t rawlen;
- /* Type of log message.
- * See \ref LogTypes for a list of supported message types.
- */
- uint8_t type;
- /* Log message ID (-1 if no ID). */
- int32_t id;
- /* Pointer to raw (unparsed) message. */
- uint8_t *raw;
-
- union {
- /* Normal text log message.
- * Only valid if type is #ESM_LOG_TYPE_TEXT.
- */
- struct esm_logmsg_text_t *text;
- /*Binary dump message.
- * Only valid if type is #ESM_LOG_TYPE_BINARY.
- */
- struct esm_logmsg_bin_t *bin;
- } u; /* Union for decoded message data. */
-};
-
-#endif
-
+++ /dev/null
-/*
- * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/elliptic_std_def.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __ELLIPTIC_STD_DEF_H__
-#define __ELLIPTIC_STD_DEF_H__
-
-#ifndef __KERNEL__
-/**
- * \defgroup CALDef Common Definitions
- *
- * This section defines the common shared types
- *
- * \addtogroup CALDef
- * @{
- *
- */
-
-/**
- * \defgroup SysStdTypes Standard Types
- * This section defines the common SHARED STANDARD types
- * \addtogroup SysStdTypes
- * @{
- *
- */
-
-/**
- * \ingroup SysStdTypes Standard Types
- * include <stddef.h>\n
- * > - C89 compliant: if this is not available then add your definition here
- *
- */
- /* C89 compliant - if this is not available then add your definition here */
-#include <stddef.h>
-/**
- * \ingroup SysStdTypes Standard Types
- * include <stdint.h>\n
- * > - C99 compliant: if this is not available then add your definition here
- *
- */
- /* C99 compliant - if this is not available then add your definition here */
-#include <stdint.h>
-/**
- * \ingroup SysStdTypes Standard Types
- * include <stdarg.h>\n
- * > - C89 compliant: if this is not available then add your definition here
- *
- */
-/* C89 compliant - if this is not available then add your definition here */
-#include <stdarg.h>
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-#else
-#include <linux/types.h>
-#include <linux/kernel.h>
-#endif
-
-#endif /* __ELLIPTIC_STD_DEF_H__ */
-
+++ /dev/null
-/*
- * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/elliptic_system_types.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef __ELLIPTIC_SYSTEM_TYPE_H__
-#define __ELLIPTIC_SYSTEM_TYPE_H__
-
-/**
- * \defgroup CALDef Common Definitions
- *
- * This section defines the common shared types
- *
- * \addtogroup CALDef
- * \{
- *
- */
-
-/**
- * \defgroup SysTypes System Types
- *
- * This section defines the common SHARED SYSTEM types
- *
- * \addtogroup SysTypes
- * \{
- *
- */
-
-/* System types definitions. */
-#define ELP_STATUS int16_t
-#define ELP_SYSTEM_INFO int16_t
-#define ELP_SYSTEM_BIG_ENDIAN 0
-#define ELP_SYSTEM_LITLLE_ENDIAN 1
-
-/* PRNG definitions. */
-#define PRINT_FUNC printf_ptr
-#define PRINT_FUNC_DECL int32_t (*PRINT_FUNC)(const void *str, ...)
-#define PRNG_FUNC prng
-#define PRNG_FUNC2 prng2
-#define PRNG_FUNC_DECL uint8_t (*PRNG_FUNC)(void *, void *, uint8_t)
-#define PRNG_FUNC2_DECL uint32_t (*PRNG_FUNC2)(void *, void *, uint32_t)
-
-struct elp_std_prng_info {
- void *prng_inst;
-
- PRNG_FUNC_DECL;
-};
-
-struct elp_std_prng_info2 {
- void *prng_inst;
-
- PRNG_FUNC2_DECL;
-};
-
-#define ELP_STD_PRNG_INFO elp_std_prng_info
-#define ELP_STD_PRNG_INFO2 elp_std_prng_info2
-
-/**
- * \}
- */
-
-/**
- * \}
- */
-
-#endif
-
+++ /dev/null
-/*
- * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/hdcp_main.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/netlink.h>
-#include <linux/proc_fs.h>
-#include <linux/version.h>
-#include <linux/delay.h>
-#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
-
-#include "host_driver_linux_if.h"
-
-#include "../hw/hdmi_tx_reg.h"
-#include "../hw/mach_reg.h"
-
-#define ESM_DEVICE_MAJOR 58
-#define MAX_ESM_DEVICES 6
-
-/* ESM Device */
-struct esm_device {
- int allocated;
- int code_loaded;
- int code_is_phys_mem;
- ulong code_base;
- ulong code_size;
- uint8_t *code;
- int data_is_phys_mem;
- ulong data_base;
- ulong data_size;
- uint8_t *data;
- ulong hpi_base;
- ulong hpi_size;
- uint8_t *hpi;
- int hpi_mem_region_requested;
-};
-
-static void hdcp22_hw_init(void);
-static void set_pkf_duk_nonce(void);
-
-/* Configuration parameters */
-static int verbose;
-static int nonce_mode = 1; /* 1: use HW nonce 0: use SW nonce */
-
-/* Constant strings */
-static const char *MY_TAG = "ESM HLD: ";
-static const char *ESM_DEVICE_NAME = "esm";
-static const char *ESM_DEVICE_CLASS = "elliptic";
-
-/* Linux device, class and range */
-static int device_created;
-static struct device *device;
-static int device_range_registered;
-static int device_class_created;
-static struct class *device_class;
-
-/* ESM devices */
-static struct esm_device esm_devices[MAX_ESM_DEVICES];
-
-/*
- * Processing of the requests from the userspace
- */
-/* Loads the firmware */
-static long cmd_load_code(struct esm_device *esm,
- struct esm_hld_ioctl_load_code *request)
-{
- unsigned long ret = 0;
- uint8_t *kernel_code;
- struct esm_hld_ioctl_load_code krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct esm_hld_ioctl_load_code));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
-
- if (verbose) {
- pr_info("%scmd_load_code: code=%p code_size=0x%x\n",
- MY_TAG, krequest.code, krequest.code_size);
- }
-
- if (esm->code_loaded == 1) {
- pr_info("%scmd_load_code: Code already loaded.\n", MY_TAG);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
- } else {
- if (krequest.code_size > esm->code_size) {
- pr_info("%sCode larger than memory (0x%x > 0x%lx).\n",
- MY_TAG, krequest.code_size, esm->code_size);
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- } else {
- kernel_code = kmalloc(krequest.code_size, GFP_KERNEL);
-
- if (kernel_code) {
- /* No Endian shift */
- ret = copy_from_user(esm->code, krequest.code,
- krequest.code_size);
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
-
- kfree(kernel_code);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose)
- pr_info("%scopying firmware to code memory region.\n",
- MY_TAG);
- } else {
- pr_info("%sFailed to allocate (code_size=0x%x)\n",
- MY_TAG, krequest.code_size);
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- }
- }
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_load_code));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- esm->code_loaded =
- (krequest.returned_status == ESM_HL_DRIVER_SUCCESS);
-
- return 0;
-}
-
-static long cmd_load_code32(struct esm_device *esm,
- struct compact_esm_hld_ioctl_load_code *request)
-{
- unsigned long ret = 0;
- ulong r;
- struct compact_esm_hld_ioctl_load_code __user *uf = request;
- uint8_t *kernel_code;
- struct compact_esm_hld_ioctl_load_code krequest;
-
- memset(&krequest, 0, sizeof(struct compact_esm_hld_ioctl_load_code));
- r = get_user(krequest.code, &uf->code);
- r |= get_user(krequest.code_size, &uf->code_size);
- if (r)
- return -EFAULT;
-
- if (esm->code_loaded == 1) {
- pr_info("%scmd_load_code: Code already loaded.\n", MY_TAG);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
- } else {
- if (krequest.code_size > esm->code_size) {
- pr_info("%sCode size larger than code memory (0x%x > 0x%lx).\n",
- MY_TAG, krequest.code_size, esm->code_size);
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- } else {
- kernel_code = kmalloc(krequest.code_size, GFP_KERNEL);
-
- if (kernel_code) {
- pr_info("%s[%d]\n", __func__, __LINE__);
- /* No Endian shift */
- ret = copy_from_user(esm->code, compat_ptr(krequest.code),
- krequest.code_size);
- if (ret)
- pr_info("copy %ld Bytes\n", ret);
-
- kfree(kernel_code);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose)
- pr_info("%scopying firmware to code memory region.\n",
- MY_TAG);
- } else {
- pr_info("%sFailed to allocat memory (code_size=0x%x)\n",
- MY_TAG, krequest.code_size);
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- }
- }
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct compact_esm_hld_ioctl_load_code));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- esm->code_loaded =
- (krequest.returned_status == ESM_HL_DRIVER_SUCCESS);
-
- return 0;
-}
-
-/* Returns the physical address of the code */
-static long cmd_get_code_phys_addr(struct esm_device *esm,
- struct esm_hld_ioctl_get_code_phys_addr *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_get_code_phys_addr krequest;
-
- krequest.returned_phys_addr = esm->code_base;
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%scmd_get_code_phys_addr: returning code_base=0x%x\n",
- MY_TAG, krequest.returned_phys_addr);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_get_code_phys_addr));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Returns the physical address of the data */
-static long cmd_get_data_phys_addr(struct esm_device *esm,
- struct esm_hld_ioctl_get_data_phys_addr *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_get_data_phys_addr krequest;
-
- krequest.returned_phys_addr = esm->data_base;
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%scmd_get_data_phys_addr: returning data_base=0x%x\n",
- MY_TAG, krequest.returned_phys_addr);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_get_data_phys_addr));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Returns the size of the data memory region */
-static long cmd_get_data_size(struct esm_device *esm,
- struct esm_hld_ioctl_get_data_size *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_get_data_size krequest;
-
- krequest.returned_data_size = esm->data_size;
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%scmd_get_data_size: returning data_size=0x%x\n",
- MY_TAG, krequest.returned_data_size);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_get_data_size));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Reads a single 32-bit HPI register */
-static long cmd_hpi_read(struct esm_device *esm,
- struct esm_hld_ioctl_hpi_read *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_hpi_read krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct esm_hld_ioctl_hpi_read));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- if (verbose) {
- pr_info("%scmd_hpi_read: Reading register at offset 0x%x\n",
- MY_TAG, krequest.offset);
- }
-
- if (esm->hpi) {
- krequest.returned_data = hdcp22_rd_reg(krequest.offset);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%scmd_hpi_read: Returning data=0x%x\n",
- MY_TAG, krequest.returned_data);
- }
- } else {
- krequest.returned_data = 0;
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- pr_info("%scmd_hpi_read: No memory.\n", MY_TAG);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_hpi_read));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Writes a single 32-bit HPI register */
-static long cmd_hpi_write(struct esm_device *esm,
- struct esm_hld_ioctl_hpi_write *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_hpi_write krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct esm_hld_ioctl_hpi_write));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- if (krequest.offset == 0x40) {
- hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1);
- hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_CTRL, 0x6);
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1);
- udelay(10);
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1);
- udelay(10);
- hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MASK, 0);
- hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MUTE, 0);
- set_pkf_duk_nonce();
- }
- if (verbose) {
- pr_info("%sWriting 0x%X to register at offset 0x%X\n",
- MY_TAG, krequest.data, krequest.offset);
- }
-
- if (esm->hpi) {
- hdcp22_wr_reg(krequest.offset, (uint32_t)krequest.data);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%sWrote 0x%X to register at offset 0x%X\n",
- MY_TAG, krequest.data, krequest.offset);
- }
- } else {
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- pr_info("%scmd_hpi_write: No memory.\n", MY_TAG);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_hpi_write));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Reads from a region of the data memory */
-static long cmd_data_read(struct esm_device *esm,
- struct esm_hld_ioctl_data_read *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_data_read krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct esm_hld_ioctl_data_read));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- if (verbose) {
- pr_info("%sReading %u bytes at offset offset 0x%x\n",
- MY_TAG, krequest.nbytes, krequest.offset);
- }
-
- if (esm->data) {
- if (krequest.offset + krequest.nbytes > esm->data_size) {
- krequest.returned_status = ESM_HL_DRIVER_INVALID_PARAM;
- pr_info("%scmd_data_read: Invalid offset and size.\n",
- MY_TAG);
- } else {
- ret = copy_to_user(krequest.dest_buf,
- esm->data + krequest.offset, krequest.nbytes);
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%sreading %u at offset 0x%x\n",
- MY_TAG, krequest.nbytes,
- krequest.offset);
- }
- }
- } else {
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- pr_info("%scmd_data_read: No memory.\n", MY_TAG);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_data_read));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Reads from a region of the data memory */
-static long cmd_data_read32(struct esm_device *esm,
- struct compact_esm_hld_ioctl_data_read *request)
-{
- unsigned long ret = 0;
- struct compact_esm_hld_ioctl_data_read krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct compact_esm_hld_ioctl_data_read));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- if (verbose) {
- pr_info("%sReading %u offset offset 0x%x\n",
- MY_TAG, krequest.nbytes, krequest.offset);
- }
-
- if (esm->data) {
- if (krequest.offset + krequest.nbytes > esm->data_size) {
- krequest.returned_status = ESM_HL_DRIVER_INVALID_PARAM;
- pr_info("%scmd_data_read: Invalid offset and size.\n",
- MY_TAG);
- } else {
- ret = copy_to_user(compat_ptr(krequest.dest_buf),
- esm->data + krequest.offset, krequest.nbytes);
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%sreading %u bytes at offset 0x%x\n",
- MY_TAG, krequest.nbytes, krequest.offset);
- }
- }
- } else {
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- pr_info("%scmd_data_read: No memory.\n", MY_TAG);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct compact_esm_hld_ioctl_data_read));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Writes to a region of the data memory */
-static long cmd_data_write(struct esm_device *esm,
- struct esm_hld_ioctl_data_write *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_data_write krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct esm_hld_ioctl_data_write));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- if (verbose) {
- pr_info("%sWriting %u bytes to data memory at offset 0x%x\n",
- MY_TAG, krequest.nbytes, krequest.offset);
- }
-
- if (esm->data) {
- if (krequest.offset + krequest.nbytes > esm->data_size) {
- krequest.returned_status = ESM_HL_DRIVER_INVALID_PARAM;
- pr_info("%scmd_data_write: Invalid offset and size.\n",
- MY_TAG);
- } else {
- ret = copy_from_user(esm->data + krequest.offset,
- krequest.src_buf, krequest.nbytes);
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%swriting %u to 0x%x\n",
- MY_TAG, krequest.nbytes,
- krequest.offset);
- }
- }
- } else {
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- pr_info("%scmd_data_write: No memory.\n", MY_TAG);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_data_write));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Writes to a region of the data memory */
-static long cmd_data_write32(struct esm_device *esm,
- struct compact_esm_hld_ioctl_data_write *request)
-{
- unsigned long ret = 0;
- struct compact_esm_hld_ioctl_data_write krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct compact_esm_hld_ioctl_data_write));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- if (verbose) {
- pr_info("%sWriting %u bytes to memory at offset 0x%x\n",
- MY_TAG, krequest.nbytes, krequest.offset);
- }
-
- if (esm->data) {
- if (krequest.offset + krequest.nbytes > esm->data_size) {
- krequest.returned_status = ESM_HL_DRIVER_INVALID_PARAM;
- pr_info("%scmd_data_write: Invalid offset and size.\n",
- MY_TAG);
- } else {
- ret = copy_from_user(esm->data + krequest.offset,
- compat_ptr(krequest.src_buf), krequest.nbytes);
- if (ret)
- pr_info("copy %ld Bytes\n", ret);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%swriting %u at offset 0x%x\n",
- MY_TAG, krequest.nbytes,
- krequest.offset);
- }
- }
- } else {
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- pr_info("%scmd_data_write: No memory.\n", MY_TAG);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct compact_esm_hld_ioctl_data_write));
- if (ret)
- pr_info("copy %ld Bytes\n", ret);
- return 0;
-}
-
-/* Sets a region of the data memory to a given 8-bit value */
-static long cmd_data_set(struct esm_device *esm,
- struct esm_hld_ioctl_data_set *request)
-{
- unsigned long ret = 0;
- struct esm_hld_ioctl_data_set krequest;
-
- ret = copy_from_user(&krequest, request,
- sizeof(struct esm_hld_ioctl_data_set));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- if (verbose) {
- pr_info("%sSetting %u bytes (data=0x%x) from offset 0x%x\n",
- MY_TAG, krequest.nbytes, krequest.data,
- krequest.offset);
- }
-
- if (esm->data) {
- if (krequest.offset + krequest.nbytes > esm->data_size) {
- krequest.returned_status = ESM_HL_DRIVER_INVALID_PARAM;
- pr_info("%scmd_data_set: Invalid offset and size.\n",
- MY_TAG);
- } else {
- memset(esm->data + krequest.offset, krequest.data,
- krequest.nbytes);
- krequest.returned_status = ESM_HL_DRIVER_SUCCESS;
-
- if (verbose) {
- pr_info("%ssetting %u data=0x%x offset 0x%x\n",
- MY_TAG, krequest.nbytes, krequest.data,
- krequest.offset);
- }
- }
- } else {
- krequest.returned_status = ESM_HL_DRIVER_NO_MEMORY;
- pr_info("%scmd_data_set: No memory.\n", MY_TAG);
- }
-
- ret = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_data_set));
- if (ret)
- pr_info("copy left %ld Bytes\n", ret);
- return 0;
-}
-
-/* Opens an ESM device. Associates a device file to an ESM device. */
-static long cmd_esm_open(struct file *f,
- struct esm_hld_ioctl_esm_open *request)
-{
- unsigned long r = 0;
- int i;
- struct esm_device *esm = esm_devices;
- int ret = ESM_HL_DRIVER_SUCCESS;
- struct esm_hld_ioctl_esm_open krequest;
-
- r = copy_from_user(&krequest, request,
- sizeof(struct esm_hld_ioctl_esm_open));
- if (r)
- pr_info("copy left %ld Bytes\n", r);
- f->private_data = NULL;
- /* Look for a matching ESM device (based on HPI address) */
- for (i = MAX_ESM_DEVICES; i--; esm++) {
- if (esm->allocated && (krequest.hpi_base == esm->hpi_base)) {
- /* Found it */
- f->private_data = esm;
- break;
- }
- }
-
- if (!f->private_data) {
- /* Not found. Allocate a new ESM device. */
- esm = esm_devices;
-
- for (i = MAX_ESM_DEVICES; i--; esm++) {
- if (!esm->allocated) {
- dma_addr_t dh;
- char region_name[20];
-
- esm->allocated = 1;
- esm->hpi_base = krequest.hpi_base;
- /* this can be static since the HPI
- * interface will not change
- */
- esm->hpi_size = 0x100;
- esm->code_base = krequest.code_base;
- esm->code_size = krequest.code_size;
- esm->data_base = krequest.data_base;
- esm->data_size = krequest.data_size;
-
- pr_info("%sNew ESM device:\n\n", MY_TAG);
- pr_info(" hpi_base: 0x%lx\n", esm->hpi_base);
- pr_info(" hpi_size: 0x%lx\n", esm->hpi_size);
- pr_info(" code_base: 0x%lx\n", esm->code_base);
- pr_info(" code_size: 0x%lx\n", esm->code_size);
- pr_info(" data_base: 0x%lx\n", esm->data_base);
- pr_info(" data_size: 0x%lx\n\n",
- esm->data_size);
-
- /* Initialize the code memory */
- if (esm->code_base) {
- esm->code_is_phys_mem = 1;
- esm->code =
- phys_to_virt(esm->code_base);
- pr_info("Code is at PhyAddr 0x%lx\n",
- esm->code_base);
- } else {
- esm->code = dma_alloc_coherent(
- (struct device *)esm,
- esm->code_size, &dh,
- GFP_KERNEL);
-
- if (!esm->code) {
- pr_info("%sFailed alloca (%ld bytes)\n",
- MY_TAG, esm->code_size);
- ret = ESM_HL_DRIVER_NO_MEMORY;
- break;
- }
- esm->code_base = dh;
- pr_info("%sBase allocated: phys=0x%lx virt=%p\n",
- MY_TAG, esm->code_base, esm->code);
- }
-
- /* Initialize the data memory */
- if (esm->data_base) {
- esm->data_is_phys_mem = 1;
- esm->data = phys_to_virt(esm->data_base);
- pr_info("Data is at physical address 0x%lx\n",
- esm->code_base);
- } else {
- esm->data = dma_alloc_coherent((struct device *)esm,
- esm->data_size, &dh, GFP_KERNEL);
-
- if (!esm->data) {
- pr_info("%sFailed to allocate (%ld bytes)\n",
- MY_TAG, esm->data_size);
- ret = ESM_HL_DRIVER_NO_MEMORY;
- break;
- }
-
- esm->data_base = dh;
- pr_info("%sBaseAddr of allocated: phys=0x%lx virt=%p\n",
- MY_TAG, esm->data_base, esm->data);
- }
-
- /* Init HPI access */
- sprintf(region_name, "ESM-%lX", esm->hpi_base);
- request_mem_region(esm->hpi_base, esm->hpi_size, region_name);
- esm->hpi_mem_region_requested = 1;
- esm->hpi = ioremap_nocache(esm->hpi_base, esm->hpi_size);
-
- /* Associate the Linux file to the ESM device */
- f->private_data = esm;
- break;
- }
- }
- }
-
- if (!f->private_data) {
- pr_info("%scmd_esm_open: Too many ESM devices.\n", MY_TAG);
- ret = ESM_HL_DRIVER_TOO_MANY_ESM_DEVICES;
- }
-
- krequest.returned_status = ret;
- r = copy_to_user(request, &krequest,
- sizeof(struct esm_hld_ioctl_esm_open));
- if (r)
- pr_info("copy left %ld Bytes\n", r);
- return 0;
-}
-
-/*
- * Linux Device
- */
-
-/* The device has been opened */
-static int device_open(struct inode *inode, struct file *filp)
-{
- if (verbose)
- pr_info("%sDevice opened.\n", MY_TAG);
-
- /* No associated ESM device yet.
- * Use IOCTL ESM_HLD_IOCTL_ESM_OPEN to associate an ESM
- * to the opened device file.
- */
- filp->private_data = NULL;
-
- return 0;
-}
-
-/* The device has been closed */
-static int device_release(struct inode *inode, struct file *filp)
-{
- if (verbose)
- pr_info("%sDevice released.\n", MY_TAG);
-
-
- return 0;
-}
-
-/* IOCTL operation on the device */
-static long device_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
-{
- arg = (unsigned long)compat_ptr(arg);
-
- switch (cmd) {
- case ESM_HLD_IOCTL_LOAD_CODE:
- return cmd_load_code(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_load_code *)arg);
-
- case ESM_HLD_IOCTL_LOAD_CODE32:
- return cmd_load_code32(
- (struct esm_device *)f->private_data,
- (struct compact_esm_hld_ioctl_load_code *)arg);
-
- case ESM_HLD_IOCTL_GET_CODE_PHYS_ADDR:
- return cmd_get_code_phys_addr(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_get_code_phys_addr *)arg);
-
- case ESM_HLD_IOCTL_GET_DATA_PHYS_ADDR:
- return cmd_get_data_phys_addr(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_get_data_phys_addr *)arg);
-
- case ESM_HLD_IOCTL_GET_DATA_SIZE:
- return cmd_get_data_size(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_get_data_size *)arg);
-
- case ESM_HLD_IOCTL_HPI_READ:
- return cmd_hpi_read(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_hpi_read *)arg);
-
- case ESM_HLD_IOCTL_HPI_WRITE:
- return cmd_hpi_write(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_hpi_write *)arg);
-
- case ESM_HLD_IOCTL_DATA_READ:
- return cmd_data_read(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_data_read *)arg);
-
- case ESM_HLD_IOCTL_DATA_READ32:
- return cmd_data_read32(
- (struct esm_device *)f->private_data,
- (struct compact_esm_hld_ioctl_data_read *)arg);
-
- case ESM_HLD_IOCTL_DATA_WRITE:
- return cmd_data_write(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_data_write *)arg);
-
- case ESM_HLD_IOCTL_DATA_WRITE32:
- return cmd_data_write32(
- (struct esm_device *)f->private_data,
- (struct compact_esm_hld_ioctl_data_write *)arg);
-
- case ESM_HLD_IOCTL_DATA_SET:
- return cmd_data_set(
- (struct esm_device *)f->private_data,
- (struct esm_hld_ioctl_data_set *)arg);
-
- case ESM_HLD_IOCTL_ESM_OPEN:
- return cmd_esm_open(f, (struct esm_hld_ioctl_esm_open *)arg);
- }
-
-
- return -1;
-}
-
-static void dump_device_info(struct esm_device *dev)
-{
- pr_info(" allocated = %d\n", dev->allocated);
- pr_info(" code_loaded = %d\n", dev->code_loaded);
- pr_info(" code_is_phys_mem = %d\n", dev->code_is_phys_mem);
- pr_info(" code_base = 0x%lx\n", dev->code_base);
- pr_info(" code_size = %lu\n", dev->code_size);
- pr_info(" code = 0x%p\n", dev->code);
- pr_info(" data_is_phys_mem = %d\n", dev->data_is_phys_mem);
- pr_info(" data_base = 0x%lx\n", dev->data_base);
- pr_info(" data_size = %lu\n", dev->data_size);
- pr_info(" data = 0x%p\n", dev->data);
- pr_info(" hpi_base = 0x%lx\n", dev->hpi_base);
- pr_info(" hpi_size = %lu\n", dev->hpi_size);
- pr_info(" hpi = 0x%p\n", dev->hpi);
- pr_info(" hpi_mem_region_requested = %d\n",
- dev->hpi_mem_region_requested);
-}
-
-static void dump_device_raw(const uint8_t *buf, uint32_t size)
-{
- uint32_t i;
-
- pr_info("Dump Addr: 0x%p Size: %d\n", buf, size);
- pr_info("==============DUMP START==============\n");
- for (i = 0; i < size; i += 8)
- pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
- buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4],
- buf[i+5], buf[i+6], buf[i+7]);
- pr_info("==============DUMP END ==============\n");
-}
-
-#define DUMP_SECTION(prefix, start, end) \
-do { \
- if (start > end) { \
- pr_info("Error start = 0x%x > end = 0x%x\n", (uint32_t)start, \
- (uint32_t)end); \
- break; \
- } \
- pr_info("Dump %s\n", prefix); \
- for (addr = start; addr < end + 1; addr++) { \
- val = hdmitx_rd_reg(addr); \
- if (val) \
- pr_info("[0x%08x]: 0x%08x\n", addr, val); \
- } \
-} while (0)
-
-static void dump_snps_regs(void)
-{
- unsigned int addr;
- unsigned int val;
-
- DUMP_SECTION("TOP", HDMITX_TOP_SW_RESET, HDMITX_TOP_STAT0);
- DUMP_SECTION("TOPSec", HDMITX_TOP_SKP_CNTL_STAT, HDMITX_TOP_DUK_3);
- DUMP_SECTION("TOP", HDMITX_TOP_INFILTER, HDMITX_TOP_NSEC_SCRATCH);
- DUMP_SECTION("TOPSec", HDMITX_TOP_SEC_SCRATCH, HDMITX_TOP_SEC_SCRATCH);
- DUMP_SECTION("TOP", HDMITX_TOP_DONT_TOUCH0, HDMITX_TOP_DONT_TOUCH1);
- DUMP_SECTION("DWC", HDMITX_DWC_DESIGN_ID, HDMITX_DWC_CSC_LIMIT_DN_LSB);
- DUMP_SECTION("DWCSec", HDMITX_DWC_A_HDCPCFG0, HDMITX_DWC_A_HDCPCFG1);
- DUMP_SECTION("DWC", HDMITX_DWC_A_HDCPOBS0, HDMITX_DWC_A_KSVMEMCTRL);
- /* Exclude HDMITX_DWC_HDCP_BSTATUS_0 to HDMITX_DWC_HDCPREG_RMLCTL */
- DUMP_SECTION("DWC", HDMITX_DWC_HDCPREG_RMLSTS,
- HDMITX_DWC_HDCPREG_RMLSTS);
- DUMP_SECTION("DWCSec", HDMITX_DWC_HDCPREG_SEED0,
- HDMITX_DWC_HDCPREG_DPK6);
- DUMP_SECTION("DWC", HDMITX_DWC_HDCP22REG_ID,
- HDMITX_DWC_HDCP22REG_ID);
- DUMP_SECTION("DWCSec", HDMITX_DWC_HDCP22REG_CTRL,
- HDMITX_DWC_HDCP22REG_CTRL);
- DUMP_SECTION("DWC", HDMITX_DWC_HDCP22REG_CTRL1,
- HDMITX_DWC_I2CM_SCDC_UPDATE1);
-}
-
-#define DBG_HELP_STR \
- "dev_infoN: show the Nth esm devices info\n" \
- "dumpesm: deump ESM registers\n" \
- "dumpsnps: dump SNPS registers\n" \
- "reset: reset ESM cpu\n"
-
-static ssize_t show_debug(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- int pos = 0;
- static const char *dbg_help = DBG_HELP_STR;
-
- pos += snprintf(buf+pos, PAGE_SIZE, "%s", dbg_help);
- return pos;
-}
-
-static ssize_t store_debug(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count)
-{
- int ret;
- unsigned long idx;
-
- if (strncmp(buf, "dev_info", 8) == 0) {
- ret = kstrtoul(buf+8, 10, &idx);
- if (idx >= MAX_ESM_DEVICES)
- pr_info("MAX_ESM_DEVICES is %d\n", MAX_ESM_DEVICES);
- else {
- pr_info("esm_devices NO %lu\n", idx);
- dump_device_info(&esm_devices[idx]);
- }
- return 16;
- }
- if (strncmp(buf, "dumpsnps", 8) == 0) {
- dump_snps_regs();
- return 16;
- }
- if (strncmp(buf, "dumpesm", 7) == 0) {
- uint32_t i;
- uint32_t val;
-
- for (i = 0; i < 0x100; i += 4) {
- val = hdcp22_rd_reg(i);
- if (val)
- pr_info("hdcp22 0x%02x: 0x%08x\n", i, val);
- }
- return 16;
- }
- if (strncmp(buf, "dumpcode", 8) == 0) {
- ret = kstrtoul(buf+8, 10, &idx);
- if (idx >= MAX_ESM_DEVICES)
- pr_info("MAX_ESM_DEVICES is %d\n", MAX_ESM_DEVICES);
- else {
- pr_info("esm_devices NO %lu\n", idx);
- dump_device_raw((uint8_t *)esm_devices[idx].code,
- esm_devices[idx].code_size);
- }
- return 16;
- }
- if (strncmp(buf, "dumpdata", 8) == 0) {
- ret = kstrtoul(buf+8, 10, &idx);
- if (idx >= MAX_ESM_DEVICES)
- pr_info("MAX_ESM_DEVICES is %d\n", MAX_ESM_DEVICES);
- else {
- pr_info("esm_devices NO %lu\n", idx);
- dump_device_raw((uint8_t *)esm_devices[idx].data,
- esm_devices[idx].data_size);
- }
- return 16;
- }
- if (strncmp(buf, "dumphpi", 7) == 0) {
- ret = kstrtoul(buf+7, 10, &idx);
- if (idx >= MAX_ESM_DEVICES)
- pr_info("MAX_ESM_DEVICES is %d\n", MAX_ESM_DEVICES);
- else {
- pr_info("esm_devices NO %lu\n", idx);
- dump_device_raw((uint8_t *)esm_devices[idx].hpi,
- esm_devices[idx].hpi_size);
- }
- return 16;
- }
- if (strncmp(buf, "reset", 5) == 0) {
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1);
- mdelay(2);
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1);
- pr_info("reset done\n");
- }
- return 16;
-}
-
-static DEVICE_ATTR(debug, 0644, show_debug, store_debug);
-
-/* Creates the device required to interface with the HLD driver */
-static int create_device(void)
-{
- int ret = 0;
-
- pr_info("%sCreating device '%s'...\n",
- MY_TAG, ESM_DEVICE_NAME);
-
- device = device_create(device_class, NULL, MKDEV(ESM_DEVICE_MAJOR, 0),
- NULL, ESM_DEVICE_NAME);
-
- if (IS_ERR(device)) {
- pr_info("%sFailed to create device '%s'.\n",
- MY_TAG, ESM_DEVICE_NAME);
- return PTR_ERR(device);
- }
- ret = device_create_file(device, &dev_attr_debug);
- device_created = 1;
- pr_info("%sDevice '%s' has been created.\n",
- MY_TAG, ESM_DEVICE_NAME);
-
- return 0;
-}
-
-/* Destroys the interface device */
-static void end_device(void)
-{
- int i;
- struct esm_device *esm = esm_devices;
-
- if (device_created) {
- pr_info("%sDeleting device '%s'...\n",
- MY_TAG, ESM_DEVICE_NAME);
- device_remove_file(device, &dev_attr_debug);
- device_destroy(device_class, MKDEV(ESM_DEVICE_MAJOR, 0));
- device_created = 0;
- }
-
- for (i = MAX_ESM_DEVICES; i--; esm++) {
- if (esm->allocated) {
- if (esm->code && !esm->code_is_phys_mem) {
- dma_addr_t dh = (dma_addr_t)esm->code_base;
-
- dma_free_coherent(NULL, esm->code_size,
- esm->code, dh);
- }
-
- if (esm->data && !esm->data_is_phys_mem) {
- dma_addr_t dh = (dma_addr_t)esm->data_base;
-
- dma_free_coherent(NULL, esm->data_size,
- esm->data, dh);
- }
-
- if (esm->hpi)
- iounmap(esm->hpi);
-
- if (esm->hpi_mem_region_requested)
- release_mem_region(esm->hpi_base,
- esm->hpi_size);
- }
- }
-
- memset(esm_devices, 0, sizeof(esm_devices));
-}
-
-/*
- * Linux device class and range
- */
-/* Table of the supported operations on ESM devices */
-static const struct file_operations device_file_operations = {
- .open = device_open,
- .release = device_release,
-/* .unlocked_ioctl = device_ioctl, */
- .compat_ioctl = device_ioctl,
- .owner = THIS_MODULE,
-};
-
-static int register_device_range(void)
-{
- int ret;
-
- pr_info("%sRegistering device range '%s'...\n",
- MY_TAG, ESM_DEVICE_NAME);
-
- ret = register_chrdev(ESM_DEVICE_MAJOR, ESM_DEVICE_NAME,
- &device_file_operations);
-
- if (ret < 0) {
- pr_info("%sFailed to register device range '%s'.\n",
- MY_TAG, ESM_DEVICE_NAME);
- return ret;
- }
-
- pr_info("%sDevice range '%s' has been registered.\n",
- MY_TAG, ESM_DEVICE_NAME);
- device_range_registered = 1;
-
- return 0;
-}
-
-static void unregister_device_range(void)
-{
- if (device_range_registered) {
- pr_info("%sUnregistering device range '%s'...\n",
- MY_TAG, ESM_DEVICE_NAME);
- unregister_chrdev(ESM_DEVICE_MAJOR, ESM_DEVICE_NAME);
- device_range_registered = 0;
- }
-}
-
-/*
- * Creates the interface device class.
- * Note: Attributes could be created for that class.
- * Not required at this time.
- */
-static int create_device_class(void)
-{
- pr_info("%sCreating class /sys/class/%s...\n",
- MY_TAG, ESM_DEVICE_CLASS);
-
- device_class = class_create(THIS_MODULE, ESM_DEVICE_CLASS);
-
- if (IS_ERR(device_class)) {
- pr_info("%sFailed to create device class /sys/class/%s.\n",
- MY_TAG, ESM_DEVICE_CLASS);
- return PTR_ERR(device_class);
- }
-
- device_class_created = 1;
- pr_info("%sThe class /sys/class/%s has been created.\n",
- MY_TAG, ESM_DEVICE_CLASS);
-
- return 0;
-}
-
-/* Ends the device class of the ESM devices */
-static void end_device_class(void)
-{
- if (device_class_created) {
- pr_info("%sDeleting the device class /sys/class/%s...\n",
- MY_TAG, ESM_DEVICE_CLASS);
- class_destroy(device_class);
- device_class_created = 0;
- }
-}
-
-static void set_pkf_duk_nonce(void)
-{
- /* Configure duk/pkf */
- hdmitx_hdcp_opr(0xc);
- if (nonce_mode == 1)
- hdmitx_wr_reg(HDMITX_TOP_SKP_CNTL_STAT, 0xf);
- else {
- hdmitx_wr_reg(HDMITX_TOP_SKP_CNTL_STAT, 0xe);
-/* Configure nonce[127:0].
- * MSB must be written the last to assert nonce_vld signal.
- */
- hdmitx_wr_reg(HDMITX_TOP_NONCE_0, 0x32107654);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_1, 0xba98fedc);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_2, 0xcdef89ab);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_3, 0x45670123);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_0, 0x76543210);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_1, 0xfedcba98);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_2, 0x89abcdef);
- hdmitx_wr_reg(HDMITX_TOP_NONCE_3, 0x01234567);
- }
- mdelay(10);
-}
-
-static void hdcp22_hw_init(void)
-{
- hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 1, 7, 1);
- hdmitx_wr_reg(HDMITX_DWC_A_HDCPCFG1, 0x7);
- hdmitx_wr_reg(HDMITX_DWC_A_HDCPCFG0, 0x53);
- hd_set_reg_bits(P_HHI_GCLK_MPEG2, 1, 3, 1);
- hd_write_reg(P_HHI_HDCP22_CLK_CNTL, 0x01000100);
- /* Enable skpclk to HDCP2.2 IP */
- hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 7, 1);
- /* Enable esmclk to HDCP2.2 IP */
- hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 6, 1);
- /* Enable tmds_clk to HDCP2.2 IP */
- hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 5, 1);
-#if 0
- /* sw_reset_hdcp22: to reset HDCP2.2 IP */
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1);
- mdelay(10);
- hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1);
-#endif
- set_pkf_duk_nonce();
-}
-
-/*
- * Initialization/termination of the module
- */
-static int __init hld_init(void)
-{
- struct hdmitx_dev *hdmitx_device = get_hdmitx_device();
-
- pr_info("%sInitializing...\n", MY_TAG);
- if (hdmitx_device->hdtx_dev == NULL) {
- pr_info("%sExit for null device of hdmitx!\n", MY_TAG);
- return -ENODEV;
- }
-
- memset(esm_devices, 0, sizeof(esm_devices));
-
- if ((register_device_range() == 0) && (create_device_class() == 0) &&
- (create_device() == 0))
- pr_info("%sDone initializing the HLD driver.\n",
- MY_TAG);
-
- else
- pr_info("%sFailed to initialize the HLD driver.\n",
- MY_TAG);
-
- hdcp22_hw_init();
- return 0;
-}
-
-static void __exit hld_exit(void)
-{
- struct hdmitx_dev *hdmitx_device = get_hdmitx_device();
-
- pr_info("%sExiting...\n", MY_TAG);
- if (hdmitx_device->hdtx_dev == NULL) {
- pr_info("%sExit for null device of hdmitx!\n", MY_TAG);
- return;
- }
-
- end_device();
- end_device_class();
- unregister_device_range();
- pr_info("%sDone.\n", MY_TAG);
-}
-
-module_init(hld_init);
-module_exit(hld_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Elliptic Technologies");
-MODULE_DESCRIPTION("ESM Linux Host Library Driver");
-
-module_param(verbose, int, 0644);
-MODULE_PARM_DESC(verbose, "Enable (1) or disable (0) the debug traces.");
-
-module_param(nonce_mode, int, 0644);
-MODULE_PARM_DESC(nonce_mode, "Enable (1) or disable (0) the debug traces.");
+++ /dev/null
-/*
- * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/host_driver_linux_if.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _HOST_LIB_DRIVER_LINUX_IF_H_
-#define _HOST_LIB_DRIVER_LINUX_IF_H_
-
-#ifdef __KERNEL__
-#include <linux/ioctl.h>
-#else
-#include <sys/ioctl.h>
-#endif
-
-#include "ESMHostTypes.h"
-#include "ESMHostLibDriverErrors.h"
-
-/* ESM_HLD_IOCTL_LOAD_CODE */
-struct esm_hld_ioctl_load_code {
- uint8_t *code;
- uint32_t code_size;
- ESM_STATUS returned_status;
-};
-
-struct compact_esm_hld_ioctl_load_code {
- compat_uptr_t code;
- uint32_t code_size;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_GET_CODE_PHYS_ADDR */
-struct esm_hld_ioctl_get_code_phys_addr {
- uint32_t returned_phys_addr;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_GET_DATA_PHYS_ADDR */
-struct esm_hld_ioctl_get_data_phys_addr {
- uint32_t returned_phys_addr;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_GET_DATA_SIZE */
-struct esm_hld_ioctl_get_data_size {
- uint32_t returned_data_size;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_HPI_READ */
-struct esm_hld_ioctl_hpi_read {
- uint32_t offset;
- uint32_t returned_data;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_HPI_WRITE */
-struct esm_hld_ioctl_hpi_write {
- uint32_t offset;
- uint32_t data;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_DATA_READ */
-struct esm_hld_ioctl_data_read {
- uint32_t offset;
- uint32_t nbytes;
- uint8_t *dest_buf;
- ESM_STATUS returned_status;
-};
-
-struct compact_esm_hld_ioctl_data_read {
- uint32_t offset;
- uint32_t nbytes;
- compat_uptr_t dest_buf;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_DATA_WRITE */
-struct esm_hld_ioctl_data_write {
- uint32_t offset;
- uint32_t nbytes;
- uint8_t *src_buf;
- ESM_STATUS returned_status;
-};
-
-struct compact_esm_hld_ioctl_data_write {
- uint32_t offset;
- uint32_t nbytes;
- compat_uptr_t src_buf;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_DATA_SET */
-struct esm_hld_ioctl_data_set {
- uint32_t offset;
- uint32_t nbytes;
- uint8_t data;
- ESM_STATUS returned_status;
-};
-
-/* ESM_HLD_IOCTL_ESM_OPEN */
-struct esm_hld_ioctl_esm_open {
- uint32_t hpi_base;
- uint32_t code_base;
- uint32_t code_size;
- uint32_t data_base;
- uint32_t data_size;
- ESM_STATUS returned_status;
-};
-
-/* IOCTL commands */
-#define ESM_HLD_IOC_MAGIC 'E'
-#define ESM_HLD_IOCTL_LOAD_CODE \
- _IOWR(ESM_HLD_IOC_MAGIC, 1000, struct esm_hld_ioctl_load_code)
-#define ESM_HLD_IOCTL_GET_CODE_PHYS_ADDR \
- _IOR(ESM_HLD_IOC_MAGIC, 1001, struct esm_hld_ioctl_get_code_phys_addr)
-#define ESM_HLD_IOCTL_GET_DATA_PHYS_ADDR \
- _IOR(ESM_HLD_IOC_MAGIC, 1002, struct esm_hld_ioctl_get_data_phys_addr)
-#define ESM_HLD_IOCTL_GET_DATA_SIZE \
- _IOR(ESM_HLD_IOC_MAGIC, 1003, struct esm_hld_ioctl_get_data_size)
-#define ESM_HLD_IOCTL_HPI_READ \
- _IOWR(ESM_HLD_IOC_MAGIC, 1004, struct esm_hld_ioctl_hpi_read)
-#define ESM_HLD_IOCTL_HPI_WRITE \
- _IOWR(ESM_HLD_IOC_MAGIC, 1005, struct esm_hld_ioctl_hpi_write)
-#define ESM_HLD_IOCTL_DATA_READ \
- _IOWR(ESM_HLD_IOC_MAGIC, 1006, struct esm_hld_ioctl_data_read)
-#define ESM_HLD_IOCTL_DATA_WRITE \
- _IOWR(ESM_HLD_IOC_MAGIC, 1007, struct esm_hld_ioctl_data_write)
-#define ESM_HLD_IOCTL_DATA_SET \
- _IOWR(ESM_HLD_IOC_MAGIC, 1008, struct esm_hld_ioctl_data_set)
-#define ESM_HLD_IOCTL_ESM_OPEN \
- _IOWR(ESM_HLD_IOC_MAGIC, 1009, struct esm_hld_ioctl_esm_open)
-#define ESM_HLD_IOCTL_LOAD_CODE32 \
- _IOWR(ESM_HLD_IOC_MAGIC, 1000, struct compact_esm_hld_ioctl_load_code)
-#define ESM_HLD_IOCTL_DATA_READ32 \
- _IOWR(ESM_HLD_IOC_MAGIC, 1006, struct compact_esm_hld_ioctl_data_read)
-#define ESM_HLD_IOCTL_DATA_WRITE32 \
- _IOWR(ESM_HLD_IOC_MAGIC, 1007, struct compact_esm_hld_ioctl_data_write)
-
-#endif /* _HOST_LIB_DRIVER_LINUX_IF_H_ */
static unsigned char __nosavedata edid_checkvalue[4] = {0};
static unsigned int hdmitx_edid_check_valid_blocks(unsigned char *buf);
static void Edid_DTD_parsing(struct rx_cap *pRXCap, unsigned char *data);
+static void hdmitx_edid_set_default_aud(struct hdmitx_dev *hdev);
static void edid_save_checkvalue(unsigned char *buf, unsigned int block_cnt)
{
return ret;
}
-static void Edid_ReceiverBrandNameParse(struct rx_cap *pRxCap,
+static void Edid_ParsingIDManufacturerName(struct rx_cap *pRxCap,
unsigned char *data)
{
int i;
brand[2] = data[1] & 0x1f;
for (i = 0; i < 3; i++)
- pRxCap->ReceiverBrandName[i] = uppercase[brand[i] - 1];
+ pRxCap->IDManufacturerName[i] = uppercase[brand[i] - 1];
+}
+
+static void Edid_ParsingIDProductCode(struct rx_cap *pRXCap,
+ unsigned char *data)
+{
+ if (data == NULL)
+ return;
+ pRXCap->IDProductCode[0] = data[1];
+ pRXCap->IDProductCode[1] = data[0];
+}
+
+static void Edid_ParsingIDSerialNumber(struct rx_cap *pRXCap,
+ unsigned char *data)
+{
+ int i;
+
+ if (data == NULL)
+ return;
+ for (i = 0; i < 4; i++)
+ pRXCap->IDSerialNumber[i] = data[3-i];
+ return;
}
static int Edid_find_name_block(unsigned char *data)
}
set_vsdb_phy_addr(hdev, &info->vsdb_phy_addr, &buff[BlockAddr]);
- if ((check_fbc_special(&hdev->EDID_buf[0])) ||
- (check_fbc_special(&hdev->EDID_buf1[0])))
- rx_edid_physical_addr(0, 0, 0, 0);
- else
- rx_edid_physical_addr(info->vsdb_phy_addr.a,
- info->vsdb_phy_addr.b,
- info->vsdb_phy_addr.c,
- info->vsdb_phy_addr.d);
+ if (hdev->repeater_tx) {
+ if ((check_fbc_special(&hdev->EDID_buf[0])) ||
+ (check_fbc_special(&hdev->EDID_buf1[0])))
+ rx_edid_physical_addr(0, 0, 0, 0);
+ else
+ rx_edid_physical_addr(info->vsdb_phy_addr.a,
+ info->vsdb_phy_addr.b,
+ info->vsdb_phy_addr.c,
+ info->vsdb_phy_addr.d);
+ }
set_vsdb_dc_cap(&hdev->RXCap, &buff[BlockAddr]);
if (temp_addr >= VSpecificBoundary)
{
if (edid_flag & 0x80)
info->support_underscan_flag = 1;
- if (edid_flag & 0x40)
+ if (edid_flag & 0x40) {
+ struct hdmitx_dev *hdev =
+ container_of(info, struct hdmitx_dev, hdmi_info);
info->support_basic_audio_flag = 1;
+ hdmitx_edid_set_default_aud(hdev);
+ }
if (edid_flag & 0x20)
info->support_ycbcr444_flag = 1;
if (edid_flag & 0x10)
len = dat[pos] & 0x1f;
pos++;
- if (dat[pos] == 1)
- pos++;
- else {
+ if (dat[pos] != 1) {
pr_info("hdmitx: edid: parsing fail %s[%d]\n", __func__,
__LINE__);
return;
- }
+ } else
+ pos++;
dv->ieeeoui = dat[pos++];
dv->ieeeoui += dat[pos++] << 8;
int i, tmp, idx;
unsigned char *vfpdb_offset = NULL;
struct rx_cap *pRXCap = &(hdmitx_device->RXCap);
+ unsigned int aud_flag = 0;
if (BlockBuf[0] != 0x02)
return -1; /* not a CEA BLOCK. */
pRXCap->native_Mode = BlockBuf[3];
pRXCap->number_of_dtd += BlockBuf[3] & 0xf;
- pRXCap->VIC_count = 0;
pRXCap->native_VIC = 0xff;
+ pRXCap->AUD_count = 0;
Edid_Y420CMDB_Reset(&(hdmitx_device->hdmi_info));
count = BlockBuf[offset] & 0x1f;
switch (tag) {
case HDMI_EDID_BLOCK_TYPE_AUDIO:
- pRXCap->AUD_count = count/3;
+ aud_flag = 1;
+ tmp = count / 3;
+ idx = pRXCap->AUD_count;
+ pRXCap->AUD_count += tmp;
offset++;
- for (i = 0 ; i < pRXCap->AUD_count ; i++) {
- pRXCap->RxAudioCap[i].audio_format_code =
+ for (i = 0 ; i < tmp; i++) {
+ pRXCap->RxAudioCap[idx + i].audio_format_code =
(BlockBuf[offset + i * 3]>>3)&0xf;
- pRXCap->RxAudioCap[i].channel_num_max =
+ pRXCap->RxAudioCap[idx + i].channel_num_max =
BlockBuf[offset + i * 3]&0x7;
- pRXCap->RxAudioCap[i].freq_cc =
+ pRXCap->RxAudioCap[idx + i].freq_cc =
BlockBuf[offset + i * 3 + 1]&0x7f;
- pRXCap->RxAudioCap[i].cc3 =
+ pRXCap->RxAudioCap[idx + i].cc3 =
BlockBuf[offset + i * 3 + 2]&0x7;
}
offset += count;
}
}
+ if (aud_flag == 0)
+ hdmitx_edid_set_default_aud(hdmitx_device);
+
Edid_Y420CMDB_PostProcess(hdmitx_device);
hdmitx_device->vic_count = pRXCap->VIC_count;
return 0;
}
+static void hdmitx_edid_set_default_aud(struct hdmitx_dev *hdev)
+{
+ struct rx_cap *pRXCap = &(hdev->RXCap);
+
+ /* if AUD_count not equal to 0, no need default value */
+ if (pRXCap->AUD_count)
+ return;
+
+ pRXCap->AUD_count = 1;
+ pRXCap->RxAudioCap[0].audio_format_code = 1; /* PCM */
+ pRXCap->RxAudioCap[0].channel_num_max = 1; /* 2ch */
+ pRXCap->RxAudioCap[0].freq_cc = 7; /* 32/44.1/48 kHz */
+ pRXCap->RxAudioCap[0].cc3 = 7; /* 16/20/24 bit */
+}
+
/* add default VICs for DVI case */
static void hdmitx_edid_set_default_vic(struct hdmitx_dev *hdmitx_device)
{
return 0;
/* check block 1 extension tag */
- if (buf[0x80] != 0x2)
+ if (!((buf[0x80] == 0x2) || (buf[0x80] == 0xf0)))
return 0;
/* check block 1 checksum */
if (buf[0x7e] == 0)/* check Extension flag at block 0 */
return 1;
- else if (buf[0x80] != 0x2)/* check block 1 extension tag */
+ /* check block 1 extension tag */
+ else if (!((buf[0x80] == 0x2) || (buf[0x80] == 0xf0)))
return 0;
/* check block 1 checksum */
pRxCap->edid_revision = (data[1] < 0x5)?data[1]:0;
}
+static void Edid_PhyscialSizeParse(struct rx_cap *pRxCap,
+ unsigned char *data)
+{
+ if ((data[0] != 0) && (data[1] != 0)) {
+ pRxCap->physcial_weight = data[0];
+ pRxCap->physcial_height = data[1];
+ }
+}
+
/* if edid block 0 are all zeros, then consider RX as HDMI device */
static int edid_zero_data(unsigned char *buf)
{
/* return -1 ; */
}
- Edid_ReceiverBrandNameParse(&hdmitx_device->RXCap, &EDID_buf[8]);
-
+ Edid_ParsingIDManufacturerName(&hdmitx_device->RXCap, &EDID_buf[8]);
+ Edid_ParsingIDProductCode(&hdmitx_device->RXCap, &EDID_buf[0x0A]);
+ Edid_ParsingIDSerialNumber(&hdmitx_device->RXCap, &EDID_buf[0x0C]);
idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS;
idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS;
idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS;
Edid_VersionParse(&hdmitx_device->RXCap, &EDID_buf[18]);
+ Edid_PhyscialSizeParse(&hdmitx_device->RXCap, &EDID_buf[21]);
+
Edid_DecodeStandardTiming(&hdmitx_device->hdmi_info, &EDID_buf[26], 8);
Edid_ParseCEADetailedTimingDescriptors(&hdmitx_device->hdmi_info,
4, 0x36, &EDID_buf[0]);
}
}
- if (EDID_buf[i*128+0] == 0x2) {
- if (hdmitx_edid_block_parse(hdmitx_device,
- &(EDID_buf[i*128])) >= 0) {
- if (hdmitx_device->RXCap.IEEEOUI == 0x0c03)
- break;
- }
- }
+ hdmitx_edid_block_parse(hdmitx_device, &(EDID_buf[i*128]));
}
/*
if (edid_zero_data(EDID_buf))
pRXCap->IEEEOUI = 0x0c03;
+ if ((!pRXCap->AUD_count) && (!pRXCap->IEEEOUI))
+ hdmitx_edid_set_default_aud(hdmitx_device);
+
edid_save_checkvalue(EDID_buf, BlockCount+1);
#if 1
/* update RX HDR information */
info = get_current_vinfo();
if (info) {
- info->hdr_info.hdr_support = (pRXCap->hdr_sup_eotf_sdr << 0)
- | (pRXCap->hdr_sup_eotf_hdr << 1)
- | (pRXCap->hdr_sup_eotf_smpte_st_2084 << 2);
- info->hdr_info.lumi_max = pRXCap->hdr_lum_max;
- info->hdr_info.lumi_avg = pRXCap->hdr_lum_avg;
- info->hdr_info.lumi_min = pRXCap->hdr_lum_min;
- pr_info("hdmitx: update RX hdr info %x\n",
- info->hdr_info.hdr_support);
+ if (!((strncmp(info->name, "480cvbs", 7) == 0) ||
+ (strncmp(info->name, "576cvbs", 7) == 0) ||
+ (strncmp(info->name, "null", 4) == 0))) {
+ info->hdr_info.hdr_support =
+ (pRXCap->hdr_sup_eotf_sdr << 0) |
+ (pRXCap->hdr_sup_eotf_hdr << 1) |
+ (pRXCap->hdr_sup_eotf_smpte_st_2084 << 2);
+ info->hdr_info.lumi_max = pRXCap->hdr_lum_max;
+ info->hdr_info.lumi_avg = pRXCap->hdr_lum_avg;
+ info->hdr_info.lumi_min = pRXCap->hdr_lum_min;
+ pr_info("hdmitx: update rx hdr info %x at edid parsing\n",
+ info->hdr_info.hdr_support);
+ }
}
return 0;
}
static struct dispmode_vic dispmode_vic_tab[] = {
- {"480i60hz", HDMI_480i60_16x9},
- {"480p60hz", HDMI_480p60_16x9},
- {"576i50hz", HDMI_576i50_16x9},
- {"576p50hz", HDMI_576p50_16x9},
- {"720p50hz", HDMI_720p50},
- {"720p60hz", HDMI_720p60},
+ {"480i60hz", HDMI_480i60_16x9},
+ {"480p60hz", HDMI_480p60_16x9},
+ {"576i50hz", HDMI_576i50_16x9},
+ {"576p50hz", HDMI_576p50_16x9},
+ {"720p50hz", HDMI_720p50},
+ {"720p60hz", HDMI_720p60},
{"1080i50hz", HDMI_1080i50},
- {"1080i60hz", HDMI_1080i60},
+ {"1080i60hz", HDMI_1080i60},
{"1080p50hz", HDMI_1080p50},
{"1080p30hz", HDMI_1080p30},
{"1080p25hz", HDMI_1080p25},
{"1080p24hz", HDMI_1080p24},
- {"1080p60hz", HDMI_1080p60},
- {"2160p30hz", HDMI_4k2k_30},
- {"2160p25hz", HDMI_4k2k_25},
- {"2160p24hz", HDMI_4k2k_24},
+ {"1080p60hz", HDMI_1080p60},
+ {"2160p30hz", HDMI_4k2k_30},
+ {"2160p25hz", HDMI_4k2k_25},
+ {"2160p24hz", HDMI_4k2k_24},
{"smpte24hz", HDMI_4k2k_smpte_24},
{"smpte25hz", HDMI_4096x2160p25_256x135},
{"smpte30hz", HDMI_4096x2160p30_256x135},
unsigned int calc_tmds_clk = 0;
int i = 0;
int svd_flag = 0;
+ /* Default max color depth is 24 bit */
+ enum hdmi_color_depth rx_y444_max_dc = COLORDEPTH_24B;
+ enum hdmi_color_depth rx_y422_max_dc = COLORDEPTH_24B;
+ enum hdmi_color_depth rx_y420_max_dc = COLORDEPTH_24B;
+ enum hdmi_color_depth rx_rgb_max_dc = COLORDEPTH_24B;
if (!hdev || !para)
return 0;
if (calc_tmds_clk < rx_max_tmds_clk)
valid = 1;
else
- valid = 0;
+ return 0;
+
+ if (para->cs == COLORSPACE_YUV444) {
+ /* Rx may not support Y444 */
+ if (!(pRXCap->native_Mode & (1 << 5)))
+ return 0;
+ if (pRXCap->dc_y444 && pRXCap->dc_30bit)
+ rx_y444_max_dc = COLORDEPTH_30B;
+ if (para->cd <= rx_y444_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+ if (para->cs == COLORSPACE_YUV422) {
+ /* Rx may not support Y422 */
+ if (!(pRXCap->native_Mode & (1 << 4)))
+ return 0;
+ if (pRXCap->dc_y444 && pRXCap->dc_30bit)
+ rx_y422_max_dc = COLORDEPTH_30B;
+ if (para->cd <= rx_y422_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+ if (para->cs == COLORSPACE_RGB444) {
+ /* Always assume RX supports RGB444 */
+ if (pRXCap->dc_30bit)
+ rx_rgb_max_dc = COLORDEPTH_30B;
+ if (para->cd <= rx_rgb_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+ if (para->cs == COLORSPACE_YUV420) {
+ if (pRXCap->dc_30bit_420)
+ rx_y420_max_dc = COLORDEPTH_30B;
+ if (para->cd <= rx_y420_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
return valid;
}
{
struct rx_cap *pRXCap = &(hdmitx_device->RXCap);
- return hdmitx_edid_vic_tab_map_string(pRXCap->native_VIC);
+ return hdmitx_edid_vic_to_string(pRXCap->native_VIC);
}
/* Clear HDMI Hardware Module EDID RAM and EDID Buffer */
memset(&hdmitx_device->EDID_hash[0], 0,
sizeof(hdmitx_device->EDID_hash));
hdmitx_device->edid_parsing = 0;
+ hdmitx_edid_set_default_aud(hdmitx_device);
}
/*
struct rx_cap *pRXCap = &(hdmitx_device->RXCap);
pos += snprintf(buffer+pos, buffer_len-pos,
- "Rx Brand Name: %s\n", pRXCap->ReceiverBrandName);
+ "Rx Manufacturer Name: %s\n", pRXCap->IDManufacturerName);
+ pos += snprintf(buffer+pos, buffer_len-pos,
+ "Rx Product Code: %02x%02x\n",
+ pRXCap->IDProductCode[0],
+ pRXCap->IDProductCode[1]);
+ pos += snprintf(buffer+pos, buffer_len-pos,
+ "Rx Serial Number: %02x%02x%02x%02x\n",
+ pRXCap->IDSerialNumber[0],
+ pRXCap->IDSerialNumber[1],
+ pRXCap->IDSerialNumber[2],
+ pRXCap->IDSerialNumber[3]);
pos += snprintf(buffer+pos, buffer_len-pos,
"Rx Product Name: %s\n", pRXCap->ReceiverProductName);
"Manufacture Year: %d\n", pRXCap->manufacture_year+1990);
pos += snprintf(buffer+pos, buffer_len-pos,
+ "Physcial size(cm): %d x %d\n",
+ pRXCap->physcial_weight, pRXCap->physcial_height);
+
+ pos += snprintf(buffer+pos, buffer_len-pos,
"EDID Version: %d.%d\n",
pRXCap->edid_version, pRXCap->edid_revision);
}
pos += snprintf(buffer+pos, buffer_len-pos,
"Speaker Allocation: %x\n", pRXCap->RxSpeakerAllocation);
- pos += snprintf(buffer+pos, buffer_len-pos, "Vendor: 0x%x\n",
- pRXCap->IEEEOUI);
+ pos += snprintf(buffer+pos, buffer_len-pos,
+ "Vendor: 0x%x ( %s device)\n",
+ pRXCap->IEEEOUI, (pRXCap->IEEEOUI)?"HDMI":"DVI");
pos += snprintf(buffer+pos, buffer_len-pos,
"MaxTMDSClock1 %d MHz\n", pRXCap->Max_TMDS_Clock1 * 5);
* version 1.1
*/
-/* android ics switch device */
-static struct extcon_dev hdcp_dev = {
- .name = "hdcp",
-};
-
-/* For most cases, we don't use HDCP
- * If using HDCP, need add follow command in boot/init.rc and
- * recovery/boot/init.rc
- * write /sys/module/hdmitx/parameters/hdmi_output_force 0
- */
-static int hdmi_output_force = 1;
+
static int hdmi_authenticated;
-static int hdmi_hdcp_process = 1;
/* Notic: the HDCP key setting has been moved to uboot
* On MBX project, it is too late for HDCP get from
return one_num == 20;
}
-static struct timer_list hdcp_monitor_timer;
-static void hdcp_monitor_func(unsigned long arg)
+static void _hdcp_do_work(struct work_struct *work)
{
- /* static int hdcp_auth_flag = 0; */
- struct hdmitx_dev *hdev = (struct hdmitx_dev *)hdcp_monitor_timer.data;
-
- if ((hdev->HWOp.Cntl) && (hdev->log & (HDMI_LOG_HDCP)))
- hdev->HWOp.Cntl(hdev, HDMITX_HDCP_MONITOR, 1);
+ struct hdmitx_dev *hdev =
+ container_of(work, struct hdmitx_dev, work_do_hdcp.work);
+
+ if (hdev->hdcp_mode == 2) {
+ /* hdev->HWOp.CntlMisc(hdev, MISC_HDCP_CLKDIS, 1); */
+ /* schedule_delayed_work(&hdev->work_do_hdcp, HZ / 50); */
+ } else
+ hdev->HWOp.CntlMisc(hdev, MISC_HDCP_CLKDIS, 0);
+}
- mod_timer(&hdcp_monitor_timer, jiffies + 2 * HZ);
+void hdmitx_hdcp_do_work(struct hdmitx_dev *hdev)
+{
+ _hdcp_do_work(&hdev->work_do_hdcp.work);
}
static int hdmitx_hdcp_task(void *data)
{
struct hdmitx_dev *hdev = (struct hdmitx_dev *)data;
- init_timer(&hdcp_monitor_timer);
- hdcp_monitor_timer.data = (ulong) data;
- hdcp_monitor_timer.function = hdcp_monitor_func;
- hdcp_monitor_timer.expires = jiffies + HZ;
- add_timer(&hdcp_monitor_timer);
-
+ INIT_DELAYED_WORK(&hdev->work_do_hdcp, _hdcp_do_work);
while (hdev->hpd_event != 0xff) {
hdmi_authenticated = hdev->HWOp.CntlDDC(hdev,
DDC_HDCP_GET_AUTH, 0);
- extcon_set_state(&hdcp_dev, 0, hdmi_authenticated); //TO_DO___49
+ hdmitx_hdcp_status(hdmi_authenticated);
msleep_interruptible(200);
}
{
struct hdmitx_dev *hdev = get_hdmitx_device();
- hdmi_print(IMP, SYS "hdmitx_hdcp_init\n");
+ pr_info("hdmitx_hdcp_init\n");
if (hdev->hdtx_dev == NULL) {
hdmi_print(IMP, SYS "exit for null device of hdmitx!\n");
return -ENODEV;
}
- extcon_dev_register(&hdcp_dev);
-
hdev->task_hdcp = kthread_run(hdmitx_hdcp_task, (void *)hdev,
"kthread_hdcp");
static void __exit hdmitx_hdcp_exit(void)
{
- extcon_dev_unregister(&hdcp_dev);
+ struct hdmitx_dev *hdev = get_hdmitx_device();
+
+ if (hdev)
+ cancel_delayed_work_sync(&hdev->work_do_hdcp);
}
MODULE_PARM_DESC(hdmi_authenticated, "\n hdmi_authenticated\n");
module_param(hdmi_authenticated, int, 0444);
-MODULE_PARM_DESC(hdmi_hdcp_process, "\n hdmi_hdcp_process\n");
-module_param(hdmi_hdcp_process, int, 0664);
-
-MODULE_PARM_DESC(hdmi_output_force, "\n hdmi_output_force\n");
-module_param(hdmi_output_force, int, 0664);
-
-
module_init(hdmitx_hdcp_init);
module_exit(hdmitx_hdcp_exit);
MODULE_DESCRIPTION("AMLOGIC HDMI TX HDCP driver");
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/reboot.h>
+#include <linux/extcon.h>
#include <linux/amlogic/cpu_version.h>
#include <linux/amlogic/media/vout/vinfo.h>
static int check_fbc_special(unsigned char *edid_dat);
static int hdcp_tst_sig;
static DEFINE_MUTEX(setclk_mutex);
+static atomic_t kref_audio_mute;
+static atomic_t kref_video_mute;
static char fmt_attr[16];
#ifndef CONFIG_AMLOGIC_VOUT
struct hdmi_config_platform_data *hdmi_pdata;
-static struct hdmitx_dev hdmitx_device;
-static struct extcon_dev sdev = { /* android ics switch device */
- .name = "hdmi",
-};
-static struct extcon_dev hdmi_audio = {
- .name = "hdmi_audio",
-};
-static struct extcon_dev hdmi_power = { /* android ics switch device */
- .name = "hdmi_power",
-};
-static struct extcon_dev hdmi_hdr = {
- .name = "hdmi_hdr",
+static const unsigned int hdmi_cable[] = {
+ EXTCON_DISP_HDMI,
+ EXTCON_NONE,
};
+static struct hdmitx_dev hdmitx_device;
+struct extcon_dev *hdmitx_extcon_hdmi;
+struct extcon_dev *hdmitx_excton_audio;
+struct extcon_dev *hdmitx_excton_power;
+struct extcon_dev *hdmitx_excton_hdr;
+struct extcon_dev *hdmitx_excton_rxsense;
+struct extcon_dev *hdmitx_excton_hdcp;
+
static int hdmi_init;
static inline void hdmitx_notify_hpd(int hpd)
if (info && (strncmp(info->name, "panel", 5) == 0
|| strncmp(info->name, "null", 4) == 0))
return;
+
phdmi->hpd_lock = 1;
- hdcp_tst_sig = 1;
- pr_info("%s[%d] set hdcp_pwr as %d\n", __func__, __LINE__,
- hdcp_tst_sig);
msleep(20);
phdmi->HWOp.CntlMisc(phdmi, MISC_AVMUTE_OP, SET_AVMUTE);
mdelay(100);
phdmi->output_blank_flag = 0;
phdmi->HWOp.CntlDDC(phdmi, DDC_HDCP_MUX_INIT, 1);
phdmi->HWOp.CntlDDC(phdmi, DDC_HDCP_OP, HDCP14_OFF);
- extcon_set_state(&hdmi_power, 0, 0);
+ extcon_set_state_sync(hdmitx_excton_power, EXTCON_DISP_HDMI, 0);
phdmi->HWOp.CntlConfig(&hdmitx_device, CONF_CLR_AVI_PACKET, 0);
phdmi->HWOp.CntlConfig(&hdmitx_device, CONF_CLR_VSDB_PACKET, 0);
}
hdmitx_device.HWOp.CntlConfig(&hdmitx_device,
CONF_VIDEO_BLANK_OP, VIDEO_UNBLANK);
return;
+ } else {
+ hdmitx_device.HWOp.CntlConfig(&hdmitx_device,
+ CONF_VIDEO_BLANK_OP, VIDEO_BLANK);
}
- hdmitx_device.HWOp.CntlConfig(&hdmitx_device, CONF_VIDEO_BLANK_OP,
- VIDEO_BLANK);
if (hdmitx_is_hdmi_vmode(info->name) == 1)
phdmi->HWOp.CntlMisc(&hdmitx_device, MISC_HPLL_FAKE, 0);
hdmitx_device.HWOp.CntlConfig(&hdmitx_device,
CONF_AUDIO_MUTE_OP, AUDIO_MUTE);
set_disp_mode_auto();
- extcon_set_state(&sdev, 0, hdmitx_device.hpd_state);
- extcon_set_state(&hdmi_power, 0, hdmitx_device.hpd_state);
+
+ extcon_set_state_sync(hdmitx_extcon_hdmi, EXTCON_DISP_HDMI,
+ hdmitx_device.hpd_state);
+ extcon_set_state_sync(hdmitx_excton_power, EXTCON_DISP_HDMI,
+ hdmitx_device.hpd_state);
+
pr_info("amhdmitx: late resume module %d\n", __LINE__);
phdmi->HWOp.Cntl((struct hdmitx_dev *)h->param,
HDMITX_EARLY_SUSPEND_RESUME_CNTL, HDMITX_LATE_RESUME);
hdmi_print(INF, SYS "late resume\n");
}
-static struct early_suspend hdmitx_early_suspend_handler = {
- .level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 10,
- .suspend = hdmitx_early_suspend,
- .resume = hdmitx_late_resume,
- .param = &hdmitx_device,
-};
-#endif
-
/* Set avmute_set signal to HDMIRX */
static int hdmitx_reboot_notifier(struct notifier_block *nb,
unsigned long action, void *data)
return NOTIFY_OK;
}
+static struct early_suspend hdmitx_early_suspend_handler = {
+ .level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 10,
+ .suspend = hdmitx_early_suspend,
+ .resume = hdmitx_late_resume,
+ .param = &hdmitx_device,
+};
+#endif
+
/* static struct hdmitx_info hdmi_info; */
#define INIT_FLAG_VDACOFF 0x1
/* unplug powerdown */
}
}
+static void hdmi_physcial_size_update(struct vinfo_s *info,
+ struct hdmitx_dev *hdev)
+{
+ unsigned int width, height;
+
+ if (info == NULL) {
+ hdmi_print(ERR, VID "cann't get valid mode\n");
+ return;
+ }
+
+ width = hdev->RXCap.physcial_weight;
+ height = hdev->RXCap.physcial_height;
+ if ((width == 0) || (height == 0)) {
+ info->screen_real_width = info->aspect_ratio_num;
+ info->screen_real_height = info->aspect_ratio_den;
+ } else {
+ info->screen_real_width = width * 10; /* transfer mm */
+ info->screen_real_height = height * 10; /* transfer mm */
+ }
+ pr_info("hdmitx: update physcial size: %d %d\n",
+ info->screen_real_width, info->screen_real_height);
+}
+
static int set_disp_mode_auto(void)
{
int ret = -1;
info->fresh_tx_hdr_pkt = hdmitx_set_drm_pkt;
info->fresh_tx_vsif_pkt = hdmitx_set_vsif_pkt;
info->dv_info = &hdev->RXCap.dv_info;
- info->hdr_info.hdr_support = (hdev->RXCap.hdr_sup_eotf_sdr << 0)
- | (hdev->RXCap.hdr_sup_eotf_hdr << 1)
- | (hdev->RXCap.hdr_sup_eotf_smpte_st_2084 << 2);
- info->hdr_info.lumi_max = hdev->RXCap.hdr_lum_max;
- info->hdr_info.lumi_avg = hdev->RXCap.hdr_lum_avg;
- info->hdr_info.lumi_min = hdev->RXCap.hdr_lum_min;
- pr_info("hdmitx: update rx hdr info %x\n",
- info->hdr_info.hdr_support);
+ if (!((strncmp(info->name, "480cvbs", 7) == 0) ||
+ (strncmp(info->name, "576cvbs", 7) == 0) ||
+ (strncmp(info->name, "null", 4) == 0))) {
+ info->hdr_info.hdr_support = (hdev->RXCap.hdr_sup_eotf_sdr << 0)
+ | (hdev->RXCap.hdr_sup_eotf_hdr << 1)
+ | (hdev->RXCap.hdr_sup_eotf_smpte_st_2084 << 2);
+ info->hdr_info.lumi_max = hdev->RXCap.hdr_lum_max;
+ info->hdr_info.lumi_avg = hdev->RXCap.hdr_lum_avg;
+ info->hdr_info.lumi_min = hdev->RXCap.hdr_lum_min;
+ pr_info("hdmitx: update rx hdr info %x\n",
+ info->hdr_info.hdr_support);
+ }
+ hdmi_physcial_size_update(info, hdev);
/* If info->name equals to cvbs, then set mode to I mode to hdmi
*/
if ((strncmp(info->name, "480cvbs", 7) == 0) ||
(strncmp(info->name, "576cvbs", 7) == 0) ||
+ (strncmp(info->name, "ntsc_m", 6) == 0) ||
+ (strncmp(info->name, "pal_m", 5) == 0) ||
+ (strncmp(info->name, "pal_n", 5) == 0) ||
(strncmp(info->name, "panel", 5) == 0) ||
(strncmp(info->name, "null", 4) == 0)) {
hdmi_print(ERR, VID "%s not valid hdmi mode\n", info->name);
}
hdmitx_set_audio(hdev, &(hdev->cur_audio_param), hdmi_ch);
hdev->output_blank_flag = 1;
- if (hdev->hdcp_mode == 1) {
- hdev->HWOp.CntlDDC(hdev, DDC_HDCP_MUX_INIT, 1);
- hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP14_ON);
- }
- if (hdev->hdcp_mode == 2) {
- hdev->HWOp.CntlDDC(hdev, DDC_HDCP_MUX_INIT, 2);
- hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP22_ON);
- }
hdev->ready = 1;
return ret;
}
* edid_parsing attr
* If RX edid data are all correct, HEAD(00 ff ff ff ff ff ff 00), checksum,
* version, etc), then return "ok". Otherwise, "ng"
+ * Actually, in some old televisions, EDID is stored in EEPROM.
+ * some bits in EEPROM may reverse with time.
+ * But it does not affect edid_parsing.
+ * Therefore, we consider the RX edid data are all correct, return "OK"
*/
static ssize_t show_edid_parsing(struct device *dev,
struct device_attribute *attr, char *buf)
{
int pos = 0;
+
+ pos += snprintf(buf+pos, PAGE_SIZE, "ok\n");
+ return pos;
+}
+
+/*
+ * sink_type attr
+ * sink, or repeater
+ */
+static ssize_t show_sink_type(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int pos = 0;
struct hdmitx_dev *hdev = &hdmitx_device;
- if (hdev->edid_parsing)
- pos += snprintf(buf+pos, PAGE_SIZE, "ok\n");
+ if (!hdev->hpd_state) {
+ pos += snprintf(buf+pos, PAGE_SIZE, "none\n");
+ return pos;
+ }
+
+ if (hdev->hdmi_info.vsdb_phy_addr.b)
+ pos += snprintf(buf+pos, PAGE_SIZE, "repeater\n");
else
- pos += snprintf(buf+pos, PAGE_SIZE, "ng\n");
+ pos += snprintf(buf+pos, PAGE_SIZE, "sink\n");
+
+ return pos;
+}
+
+/*
+ * hdcp_repeater attr
+ * For hdcp 22, hdcp_tx22 will write to store_hdcp_repeater
+ * For hdcp 14, directly get bcaps bit
+ */
+static ssize_t show_hdcp_repeater(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int pos = 0;
+ struct hdmitx_dev *hdev = &hdmitx_device;
+
+ if (hdev->hdcp_mode == 1)
+ hdev->hdcp_bcaps_repeater = hdev->HWOp.CntlDDC(hdev,
+ DDC_HDCP14_GET_BCAPS_RP, 0);
+
+ pos += snprintf(buf+pos, PAGE_SIZE, "%d\n", hdev->hdcp_bcaps_repeater);
+
+ return pos;
+}
+
+static ssize_t store_hdcp_repeater(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct hdmitx_dev *hdev = &hdmitx_device;
+
+ if (hdev->hdcp_mode == 2)
+ hdev->hdcp_bcaps_repeater = (buf[0] == '1');
+
+ return count;
+}
+
+/*
+ * hdcp22_type attr
+ */
+static bool hdcp22_type;
+static ssize_t show_hdcp22_type(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int pos = 0;
+
+ pos += snprintf(buf+pos, PAGE_SIZE, "%d\n", hdcp22_type);
+
+ return pos;
+}
+
+static ssize_t store_hdcp22_type(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ if (buf[0] == '0')
+ hdcp22_type = 0;
+ if (buf[0] == '1')
+ hdcp22_type = 1;
+
+ return count;
+}
+
+static ssize_t show_hdcp22_base(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int pos = 0;
+
+ pos += snprintf(buf+pos, PAGE_SIZE, "0x%x\n", get_hdcp22_base());
return pos;
}
}
EXPORT_SYMBOL(hdmitx_audio_mute_op);
+void hdmitx_video_mute_op(unsigned int flag)
+{
+ if (flag == 0)
+ hdmitx_device.HWOp.CntlConfig(&hdmitx_device,
+ CONF_VIDEO_MUTE_OP, VIDEO_MUTE);
+ else
+ hdmitx_device.HWOp.CntlConfig(&hdmitx_device,
+ CONF_VIDEO_MUTE_OP, VIDEO_UNMUTE);
+}
+EXPORT_SYMBOL(hdmitx_video_mute_op);
+
static void hdr_work_func(struct work_struct *work)
{
struct hdmitx_dev *hdev =
return 16;
}
+static ssize_t show_aud_mute(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int pos = 0;
+
+ pos += snprintf(buf+pos, PAGE_SIZE, "%d\n",
+ atomic_read(&kref_audio_mute));
+ return pos;
+}
+
+static ssize_t store_aud_mute(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ if (buf[0] == '1') {
+ atomic_inc(&kref_audio_mute);
+ if (atomic_read(&kref_audio_mute) == 1)
+ hdmitx_audio_mute_op(0);
+ }
+ if (buf[0] == '0') {
+ if (!(atomic_sub_and_test(0, &kref_audio_mute))) {
+ atomic_dec(&kref_audio_mute);
+ if (atomic_sub_and_test(0, &kref_audio_mute))
+ hdmitx_audio_mute_op(1);
+ }
+ }
+
+ return count;
+}
+
+static ssize_t show_vid_mute(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int pos = 0;
+
+ pos += snprintf(buf+pos, PAGE_SIZE, "%d\n",
+ atomic_read(&kref_video_mute));
+ return pos;
+}
+
+static ssize_t store_vid_mute(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ if (buf[0] == '1') {
+ atomic_inc(&kref_video_mute);
+ if (atomic_read(&kref_video_mute) == 1)
+ hdmitx_video_mute_op(0);
+ }
+ if (buf[0] == '0') {
+ if (!(atomic_sub_and_test(0, &kref_video_mute))) {
+ atomic_dec(&kref_video_mute);
+ if (atomic_sub_and_test(0, &kref_video_mute))
+ hdmitx_video_mute_op(1);
+ }
+ }
+
+ return count;
+}
static ssize_t store_debug(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
pos += snprintf(buf+pos, PAGE_SIZE, "3D support lists:\n");
for (i = 0; disp_mode_t[i]; i++) {
+ /* 3D is not supported under 4k modes */
if (strstr(disp_mode_t[i], "2160p") ||
strstr(disp_mode_t[i], "smpte"))
continue;
"FramePacking ");
}
if (hdmitx_device.RXCap.support_3d_format[
- hdmitx_device.RXCap.VIC[j]].top_and_bottom == 1){
+ hdmitx_device.RXCap.VIC[j]].top_and_bottom == 1) {
pos += snprintf(buf+pos, PAGE_SIZE,
"TopBottom ");
}
aud_coding_type[pRXCap->RxAudioCap[i].
audio_format_code],
pRXCap->RxAudioCap[i].channel_num_max + 1);
- for (j = 0; j < 7; j++) {
- if (pRXCap->RxAudioCap[i].freq_cc & (1 << j))
- pos += snprintf(buf + pos, PAGE_SIZE, "%s/",
- aud_sampling_frequency[j+1]);
- }
- pos += snprintf(buf + pos - 1, PAGE_SIZE, " kHz, ");
- for (j = 0; j < 3; j++) {
- if (pRXCap->RxAudioCap[i].cc3 & (1 << j))
- pos += snprintf(buf + pos, PAGE_SIZE, "%s/",
- aud_sample_size[j+1]);
- }
- pos += snprintf(buf + pos - 1, PAGE_SIZE, " bit\n");
+ for (j = 0; j < 7; j++) {
+ if (pRXCap->RxAudioCap[i].freq_cc & (1 << j))
+ pos += snprintf(buf + pos, PAGE_SIZE, "%s/",
+ aud_sampling_frequency[j+1]);
+ }
+ pos += snprintf(buf + pos - 1, PAGE_SIZE, " kHz, ");
+ for (j = 0; j < 3; j++) {
+ if (pRXCap->RxAudioCap[i].cc3 & (1 << j))
+ pos += snprintf(buf + pos, PAGE_SIZE, "%s/",
+ aud_sample_size[j+1]);
+ }
+ pos += snprintf(buf + pos - 1, PAGE_SIZE, " bit\n");
}
return pos;
static bool valid_mode;
static char cvalid_mode[32];
+
+static bool pre_process_str(char *name)
+{
+ int i;
+ unsigned int flag = 0;
+ char *color_format[4] = {"444", "422", "420", "rgb"};
+
+ for (i = 0 ; i < 4 ; i++) {
+ if (strstr(name, color_format[i]) != NULL)
+ flag++;
+ }
+ if (flag >= 2)
+ return 0;
+ else
+ return 1;
+}
+
static ssize_t show_valid_mode(struct device *dev,
struct device_attribute *attr, char *buf)
{
int pos = 0;
struct hdmi_format_para *para = NULL;
- if (cvalid_mode[0])
+ if (cvalid_mode[0]) {
+ valid_mode = pre_process_str(cvalid_mode);
+ if (valid_mode == 0) {
+ pos += snprintf(buf + pos, PAGE_SIZE, "%d\n\r",
+ valid_mode);
+ return pos;
+ }
para = hdmi_get_fmt_name(cvalid_mode, cvalid_mode);
+ }
if (para) {
pr_info("sname = %s\n", para->sname);
pr_info("char_clk = %d\n", para->tmds_clk);
return 0;
}
+static ssize_t store_rxsense_policy(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int val = 0;
+
+ if (isdigit(buf[0])) {
+ val = buf[0] - '0';
+ pr_info("hdmitx: set rxsense_policy as %d\n", val);
+ if ((val == 0) || (val == 1))
+ hdmitx_device.rxsense_policy = val;
+ else
+ pr_info("only accept as 0 or 1\n");
+ }
+ if (hdmitx_device.rxsense_policy)
+ queue_delayed_work(hdmitx_device.rxsense_wq,
+ &hdmitx_device.work_rxsense, 0);
+ else
+ cancel_delayed_work(&hdmitx_device.work_rxsense);
+
+
+ return count;
+}
+
+static ssize_t show_rxsense_policy(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int pos = 0;
+
+ pos += snprintf(buf + pos, PAGE_SIZE, "%d\n",
+ hdmitx_device.rxsense_policy);
+
+ return pos;
+}
+
static ssize_t store_frac_rate(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
static ssize_t store_hdcp_clkdis(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
- pr_info("set hdcp clkdis: %s\n", buf);
-
hdmitx_device.HWOp.CntlMisc(&hdmitx_device, MISC_HDCP_CLKDIS,
- (buf[0] == '1') ? 1 : 0);
+ buf[0] == '1' ? 1 : 0);
return count;
}
static ssize_t store_hdcp_pwr(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
- if (buf[0] == '1') {
- hdcp_tst_sig = 1;
- pr_info("%s[%d] set hdcp_pwr as %d\n", __func__, __LINE__,
- hdcp_tst_sig);
- }
return count;
}
{
int pos = 0;
- pos += snprintf(buf + pos, PAGE_SIZE, "%d\n", !!hdcp_tst_sig);
- if (hdcp_tst_sig == 1) {
- hdcp_tst_sig = 0;
- pr_info("%s[%d] set hdcp_pwr as %d\n", __func__, __LINE__,
- hdcp_tst_sig);
- }
return pos;
}
static ssize_t store_hdcp_byp(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
- hdmitx_device.HWOp.CntlDDC(&hdmitx_device, DDC_HDCP_BYP, 0);
+ hdmitx_device.HWOp.CntlMisc(&hdmitx_device, MISC_HDCP_CLKDIS,
+ buf[0] == '1' ? 1 : 0);
return count;
}
{
pr_info("hdcp: set mode as %s\n", buf);
hdmitx_device.HWOp.CntlDDC(&hdmitx_device, DDC_HDCP_MUX_INIT, 1);
- if (strncmp(buf, "-1", 2) == 0) {
- hdmitx_device.hdcp_mode = -1;
+ if (strncmp(buf, "0", 1) == 0) {
+ hdmitx_device.hdcp_mode = 0;
hdmitx_device.HWOp.CntlDDC(&hdmitx_device,
DDC_HDCP_OP, HDCP14_OFF);
+ hdmitx_hdcp_do_work(&hdmitx_device);
}
- if (strncmp(buf, "0", 1) == 0)
- hdmitx_device.hdcp_mode = 0;
if (strncmp(buf, "1", 1) == 0) {
pr_info("%s[%d]", __func__, __LINE__);
hdmitx_device.hdcp_mode = 1;
+ hdmitx_hdcp_do_work(&hdmitx_device);
hdmitx_device.HWOp.CntlDDC(&hdmitx_device,
DDC_HDCP_OP, HDCP14_ON);
}
if (strncmp(buf, "2", 1) == 0) {
hdmitx_device.hdcp_mode = 2;
+ hdmitx_hdcp_do_work(&hdmitx_device);
hdmitx_device.HWOp.CntlDDC(&hdmitx_device,
DDC_HDCP_MUX_INIT, 2);
}
if (strncmp(buf+4, "22", 2) == 0)
hdmitx_device.HWOp.CntlDDC(&hdmitx_device,
DDC_HDCP_OP, HDCP22_OFF);
+ hdmitx_device.hdcp_mode = 0;
+ hdmitx_hdcp_do_work(&hdmitx_device);
}
return count;
pos += snprintf(buf+pos, PAGE_SIZE, "%d\n\r", hdmi_init);
return pos;
}
+
static ssize_t show_ready(struct device *dev,
struct device_attribute *attr, char *buf)
{
}
}
-static DEVICE_ATTR(disp_mode, 0664,
- show_disp_mode, store_disp_mode);
+static DEVICE_ATTR(disp_mode, 0664, show_disp_mode, store_disp_mode);
static DEVICE_ATTR(attr, 0664, show_attr, store_attr);
-static DEVICE_ATTR(aud_mode, 0644, show_aud_mode,
- store_aud_mode);
+static DEVICE_ATTR(aud_mode, 0644, show_aud_mode, store_aud_mode);
+static DEVICE_ATTR(aud_mute, 0644, show_aud_mute, store_aud_mute);
+static DEVICE_ATTR(vid_mute, 0644, show_vid_mute, store_vid_mute);
static DEVICE_ATTR(edid, 0644, show_edid, store_edid);
static DEVICE_ATTR(rawedid, 0444, show_rawedid, NULL);
+static DEVICE_ATTR(sink_type, 0444, show_sink_type, NULL);
static DEVICE_ATTR(edid_parsing, 0444, show_edid_parsing, NULL);
-static DEVICE_ATTR(config, 0664, show_config,
- store_config);
+static DEVICE_ATTR(config, 0664, show_config, store_config);
static DEVICE_ATTR(debug, 0200, NULL, store_debug);
static DEVICE_ATTR(disp_cap, 0444, show_disp_cap, NULL);
static DEVICE_ATTR(preferred_mode, 0444, show_preferred_mode, NULL);
static DEVICE_ATTR(hdr_cap, 0444, show_hdr_cap, NULL);
static DEVICE_ATTR(dv_cap, 0444, show_dv_cap, NULL);
static DEVICE_ATTR(dc_cap, 0444, show_dc_cap, NULL);
-static DEVICE_ATTR(valid_mode, 0664, show_valid_mode,
- store_valid_mode);
-static DEVICE_ATTR(aud_ch, 0664, show_aud_ch,
- store_aud_ch);
-static DEVICE_ATTR(aud_output_chs, 0664,
- show_aud_output_chs, store_aud_output_chs);
-static DEVICE_ATTR(avmute, 0664, show_avmute,
- store_avmute);
+static DEVICE_ATTR(valid_mode, 0664, show_valid_mode, store_valid_mode);
+static DEVICE_ATTR(aud_ch, 0664, show_aud_ch, store_aud_ch);
+static DEVICE_ATTR(aud_output_chs, 0664, show_aud_output_chs,
+ store_aud_output_chs);
+static DEVICE_ATTR(avmute, 0664, show_avmute, store_avmute);
static DEVICE_ATTR(vic, 0664, show_vic, store_vic);
static DEVICE_ATTR(phy, 0664, show_phy, store_phy);
-static DEVICE_ATTR(frac_rate_policy, 0664,
- show_frac_rate, store_frac_rate);
-static DEVICE_ATTR(hdcp_clkdis, 0664, show_hdcp_clkdis,
- store_hdcp_clkdis);
-static DEVICE_ATTR(hdcp_pwr, 0664, show_hdcp_pwr,
- store_hdcp_pwr);
+static DEVICE_ATTR(frac_rate_policy, 0664, show_frac_rate, store_frac_rate);
+static DEVICE_ATTR(rxsense_policy, 0644, show_rxsense_policy,
+ store_rxsense_policy);
+static DEVICE_ATTR(hdcp_clkdis, 0664, show_hdcp_clkdis, store_hdcp_clkdis);
+static DEVICE_ATTR(hdcp_pwr, 0664, show_hdcp_pwr, store_hdcp_pwr);
static DEVICE_ATTR(hdcp_byp, 0200, NULL, store_hdcp_byp);
-static DEVICE_ATTR(hdcp_mode, 0664, show_hdcp_mode,
- store_hdcp_mode);
-static DEVICE_ATTR(hdcp_lstore, 0664, show_hdcp_lstore,
- store_hdcp_lstore);
+static DEVICE_ATTR(hdcp_mode, 0664, show_hdcp_mode, store_hdcp_mode);
+static DEVICE_ATTR(hdcp_lstore, 0664, show_hdcp_lstore, store_hdcp_lstore);
+static DEVICE_ATTR(hdcp_repeater, 0644, show_hdcp_repeater,
+ store_hdcp_repeater);
+static DEVICE_ATTR(hdcp22_type, 0644, show_hdcp22_type, store_hdcp22_type);
+static DEVICE_ATTR(hdcp22_base, 0444, show_hdcp22_base, NULL);
static DEVICE_ATTR(div40, 0664, show_div40, store_div40);
-static DEVICE_ATTR(hdcp_ctrl, 0664, show_hdcp_ctrl,
- store_hdcp_ctrl);
+static DEVICE_ATTR(hdcp_ctrl, 0664, show_hdcp_ctrl, store_hdcp_ctrl);
static DEVICE_ATTR(disp_cap_3d, 0444, show_disp_cap_3d, NULL);
static DEVICE_ATTR(hdcp_ksv_info, 0444, show_hdcp_ksv_info, NULL);
static DEVICE_ATTR(hdcp_ver, 0444, show_hdcp_ver, NULL);
mutex_unlock(&getedid_mutex);
}
+static int get_downstream_hdcp_ver(void)
+{
+ /* if TX don't have HDCP22 key, skip RX hdcp22 ver */
+ if (hdmitx_device.HWOp.CntlDDC(&hdmitx_device,
+ DDC_HDCP_22_LSTORE, 0) == 0)
+ goto next;
+ if (hdcp_rd_hdcp22_ver())
+ return 22;
+next:
+ /* if (hdcp_rd_hdcp14_ver()) */
+ return 14;
+}
+
+
+static void hdmitx_rxsense_process(struct work_struct *work)
+{
+ int sense;
+ struct hdmitx_dev *hdev = container_of((struct delayed_work *)work,
+ struct hdmitx_dev, work_rxsense);
+
+ sense = hdev->HWOp.CntlMisc(hdev, MISC_TMDS_RXSENSE, 0);
+ extcon_set_state_sync(hdmitx_excton_rxsense, EXTCON_DISP_HDMI, sense);
+ queue_delayed_work(hdev->rxsense_wq, &hdev->work_rxsense, HZ);
+}
+
static void hdmitx_hpd_plugin_handler(struct work_struct *work)
{
char bksv_buf[5];
if (!(hdev->hdmitx_event & (HDMI_TX_HPD_PLUGIN)))
return;
+ if (hdev->rxsense_policy) {
+ cancel_delayed_work(&hdev->work_rxsense);
+ queue_delayed_work(hdev->rxsense_wq, &hdev->work_rxsense, 0);
+ while (!(hdmitx_excton_rxsense->state))
+ msleep_interruptible(1000);
+ }
mutex_lock(&setclk_mutex);
pr_info("hdmitx: plugin\n");
hdev->hdmitx_event &= ~HDMI_TX_HPD_PLUGIN;
/* start reading E-EDID */
- rx_repeat_hpd_state(1);
+ if (hdev->repeater_tx)
+ rx_repeat_hpd_state(1);
hdmitx_get_edid(hdev);
- if (check_fbc_special(&hdev->EDID_buf[0])
- || check_fbc_special(&hdev->EDID_buf1[0]))
- rx_set_repeater_support(0);
- else
- rx_set_repeater_support(1);
- hdev->HWOp.CntlDDC(hdev, DDC_HDCP_GET_BKSV,
- (unsigned long int)bksv_buf);
- rx_set_receive_hdcp(bksv_buf, 1, 1, 0, 0);
+ if (hdev->repeater_tx) {
+ if (check_fbc_special(&hdev->EDID_buf[0])
+ || check_fbc_special(&hdev->EDID_buf1[0]))
+ rx_set_repeater_support(0);
+ else
+ rx_set_repeater_support(1);
+ rx_repeat_hdcp_ver(get_downstream_hdcp_ver());
+ hdev->HWOp.CntlDDC(hdev, DDC_HDCP_GET_BKSV,
+ (unsigned long int)bksv_buf);
+ rx_set_receive_hdcp(bksv_buf, 1, 1, 0, 0);
+ }
set_disp_mode_auto();
hdmitx_set_audio(hdev, &(hdev->cur_audio_param), hdmi_ch);
hdev->hpd_state = 1;
hdmitx_notify_hpd(hdev->hpd_state);
- extcon_set_state(&sdev, 0, 1);
- extcon_set_state(&hdmi_audio, 0, 1);
+
+ extcon_set_state_sync(hdmitx_extcon_hdmi, EXTCON_DISP_HDMI, 1);
+ extcon_set_state_sync(hdmitx_excton_audio, EXTCON_DISP_HDMI, 1);
mutex_unlock(&setclk_mutex);
}
if (!(hdev->hdmitx_event & (HDMI_TX_HPD_PLUGOUT)))
return;
hdev->hdcp_mode = 0;
+ hdev->hdcp_bcaps_repeater = 0;
hdev->HWOp.CntlDDC(hdev, DDC_HDCP_MUX_INIT, 1);
hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP14_OFF);
mutex_lock(&setclk_mutex);
return;
}
hdev->ready = 0;
- rx_repeat_hpd_state(0);
+ if (hdev->repeater_tx)
+ rx_repeat_hpd_state(0);
hdev->HWOp.CntlConfig(hdev, CONF_CLR_AVI_PACKET, 0);
hdev->HWOp.CntlDDC(hdev, DDC_HDCP_MUX_INIT, 1);
hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP14_OFF);
hdmitx_edid_ram_buffer_clear(hdev);
hdev->hpd_state = 0;
hdmitx_notify_hpd(hdev->hpd_state);
- extcon_set_state(&sdev, 0, 0);
- extcon_set_state(&hdmi_audio, 0, 0);
+
+ extcon_set_state_sync(hdmitx_extcon_hdmi, EXTCON_DISP_HDMI, 0);
+ extcon_set_state_sync(hdmitx_excton_audio, EXTCON_DISP_HDMI, 0);
mutex_unlock(&setclk_mutex);
}
{
struct hdmitx_dev *hdmitx_device = (struct hdmitx_dev *)data;
- sdev.state = !!(hdmitx_device->HWOp.CntlMisc(hdmitx_device,
- MISC_HPD_GPI_ST, 0));
- hdmitx_device->hpd_state = sdev.state;
+ hdmitx_extcon_hdmi->state = !!(hdmitx_device->HWOp.CntlMisc(
+ hdmitx_device, MISC_HPD_GPI_ST, 0));
+ hdmitx_device->hpd_state = hdmitx_extcon_hdmi->state;
hdmitx_notify_hpd(hdmitx_device->hpd_state);
- extcon_set_state(&hdmi_power, 0, hdmitx_device->hpd_state);
+ extcon_set_state_sync(hdmitx_excton_power, EXTCON_DISP_HDMI,
+ hdmitx_device->hpd_state);
INIT_WORK(&hdmitx_device->work_hdr, hdr_work_func);
/* When init hdmi, clear the hdmitx module edid ram and edid buffer. */
INIT_WORK(&hdmitx_device->work_internal_intr,
hdmitx_internal_intr_handler);
+ /* for rx sense feature */
+ hdmitx_device->rxsense_wq = alloc_workqueue(hdmitx_excton_rxsense->name,
+ WQ_SYSFS | WQ_FREEZABLE, 0);
+ INIT_DELAYED_WORK(&hdmitx_device->work_rxsense, hdmitx_rxsense_process);
+
hdmitx_device->tx_aud_cfg = 1; /* default audio configure is on */
hdmitx_device->HWOp.SetupIRQ(hdmitx_device);
return 0;
}
+static void hdmitx_init_fmt_attr(struct hdmitx_dev *hdev, char *attr)
+{
+ memset(attr, 0, sizeof(fmt_attr));
+ if ((hdev->para->cd == COLORDEPTH_RESERVED) &&
+ (hdev->para->cs == COLORSPACE_RESERVED)) {
+ strcpy(fmt_attr, "default");
+ } else {
+ switch (hdev->para->cs) {
+ case COLORSPACE_RGB444:
+ memcpy(fmt_attr, "rgb,", 4);
+ break;
+ case COLORSPACE_YUV422:
+ memcpy(fmt_attr, "422,", 4);
+ break;
+ case COLORSPACE_YUV444:
+ memcpy(fmt_attr, "444,", 4);
+ break;
+ case COLORSPACE_YUV420:
+ memcpy(fmt_attr, "420,", 4);
+ break;
+ default:
+ break;
+ }
+ switch (hdev->para->cd) {
+ case COLORDEPTH_24B:
+ strcat(fmt_attr, "8bit");
+ break;
+ case COLORDEPTH_30B:
+ strcat(fmt_attr, "10bit");
+ break;
+ case COLORDEPTH_36B:
+ strcat(fmt_attr, "12bit");
+ break;
+ case COLORDEPTH_48B:
+ strcat(fmt_attr, "16bit");
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void hdmi_init_chip_type(void)
+{
+ /* auto detect chip_type for registers ioremap */
+ switch (get_cpu_type()) {
+ case MESON_CPU_MAJOR_ID_TXLX:
+ hdmitx_device.chip_type = 1;
+ break;
+ default:
+ break;
+ }
+
+ pr_info("hdmitx: %s: %d\n", __func__, hdmitx_device.chip_type);
+}
+
/* for notify to cec */
static BLOCKING_NOTIFIER_HEAD(hdmitx_event_notify_list);
int hdmitx_event_notifier_regist(struct notifier_block *nb)
blocking_notifier_call_chain(&hdmitx_event_notify_list, state, arg);
}
+void hdmitx_hdcp_status(int hdmi_authenticated)
+{
+ extcon_set_state_sync(hdmitx_excton_hdcp, EXTCON_DISP_HDMI,
+ hdmi_authenticated);
+}
+
+void hdmitx_extcon_register(struct platform_device *pdev)
+{
+ struct extcon_dev *edev;
+ int ret;
+
+ /*hdmitx extcon hdmi*/
+ edev = extcon_dev_allocate(hdmi_cable);
+ if (IS_ERR(edev)) {
+ hdmi_print(IMP, SYS "failed to allocate hdmitx extcon hdmi\n");
+ return;
+ }
+ edev->name = "hdmitx_extcon_hdmi";
+ dev_set_name(&edev->dev, "hdmi");
+ ret = extcon_dev_register(edev);
+ if (ret < 0) {
+ hdmi_print(IMP, SYS "failed to register hdmitx extcon hdmi\n");
+ return;
+ }
+ hdmitx_extcon_hdmi = edev;
+
+ /*hdmitx extcon audio*/
+ edev = extcon_dev_allocate(hdmi_cable);
+ if (IS_ERR(edev)) {
+ hdmi_print(IMP, SYS "failed to allocate hdmitx extcon audio\n");
+ return;
+ }
+
+ edev->name = "hdmitx_excton_audio";
+ dev_set_name(&edev->dev, "hdmi_audio");
+ ret = extcon_dev_register(edev);
+ if (ret < 0) {
+ hdmi_print(IMP, SYS "failed to register hdmitx extcon audio\n");
+ return;
+ }
+ hdmitx_excton_audio = edev;
+
+ /*hdmitx extcon power*/
+ edev = extcon_dev_allocate(hdmi_cable);
+ if (IS_ERR(edev)) {
+ hdmi_print(IMP, SYS "failed to allocate hdmitx extcon power\n");
+ return;
+ }
+
+ edev->name = "hdmitx_excton_power";
+ dev_set_name(&edev->dev, "hdmi_power");
+ ret = extcon_dev_register(edev);
+ if (ret < 0) {
+ hdmi_print(IMP, SYS "failed to register extcon power\n");
+ return;
+ }
+ hdmitx_excton_power = edev;
+
+ /*hdmitx extcon hdr*/
+ edev = extcon_dev_allocate(hdmi_cable);
+ if (IS_ERR(edev)) {
+ hdmi_print(IMP, SYS "failed to allocate hdmitx extcon hdr\n");
+ return;
+ }
+
+ edev->name = "hdmitx_excton_hdr";
+ dev_set_name(&edev->dev, "hdmi_hdr");
+ ret = extcon_dev_register(edev);
+ if (ret < 0) {
+ hdmi_print(IMP, SYS "failed to register hdmitx extcon hdr\n");
+ return;
+ }
+ hdmitx_excton_hdr = edev;
+
+ /*hdmitx extcon rxsense*/
+ edev = extcon_dev_allocate(hdmi_cable);
+ if (IS_ERR(edev)) {
+ hdmi_print(IMP, SYS "failed to allocate extcon rxsense\n");
+ return;
+ }
+
+ edev->name = "hdmitx_excton_rxsense";
+ dev_set_name(&edev->dev, "hdmi_rxsense");
+ ret = extcon_dev_register(edev);
+ if (ret < 0) {
+ hdmi_print(IMP, SYS "failed to register extcon rxsense\n");
+ return;
+ }
+ hdmitx_excton_rxsense = edev;
+
+ /*hdmitx extcon hdcp*/
+ edev = extcon_dev_allocate(hdmi_cable);
+ if (IS_ERR(edev)) {
+ hdmi_print(IMP, SYS "failed to allocate extcon hdcp\n");
+ return;
+ }
+
+ edev->name = "hdmitx_excton_hdcp";
+ dev_set_name(&edev->dev, "hdcp");
+ ret = extcon_dev_register(edev);
+ if (ret < 0) {
+ hdmi_print(IMP, SYS "failed to register extcon hdcp\n");
+ return;
+ }
+ hdmitx_excton_hdcp = edev;
+
+}
+
static int amhdmitx_probe(struct platform_device *pdev)
{
int r, ret = 0;
hdmitx_device.vic_count = 0;
hdmitx_device.auth_process_timer = 0;
hdmitx_device.force_audio_flag = 0;
- hdmitx_device.hdcp_mode = -1; /* no hdcp by default */
+ hdmitx_device.hdcp_mode = 0;
hdmitx_device.ready = 0;
+ /* no 1.000/1.001 modes by default */
+ hdmitx_device.frac_rate_policy = 0;
+ hdmitx_device.rxsense_policy = 0; /* no RxSense by default */
#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
register_early_suspend(&hdmitx_early_suspend_handler);
ret = device_create_file(dev, &dev_attr_disp_mode);
ret = device_create_file(dev, &dev_attr_attr);
ret = device_create_file(dev, &dev_attr_aud_mode);
+ ret = device_create_file(dev, &dev_attr_aud_mute);
+ ret = device_create_file(dev, &dev_attr_vid_mute);
ret = device_create_file(dev, &dev_attr_edid);
ret = device_create_file(dev, &dev_attr_rawedid);
+ ret = device_create_file(dev, &dev_attr_sink_type);
ret = device_create_file(dev, &dev_attr_edid_parsing);
ret = device_create_file(dev, &dev_attr_config);
ret = device_create_file(dev, &dev_attr_debug);
ret = device_create_file(dev, &dev_attr_vic);
ret = device_create_file(dev, &dev_attr_phy);
ret = device_create_file(dev, &dev_attr_frac_rate_policy);
+ ret = device_create_file(dev, &dev_attr_rxsense_policy);
ret = device_create_file(dev, &dev_attr_hdcp_clkdis);
ret = device_create_file(dev, &dev_attr_hdcp_pwr);
ret = device_create_file(dev, &dev_attr_hdcp_ksv_info);
ret = device_create_file(dev, &dev_attr_hdcp_ver);
ret = device_create_file(dev, &dev_attr_hdcp_byp);
ret = device_create_file(dev, &dev_attr_hdcp_mode);
+ ret = device_create_file(dev, &dev_attr_hdcp_repeater);
+ ret = device_create_file(dev, &dev_attr_hdcp22_type);
+ ret = device_create_file(dev, &dev_attr_hdcp22_base);
ret = device_create_file(dev, &dev_attr_hdcp_lstore);
ret = device_create_file(dev, &dev_attr_div40);
ret = device_create_file(dev, &dev_attr_hdcp_ctrl);
(long int)&hdmitx_notifier_nb_a;
#endif
+ hdmi_init_chip_type();
#ifdef CONFIG_OF
if (pdev->dev.of_node) {
memset(&hdmitx_device.config_data, 0,
}
pr_info("hdmitx hpd irq = %d\n", hdmitx_device.irq_hpd);
- extcon_dev_register(&sdev);
- extcon_dev_register(&hdmi_audio);
- extcon_dev_register(&hdmi_power);
- extcon_dev_register(&hdmi_hdr);
+ hdmitx_extcon_register(pdev);
hdmitx_init_parameters(&hdmitx_device.hdmi_info);
HDMITX_Meson_Init(&hdmitx_device);
+ hdmitx_init_fmt_attr(&hdmitx_device, fmt_attr);
+ pr_info("hdmitx: attr %s\n", fmt_attr);
hdmitx_device.task = kthread_run(hdmi_task_handle,
&hdmitx_device, "kthread_hdmi");
{
struct device *dev = hdmitx_device.hdtx_dev;
- extcon_dev_unregister(&sdev);
- extcon_dev_unregister(&hdmi_audio);
- extcon_dev_unregister(&hdmi_power);
- extcon_dev_unregister(&hdmi_hdr);
cancel_work_sync(&hdmitx_device.work_hdr);
if (hdmitx_device.HWOp.UnInit)
device_remove_file(dev, &dev_attr_disp_mode);
device_remove_file(dev, &dev_attr_attr);
device_remove_file(dev, &dev_attr_aud_mode);
+ device_remove_file(dev, &dev_attr_aud_mute);
+ device_remove_file(dev, &dev_attr_vid_mute);
device_remove_file(dev, &dev_attr_edid);
device_remove_file(dev, &dev_attr_rawedid);
+ device_remove_file(dev, &dev_attr_sink_type);
device_remove_file(dev, &dev_attr_edid_parsing);
device_remove_file(dev, &dev_attr_config);
device_remove_file(dev, &dev_attr_debug);
device_remove_file(dev, &dev_attr_disp_cap);
+ device_remove_file(dev, &dev_attr_preferred_mode);
device_remove_file(dev, &dev_attr_disp_cap_3d);
device_remove_file(dev, &dev_attr_hdr_cap);
device_remove_file(dev, &dev_attr_dv_cap);
device_remove_file(dev, &dev_attr_avmute);
device_remove_file(dev, &dev_attr_vic);
device_remove_file(dev, &dev_attr_frac_rate_policy);
+ device_remove_file(dev, &dev_attr_rxsense_policy);
device_remove_file(dev, &dev_attr_hdcp_pwr);
device_remove_file(dev, &dev_attr_aud_output_chs);
device_remove_file(dev, &dev_attr_div40);
+ device_remove_file(dev, &dev_attr_hdcp_repeater);
+ device_remove_file(dev, &dev_attr_hdcp22_type);
+ device_remove_file(dev, &dev_attr_hdcp22_base);
cdev_del(&hdmitx_device.cdev);
if (strstr(vout_mode, "cvbs") && current_hdmi_state == 1) {
mutex_lock(&setclk_mutex);
- sdev.state = 0;
- hdmitx_device.hpd_state = sdev.state;
+ hdmitx_extcon_hdmi->state = 0;
+ hdmitx_device.hpd_state = hdmitx_extcon_hdmi->state;
hdmitx_notify_hpd(hdmitx_device.hpd_state);
mutex_unlock(&setclk_mutex);
pr_info("resend hdmi plug in event\n");
&hdmitx_device.work_hpd_plugin, 2 * HZ);
} else {
mutex_lock(&setclk_mutex);
- sdev.state = current_hdmi_state;
- hdmitx_device.hpd_state = sdev.state;
+ hdmitx_extcon_hdmi->state = current_hdmi_state;
+ hdmitx_device.hpd_state = hdmitx_extcon_hdmi->state;
hdmitx_notify_hpd(hdmitx_device.hpd_state);
mutex_unlock(&setclk_mutex);
}
obj-y += hdmi_tx_hw.o reg_ops.o sec_ops.o enc_cfg_hw.o hdmi_tx_ddc.o hdcpVerify.o
-obj-y += hw_gxbb.o hw_gxtvbb.o hw_gxl.o hw_clk.o
+obj-y += hw_gxbb.o hw_gxtvbb.o hw_gxl.o hw_txlx.o hw_clk.o
void set_hpll_od2_gxl(unsigned int div);
void set_hpll_od3_gxl(unsigned int div);
+int hdmitx_hpd_hw_op_txlx(enum hpd_op cmd);
+int read_hpd_gpio_txlx(void);
+int hdmitx_ddc_hw_op_txlx(enum ddc_op cmd);
+
#endif
return st;
}
+#if 0
static uint32_t ddc_readext_8byte(uint8_t slave, uint8_t offset_addr,
uint8_t *data)
{
uint32_t st = 0;
int32_t i;
-
hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, slave);
hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, offset_addr);
hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, EDIDSEG_ADR);
data[i] = hdmitx_rd_reg(HDMITX_DWC_I2CM_READ_BUFF0 + i);
return st;
}
+#endif
static uint32_t ddc_read_8byte(uint8_t slave, uint8_t offset_addr,
uint8_t *data)
return st;
}
+#if 0
static uint32_t ddc_readext_1byte(uint8_t slave, uint8_t address, uint8_t *data)
{
uint32_t st = 0;
-
+ int32_t i;
hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, slave);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, address);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, offset_addr);
hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, EDIDSEG_ADR);
hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, 0x00);
hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 1);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc rd8b error 0x%02x 0x%02x\n",
- slave, address);
+ slave, offset_addr);
} else
st = 1;
hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0x7);
*data = hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI);
return st;
}
+#endif
static uint32_t ddc_read_1byte(uint8_t slave, uint8_t offset_addr,
uint8_t *data)
static uint32_t hdcp_rd_bksv(uint8_t *data)
{
- if (0)
- ddc_readext_8byte(HDCP_SLAVE, HDCP14_BKSV, data);
-
return ddc_read_8byte(HDCP_SLAVE, HDCP14_BKSV, data);
}
void scdc_rd_sink(uint8_t adr, uint8_t *val)
{
hdmitx_ddc_hw_op(DDC_MUX_DDC);
-
- if (0)
- ddc_readext_1byte(SCDC_SLAVE, adr, val);
-
ddc_read_1byte(SCDC_SLAVE, adr, val);
}
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
return hdmitx_hpd_hw_op_gxl(cmd);
+ case MESON_CPU_MAJOR_ID_TXLX:
+ return hdmitx_hpd_hw_op_txlx(cmd);
default:
break;
}
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
return read_hpd_gpio_gxl();
+ case MESON_CPU_MAJOR_ID_TXLX:
+ return read_hpd_gpio_txlx();
default:
break;
}
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
return hdmitx_ddc_hw_op_gxl(cmd);
+ case MESON_CPU_MAJOR_ID_TXLX:
+ return hdmitx_ddc_hw_op_txlx(cmd);
default:
break;
}
/* [ 6: 0] clk_div. Divide by 1. = 24/1 = 24 MHz */
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0x100, 0, 16);
+ hd_write_reg(P_HHI_HDCP22_CLK_CNTL, 0x01000100);
+ hd_set_reg_bits(P_HHI_GCLK_MPEG2, 1, 3, 1);
+
/* Enable clk81_hdmitx_pclk */
hd_set_reg_bits(P_HHI_GCLK_MPEG2, 1, 4, 1);
/* wire wr_enable = control[3]; */
/* assign phy_clk_en = control[1]; */
/* Bring HDMITX MEM output of power down */
hd_set_reg_bits(P_HHI_MEM_PD_REG0, 0, 8, 8);
- if (hdmitx_uboot_already_display())
+ if (hdmitx_uboot_already_display()) {
+ /* Get uboot output color space from AVI */
+ switch (hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF0) & 0x3) {
+ case 0:
+ hdev->para->cs = COLORSPACE_RGB444;
+ break;
+ case 1:
+ hdev->para->cs = COLORSPACE_YUV422;
+ break;
+ case 2:
+ hdev->para->cs = COLORSPACE_YUV444;
+ break;
+ case 3:
+ hdev->para->cs = COLORSPACE_YUV420;
+ break;
+ default:
+ break;
+ }
+ /* If color space is not 422, then get depth from VP_PR_CD */
+ if (hdev->para->cs != COLORSPACE_YUV422) {
+ switch ((hdmitx_rd_reg(HDMITX_DWC_VP_PR_CD) >> 4) &
+ 0xf) {
+ case 5:
+ hdev->para->cd = COLORDEPTH_30B;
+ break;
+ case 6:
+ hdev->para->cd = COLORDEPTH_36B;
+ break;
+ case 7:
+ hdev->para->cd = COLORDEPTH_48B;
+ break;
+ case 0:
+ case 4:
+ default:
+ hdev->para->cd = COLORDEPTH_24B;
+ break;
+ }
+ } else {
+ /* If colorspace is 422, then get depth from VP_REMAP */
+ switch (hdmitx_rd_reg(HDMITX_DWC_VP_REMAP) & 0x3) {
+ case 1:
+ hdev->para->cd = COLORDEPTH_30B;
+ break;
+ case 2:
+ hdev->para->cd = COLORDEPTH_36B;
+ break;
+ case 0:
+ default:
+ hdev->para->cd = COLORDEPTH_24B;
+ break;
+ }
+ }
return;
+ } else {
+ hdev->para->cd = COLORDEPTH_RESERVED;
+ hdev->para->cs = COLORSPACE_RESERVED;
+ }
/* reset HDMITX APB & TX & PHY */
hd_set_reg_bits(P_RESET0_REGISTER, 1, 19, 1);
hd_set_reg_bits(P_RESET2_REGISTER, 1, 15, 1);
{
unsigned int data32 = 0;
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 1, 7, 1);
+ hdmitx_wr_reg(HDMITX_DWC_A_HDCPCFG1, 0x7);
+ hdmitx_wr_reg(HDMITX_DWC_A_HDCPCFG0, 0x53);
+ /* Enable skpclk to HDCP2.2 IP */
+ hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 7, 1);
+ /* Enable esmclk to HDCP2.2 IP */
+ hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 6, 1);
+ /* Enable tmds_clk to HDCP2.2 IP */
+ hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 5, 1);
+
hdmitx_hpd_hw_op(HPD_INIT_DISABLE_PULLUP);
hdmitx_hpd_hw_op(HPD_INIT_SET_FILTER);
hdmitx_ddc_hw_op(DDC_INIT_DISABLE_PULL_UP_DN);
hdev->HWOp.CntlPacket = hdmitx_cntl;
hdev->HWOp.CntlConfig = hdmitx_cntl_config;
hdev->HWOp.CntlMisc = hdmitx_cntl_misc;
- init_reg_map();
+ init_reg_map(hdev->chip_type);
digital_clk_on(0xff);
hdmi_hwp_init(hdev);
hdmi_hwi_init(hdev);
hdmitx_rd_reg(HDMITX_DWC_HDCP22REG_STAT));
hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_STAT, 0xff);
}
- hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, data32 | 0x6);
+ /* ack INTERNAL_INTR or else we stuck with no interrupts at all */
+ hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, data32 | 0x7);
return IRQ_HANDLED;
}
(0 << 12)
);
hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
-
}
static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
if (hdev->flag_3dfp)
set_phy_by_mode(2);
else
- set_phy_by_mode(3);
+ set_phy_by_mode(3);
break;
default:
if (hdev->flag_3dfp)
set_phy_by_mode(3);
else
- set_phy_by_mode(4);
+ set_phy_by_mode(4);
break;
}
- hdmi_print(IMP, SYS "PHY Setting Done\n");
}
static void set_tmds_clk_div40(unsigned int div40)
if (hdev->cur_video_param == NULL) /* disable HDMI */
return 0;
- if (!hdmitx_edid_VIC_support(hdev->cur_video_param->VIC))
- return -1;
- hdev->cur_VIC = hdev->cur_video_param->VIC;
- if (hdev->RXCap.scdc_present)
- pr_info("hdmitx: rx has SCDC present indicator\n");
else
- pr_info("hdmitx: rx no SCDC present indicator\n");
+ if (!hdmitx_edid_VIC_support(hdev->cur_video_param->VIC))
+ return -1;
+ hdev->cur_VIC = hdev->cur_video_param->VIC;
scdc_rd_sink(SINK_VER, &rx_ver);
if (rx_ver != 1)
/* move hdmitx_set_pll() to the end of this function. */
/* hdmitx_set_pll(param); */
hdev->cur_VIC = hdev->cur_video_param->VIC;
+ /* For 3D, enable phy by SystemControl at last step */
if ((!hdev->flag_3dfp) && (!hdev->flag_3dtb) && (!hdev->flag_3dss))
- hdmitx_set_phy(hdev);
+ hdmitx_set_phy(hdev);
switch (hdev->cur_video_param->VIC) {
case HDMI_480i60:
case HDMI_480i60_16x9:
pr_info("hdmitx: swrstzreq\n");
}
return 0;
- } else if (cmd == HDMITX_HDCP_MONITOR) {
- /* TODO */
- return 0;
- } else if (cmd == HDMITX_IP_SW_RST) {
- return 0; /* TODO */
- } else if (cmd == HDMITX_CBUS_RST) {
- return 0;/* todo */
- hd_set_reg_bits(P_RESET2_REGISTER, 1, 15, 1);
- return 0;
- } else if (cmd == HDMITX_INTR_MASKN_CNTL)
- /* TODO */
- return 0;
- else if (cmd == HDMITX_HWCMD_MUX_HPD_IF_PIN_HIGH) {
+ } else if (cmd == HDMITX_HWCMD_MUX_HPD_IF_PIN_HIGH) {
/* turnon digital module if gpio is high */
if (hdmitx_hpd_hw_op(HPD_IS_HPD_MUXED) == 0) {
if (hdmitx_hpd_hw_op(HPD_READ_HPD_GPIO)) {
cts_buf[i].val, i - 1, cts_buf[i - 1].val);
}
- for (i = 0; i < AUD_CTS_LOG_NUM; i++) {
+ for (i = 0, min = max = cts_buf[0].val; i < AUD_CTS_LOG_NUM; i++) {
total += cts_buf[i].val;
if (min > cts_buf[i].val)
min = cts_buf[i].val;
/* Wait until I2C done */
timeout = 0;
while ((!(hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 1)))
- && (timeout < 5)) {
- mdelay(1);
+ && (timeout < 3)) {
+ mdelay(2);
timeout++;
}
- if (timeout == 5)
+ if (timeout == 3)
pr_info("hdmitx: ddc timeout\n");
- mdelay(1);
hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 1 << 1);
/* Read back 8 bytes */
for (i = 0; i < 8; i++) {
hdmitx_rd_reg(HDMITX_DWC_HDCPREG_BKSV0 + i);
hdcp_ksv_store(ksv, 5);
get_hdcp_bstatus();
- rx_set_receive_hdcp(rptx_ksv_buf, (rptx_ksv_no + 1) / 5,
- (bcaps_6_rp ? get_hdcp_depth() : 0) + 1,
- bcaps_6_rp ? get_hdcp_max_cascade() : 0,
- bcaps_6_rp ? get_hdcp_max_devs() : 0);
- pr_info("%s[%d] ksvs Num = %d device_count = %d\n",
- __func__, __LINE__,
- (rptx_ksv_no + 1) / 5,
- bcaps_6_rp ? get_hdcp_device_count() : 0);
- memset(rptx_ksv_prbuf, 0, sizeof(rptx_ksv_prbuf));
- for (pos = 0, i = 0; i < rptx_ksv_no; i++)
- pos += sprintf(rptx_ksv_prbuf + pos, "%02x",
- rptx_ksv_buf[i]);
- rptx_ksv_prbuf[pos + 1] = '\0';
- if (1)
- hdcp_ksv_print();
+ if (hdev->repeater_tx) {
+ rx_set_receive_hdcp(rptx_ksv_buf, (rptx_ksv_no + 1) / 5,
+ (bcaps_6_rp ? get_hdcp_depth() : 0) + 1,
+ bcaps_6_rp ? get_hdcp_max_cascade() : 0,
+ bcaps_6_rp ? get_hdcp_max_devs() : 0);
+ pr_info("%s[%d] ksvs Num = %d device_count = %d\n",
+ __func__, __LINE__,
+ (rptx_ksv_no + 1) / 5,
+ bcaps_6_rp ? get_hdcp_device_count() : 0);
+ memset(rptx_ksv_prbuf, 0, sizeof(rptx_ksv_prbuf));
+ for (pos = 0, i = 0; i < rptx_ksv_no; i++)
+ pos += sprintf(rptx_ksv_prbuf + pos,
+ "%02x", rptx_ksv_buf[i]);
+ rptx_ksv_prbuf[pos + 1] = '\0';
+ if (1)
+ hdcp_ksv_print();
+ }
}
if (st_flag & (1 << 1)) {
- rptx_ksvlist_retry++;
hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, (1 << 1));
hdmitx_wr_reg(HDMITX_DWC_A_KSVMEMCTRL, 0x1);
hdmitx_poll_reg(HDMITX_DWC_A_KSVMEMCTRL, (1<<1), 2 * HZ);
return;
}
hdmitx_wr_reg(HDMITX_DWC_A_KSVMEMCTRL, 0x4);
- if (rptx_ksvlist_retry % 4 == 0) {
- for (i = 0; i < 5; i++)
- ksv[i] = (unsigned char)
- hdmitx_rd_reg(HDMITX_DWC_HDCPREG_BKSV0
- + i);
- hdcp_ksv_store(ksv, 5);
- rx_set_receive_hdcp(&ksv[0], 1, 127, 1, 1);
+ if (hdev->repeater_tx) {
+ rptx_ksvlist_retry++;
+ if (rptx_ksvlist_retry % 4 == 0) {
+ for (i = 0; i < 5; i++)
+ ksv[i] = (unsigned char) hdmitx_rd_reg(
+ HDMITX_DWC_HDCPREG_BKSV0 + i);
+ hdcp_ksv_store(ksv, 5);
+ rx_set_receive_hdcp(&ksv[0], 1, 127, 1, 1);
+ }
}
-
}
- if ((bcaps_6_rp) && (get_hdcp_max_devs() || get_hdcp_max_cascade())) {
+ if (hdev->repeater_tx && bcaps_6_rp && (get_hdcp_max_devs() ||
+ get_hdcp_max_cascade())) {
for (i = 0; i < 5; i++)
ksv[i] = (unsigned char)
hdmitx_rd_reg(HDMITX_DWC_HDCPREG_BKSV0 + i);
mod_timer(&hdev->hdcp_timer, jiffies + HZ / 100);
}
+static void set_pkf_duk_nonce(void)
+{
+ static int nonce_mode = 1; /* 1: use HW nonce 0: use SW nonce */
+
+ /* Configure duk/pkf */
+ hdmitx_hdcp_opr(0xc);
+ if (nonce_mode == 1)
+ hdmitx_wr_reg(HDMITX_TOP_SKP_CNTL_STAT, 0xf);
+ else {
+ hdmitx_wr_reg(HDMITX_TOP_SKP_CNTL_STAT, 0xe);
+/* Configure nonce[127:0].
+ * MSB must be written the last to assert nonce_vld signal.
+ */
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_0, 0x32107654);
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_1, 0xba98fedc);
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_2, 0xcdef89ab);
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_3, 0x45670123);
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_0, 0x76543210);
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_1, 0xfedcba98);
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_2, 0x89abcdef);
+ hdmitx_wr_reg(HDMITX_TOP_NONCE_3, 0x01234567);
+ }
+ udelay(10);
+}
+
static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd,
unsigned long argv)
{
break;
case DDC_HDCP_MUX_INIT:
- if (argv == 2)
+ if (argv == 2) {
hdmitx_ddc_hw_op(DDC_MUX_DDC);
+ hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1);
+ udelay(5);
+ hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_CTRL, 0x6);
+ hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 1, 5, 1);
+ udelay(10);
+ hdmitx_set_reg_bits(HDMITX_TOP_SW_RESET, 0, 5, 1);
+ udelay(10);
+ hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MASK, 0);
+ hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_MUTE, 0);
+ set_pkf_duk_nonce();
+ }
if (argv == 1)
hdmitx_hdcp_opr(6);
break;
rptx_ksv_no = 0;
memset(rptx_ksv_buf, 0, sizeof(rptx_ksv_buf));
hdmitx_ddc_hw_op(DDC_MUX_DDC);
- hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 0, 6, 1);
hdmitx_hdcp_opr(6);
hdmitx_hdcp_opr(1);
hdcp_start_timer(hdev);
return hdmitx_hdcp_opr(0xa);
case DDC_HDCP_22_LSTORE:
return hdmitx_hdcp_opr(0xb);
- case DDC_HDCP_BYP:
- hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1);
break;
case DDC_SCDC_DIV40_SCRAMB:
if (argv == 1) {
hdmitx_wr_reg(HDMITX_DWC_FC_SCRAMBLER_CTRL, 0);
}
break;
+ case DDC_HDCP14_GET_BCAPS_RP:
+ return !!(hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS3) & (1 << 6));
default:
hdmi_print(INF, "ddc: unknown cmd: 0x%x\n", cmd);
break;
case CONF_AUDIO_MUTE_OP:
audio_mute_op(argv == AUDIO_MUTE ? 0 : 1);
break;
- case CONF_VIDEO_BLANK_OP:
- return 1; /* TODO */
- if (argv == VIDEO_BLANK) {
- /* set blank CrYCb as 0x200 0x0 0x200 */
- hd_write_reg(P_VPU_HDMI_DATA_OVR,
- (0x200 << 20) | (0x0 << 10) | (0x200 << 0));
- /* Output data map: CrYCb */
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 5, 3);
- /* Enable HDMI data override */
- hd_set_reg_bits(P_VPU_HDMI_DATA_OVR, 1, 31, 1);
+ case CONF_VIDEO_MUTE_OP:
+ if (argv == VIDEO_MUTE) {
+ hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 3, 1);
+ hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 0, 3, 1);
+ hd_write_reg(P_VENC_VIDEO_TST_EN, 1);
+ hd_write_reg(P_VENC_VIDEO_TST_MDSEL, 0);
+ /*_Y/CB/CR, 10bits Unsigned/Signed/Signed */
+ hd_write_reg(P_VENC_VIDEO_TST_Y, 0x0);
+ hd_write_reg(P_VENC_VIDEO_TST_CB, 0x200);
+ hd_write_reg(P_VENC_VIDEO_TST_CR, 0x200);
+ }
+ if (argv == VIDEO_UNMUTE) {
+ hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 1, 3, 1);
+ hd_write_reg(P_VENC_VIDEO_TST_EN, 0);
}
- if (argv == VIDEO_UNBLANK)
- /* Disable HDMI data override */
- hd_write_reg(P_VPU_HDMI_DATA_OVR, 0);
break;
case CONF_CLR_AVI_PACKET:
hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0);
if (hdmitx_rd_reg(HDMITX_DWC_FC_VSDPAYLOAD0) == 0x20)
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, 0);
hd_write_reg(P_ISA_DEBUG_REG0, 0);
break;
case CONF_CLR_VSDB_PACKET:
if (hdmitx_rd_reg(HDMITX_DWC_FC_VSDPAYLOAD0) == 0x20)
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, 0);
break;
case CONF_VIDEO_MAPPING:
config_video_mapping(hdev->para->cs, hdev->para->cd);
return ret;
}
+static int hdmitx_tmds_rxsense(void)
+{
+ unsigned int curr0, curr3;
+ int ret = 0;
+
+ switch (get_cpu_type()) {
+ case MESON_CPU_MAJOR_ID_GXBB:
+ curr0 = hd_read_reg(P_HHI_HDMI_PHY_CNTL0);
+ curr3 = hd_read_reg(P_HHI_HDMI_PHY_CNTL3);
+ if (curr0 == 0)
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33632122);
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL3, 0x9a, 16, 8);
+ ret = hd_read_reg(P_HHI_HDMI_PHY_CNTL2) & 0x1;
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, curr3);
+ if (curr0 == 0)
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0);
+ break;
+ case MESON_CPU_MAJOR_ID_GXL:
+ case MESON_CPU_MAJOR_ID_GXM:
+ default:
+ curr0 = hd_read_reg(P_HHI_HDMI_PHY_CNTL0);
+ curr3 = hd_read_reg(P_HHI_HDMI_PHY_CNTL3);
+ if (curr0 == 0)
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33604142);
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL3, 0x1, 4, 1);
+ ret = hd_read_reg(P_HHI_HDMI_PHY_CNTL2) & 0x1;
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, curr3);
+ if (curr0 == 0)
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0);
+ break;
+ }
+
+ return ret;
+}
+
static int hdmitx_cntl_misc(struct hdmitx_dev *hdev, unsigned int cmd,
unsigned int argv)
{
if (argv == TMDS_PHY_DISABLE)
hdmi_phy_suspend();
break;
+ case MISC_TMDS_RXSENSE:
+ return hdmitx_tmds_rxsense();
case MISC_ESM_RESET:
if (hdev->hdcp_hpd_stick == 1) {
pr_info("hdcp: stick mode\n");
config_avmute(argv);
break;
case MISC_HDCP_CLKDIS:
- hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, argv, 6, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, !!argv, 6, 1);
break;
default:
hdmi_print(ERR, "misc: hdmitx: unknown cmd: 0x%x\n", cmd);
* until later enable by test.c
*/
data32 = 0;
- data32 |= (0 << 6);
- data32 |= (0 << 5);
- data32 |= (0 << 4);
- data32 |= (0 << 3);
- data32 |= (0 << 2);
- data32 |= (0 << 1);
- data32 |= (0 << 0);
hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, data32);
/* Enable normal output to PHY */
return;
}
- pr_info("%s[%d] set VIC = %d\n", __func__, __LINE__, para->vic);
config_hdmi20_tx(vic, hdev,
hdev->para->cd,
TX_INPUT_COLOR_FORMAT,
#include "mach_reg.h"
#include "hw_clk.h"
+/* local frac_rate flag */
static uint32_t frac_rate;
+/* enable or disable HDMITX SSPLL, enable by default */
static int sspll_en = 1;
/*
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4a05, 0, 16);
else
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4c00, 0, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4c00, 0, 16);
break;
case 5405400:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000270);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4443, 0, 16);
else
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4580, 0, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4580, 0, 16);
break;
case 3450000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000247);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4d03, 0, 16);
else
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4e00, 0, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4e00, 0, 16);
break;
case 4324320:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800025a);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4281, 0, 16);
else
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4300, 0, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4300, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x12dc5081);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4111, 0, 16);
else
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4160, 0, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4160, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4341, 0, 16);
else
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4380, 0, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4380, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
- default:
+ case MESON_CPU_MAJOR_ID_TXLX:
set_gxl_hpll_clk_out(frac_rate, clk);
break;
+ default:
+ break;
}
pr_info("config HPLL done\n");
}
+/* HERE MUST BE BIT OPERATION!!! */
static void set_hpll_sspll(enum hdmi_vic vic)
{
switch (get_cpu_type()) {
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
-/* mode hpll_clk_out od1 od2(PHY) od3
- * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
- */
+/* For colordepth 10bits */
static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
{{HDMI_720x480i60_16x9,
HDMI_720x576i50_16x9,
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
+/* For colordepth 12bits */
static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
{{HDMI_720x480i60_16x9,
HDMI_720x576i50_16x9,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
+
+/* For 3D Frame Packing Clock Setting
+ * mode hpll_clk_out od1 od2(PHY) od3
+ * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
+ */
static struct hw_enc_clk_val_group setting_3dfp_enc_clk_val[] = {
{{HDMI_1920x1080p60_16x9,
HDMI_1920x1080p50_16x9,
HDMI_1920x1080p25_16x9,
HDMI_VIC_END},
2970000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ /* NO 2160p mode*/
{{HDMI_VIC_FAKE,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
+
static void hdmitx_set_clk_(enum hdmi_vic vic, enum hdmi_color_depth cd)
{
int i = 0;
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
}
+
static void hdmitx_set_3dfp_clk(enum hdmi_vic vic)
{
int i = 0;
return 1;
else
return 0;
- }
+}
+
void hdmitx_set_clk(struct hdmitx_dev *hdev)
{
enum hdmi_vic vic = hdev->cur_VIC;
}
if (hdev->para->cs != COLORSPACE_YUV422)
hdmitx_set_clk_(vic, hdev->para->cd);
-
-
else
hdmitx_set_clk_(vic, COLORDEPTH_24B);
- }
+}
MODULE_PARM_DESC(sspll_en, "\n hdmitx sspll_en\n");
module_param(sspll_en, int, 0664);
enum hdmi_vic group[GROUP_MAX];
unsigned int hpll_clk_out; /* Unit: kHz */
unsigned int od1;
- unsigned int od2; /* HDMI_CLK_TODIG */
- unsigned int od3;
- unsigned int vid_pll_div;
- unsigned int vid_clk_div;
- unsigned int hdmi_tx_pixel_div;
- unsigned int encp_div;
- unsigned int enci_div;
+ unsigned int od2; /* HDMI_CLK_TODIG */
+ unsigned int od3;
+ unsigned int vid_pll_div;
+ unsigned int vid_clk_div;
+ unsigned int hdmi_tx_pixel_div;
+ unsigned int encp_div;
+ unsigned int enci_div;
};
void hdmitx_set_clk(struct hdmitx_dev *hdev);
#undef P_HHI_HDMI_PLL_CNTL6
#endif
-#define P_HHI_HDMI_PLL_CNTL1 (0xc883c000 + (0xc9 << 2))
-#define P_HHI_HDMI_PLL_CNTL2 (0xc883c000 + (0xca << 2))
-#define P_HHI_HDMI_PLL_CNTL3 (0xc883c000 + (0xcb << 2))
-#define P_HHI_HDMI_PLL_CNTL4 (0xc883c000 + (0xcc << 2))
-#define P_HHI_HDMI_PLL_CNTL5 (0xc883c000 + (0xcd << 2))
+#define P_HHI_HDMI_PLL_CNTL1 HHI_REG_ADDR(0xc9)
+#define P_HHI_HDMI_PLL_CNTL2 HHI_REG_ADDR(0xca)
+#define P_HHI_HDMI_PLL_CNTL3 HHI_REG_ADDR(0xcb)
+#define P_HHI_HDMI_PLL_CNTL4 HHI_REG_ADDR(0xcc)
+#define P_HHI_HDMI_PLL_CNTL5 HHI_REG_ADDR(0xcd)
/*
* NAME PAD PINMUX GPIO
--- /dev/null
+/*
+ * drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_txlx.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/printk.h>
+#include "common.h"
+#include "mach_reg.h"
+
+/*
+ * NAME PAD PINMUX GPIO
+ * HPD GPIOH_1 reg0[23] GPIO1[21]
+ * SCL GPIOH_2 reg0[22] GPIO1[22[
+ * SDA GPIOH_3 reg0[21] GPIO1[23]
+ */
+
+int hdmitx_hpd_hw_op_txlx(enum hpd_op cmd)
+{
+ int ret = 0;
+
+ switch (cmd) {
+ case HPD_INIT_DISABLE_PULLUP:
+ hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 21, 1);
+ break;
+ case HPD_INIT_SET_FILTER:
+ hdmitx_wr_reg(HDMITX_TOP_HPD_FILTER,
+ ((0xa << 12) | (0xa0 << 0)));
+ break;
+ case HPD_IS_HPD_MUXED:
+ ret = !!(hd_read_reg(P_PERIPHS_PIN_MUX_0) & (1 << 23));
+ break;
+ case HPD_MUX_HPD:
+ hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 21, 1);
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 1, 23, 1);
+ break;
+ case HPD_UNMUX_HPD:
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 0, 23, 1);
+ hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 21, 1);
+ break;
+ case HPD_READ_HPD_GPIO:
+ ret = !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 21));
+ break;
+ default:
+ pr_info("error hpd cmd %d\n", cmd);
+ break;
+ }
+ return ret;
+}
+
+int read_hpd_gpio_txlx(void)
+{
+ return !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 21));
+}
+
+int hdmitx_ddc_hw_op_txlx(enum ddc_op cmd)
+{
+ int ret = 0;
+
+ switch (cmd) {
+ case DDC_INIT_DISABLE_PULL_UP_DN:
+ hd_set_reg_bits(P_PAD_PULL_UP_EN_REG1, 0, 22, 2);
+ hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 22, 2);
+ break;
+ case DDC_MUX_DDC:
+ hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 22, 2);
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 3, 21, 2);
+ break;
+ case DDC_UNMUX_DDC:
+ hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 22, 2);
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 0, 21, 2);
+ break;
+ default:
+ pr_info("error ddc cmd %d\n", cmd);
+ }
+ return ret;
+}
unsigned int val;
};
-#define OFFSET 24
-#define CBUS_REG_ADDR(reg) ((IO_CBUS_BASE << OFFSET) + (reg << 2))
-#define nCBUS_REG_ADDR(reg) (0xc8834400 + (reg << 2))
-#define VCBUS_REG_ADDR(reg) (0xd0100000 + (reg << 2))
-#define AOBUS_REG_ADDR(reg) ((IO_AOBUS_BASE << OFFSET) + reg)
-#define APB_REG_ADDR(reg) ((IO_APB_BUS_BASE << OFFSET) + reg)
-
unsigned int hd_read_reg(unsigned int addr);
void hd_write_reg(unsigned int addr, unsigned int val);
void hd_set_reg_bits(unsigned int addr, unsigned int value, unsigned int offset,
unsigned int len);
-void sec_reg_write(unsigned int *addr, unsigned int value);
+void sec_reg_write(unsigned int *addr, unsigned int value);
unsigned int sec_reg_read(unsigned int *addr);
-void init_reg_map(void);
+void init_reg_map(unsigned int type);
+
+#define CBUS_REG_IDX 0
+#define PERIPHS_REG_IDX 1
+#define VCBUS_REG_IDX 2
+#define AOBUS_REG_IDX 3
+#define HHI_REG_IDX 4
+#define RESET_CBUS_REG_IDX 5
+#define HDMITX_REG_IDX 6
+#define HDMITX_SEC_REG_IDX 7
+#define ELP_ESM_REG_IDX 8
+#define REG_IDX_END 9
+
+#define BASE_REG_OFFSET 24
+
+#define CBUS_REG_ADDR(reg) \
+ ((CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define PERIPHS_REG_ADDR(reg) \
+ ((PERIPHS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define VCBUS_REG_ADDR(reg) \
+ ((VCBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define AOBUS_REG_ADDR(reg) \
+ ((AOBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define HHI_REG_ADDR(reg) \
+ ((HHI_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define RESET_CBUS_REG_ADDR(reg) \
+ ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define HDMITX_SEC_REG_ADDR(reg) \
+ ((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define HDMITX_REG_ADDR(reg) \
+ ((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+#define ELP_ESM_REG_ADDR(reg) \
+ ((ELP_ESM_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define WAIT_FOR_PLL_LOCKED(reg) \
do { \
pr_info("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
} while (0)
-#define P_PREG_PAD_GPIO6_EN_N nCBUS_REG_ADDR(0x08)
-#define P_PREG_PAD_GPIO6_O nCBUS_REG_ADDR(0x09)
-#define P_PREG_PAD_GPIO6_I nCBUS_REG_ADDR(0x0a)
-#define P_PREG_JTAG_GPIO_ADDR nCBUS_REG_ADDR(0x0b)
-#define P_PREG_PAD_GPIO0_EN_N nCBUS_REG_ADDR(0x0c)
-#define P_PREG_PAD_GPIO0_O nCBUS_REG_ADDR(0x0d)
-#define P_PREG_PAD_GPIO0_I nCBUS_REG_ADDR(0x0e)
-#define P_PREG_PAD_GPIO1_EN_N nCBUS_REG_ADDR(0x0f)
-#define P_PREG_PAD_GPIO1_O nCBUS_REG_ADDR(0x10)
-#define P_PREG_PAD_GPIO1_I nCBUS_REG_ADDR(0x11)
-#define P_PREG_PAD_GPIO2_EN_N nCBUS_REG_ADDR(0x12)
-#define P_PREG_PAD_GPIO2_O nCBUS_REG_ADDR(0x13)
-#define P_PREG_PAD_GPIO2_I nCBUS_REG_ADDR(0x14)
-#define P_PREG_PAD_GPIO3_EN_N nCBUS_REG_ADDR(0x15)
-#define P_PREG_PAD_GPIO3_O nCBUS_REG_ADDR(0x16)
-#define P_PREG_PAD_GPIO3_I nCBUS_REG_ADDR(0x17)
-#define P_PREG_PAD_GPIO4_EN_N nCBUS_REG_ADDR(0x18)
-#define P_PREG_PAD_GPIO4_O nCBUS_REG_ADDR(0x19)
-#define P_PREG_PAD_GPIO4_I nCBUS_REG_ADDR(0x1a)
-#define P_PREG_PAD_GPIO5_EN_N nCBUS_REG_ADDR(0x1b)
-#define P_PREG_PAD_GPIO5_O nCBUS_REG_ADDR(0x1c)
-#define P_PREG_PAD_GPIO5_I nCBUS_REG_ADDR(0x1d)
+#define P_PREG_PAD_GPIO6_EN_N PERIPHS_REG_ADDR(0x08)
+#define P_PREG_PAD_GPIO6_O PERIPHS_REG_ADDR(0x09)
+#define P_PREG_PAD_GPIO6_I PERIPHS_REG_ADDR(0x0a)
+#define P_PREG_JTAG_GPIO_ADDR PERIPHS_REG_ADDR(0x0b)
+#define P_PREG_PAD_GPIO0_EN_N PERIPHS_REG_ADDR(0x0c)
+#define P_PREG_PAD_GPIO0_O PERIPHS_REG_ADDR(0x0d)
+#define P_PREG_PAD_GPIO0_I PERIPHS_REG_ADDR(0x0e)
+#define P_PREG_PAD_GPIO1_EN_N PERIPHS_REG_ADDR(0x0f)
+#define P_PREG_PAD_GPIO1_O PERIPHS_REG_ADDR(0x10)
+#define P_PREG_PAD_GPIO1_I PERIPHS_REG_ADDR(0x11)
+#define P_PREG_PAD_GPIO2_EN_N PERIPHS_REG_ADDR(0x12)
+#define P_PREG_PAD_GPIO2_O PERIPHS_REG_ADDR(0x13)
+#define P_PREG_PAD_GPIO2_I PERIPHS_REG_ADDR(0x14)
+#define P_PREG_PAD_GPIO3_EN_N PERIPHS_REG_ADDR(0x15)
+#define P_PREG_PAD_GPIO3_O PERIPHS_REG_ADDR(0x16)
+#define P_PREG_PAD_GPIO3_I PERIPHS_REG_ADDR(0x17)
+#define P_PREG_PAD_GPIO4_EN_N PERIPHS_REG_ADDR(0x18)
+#define P_PREG_PAD_GPIO4_O PERIPHS_REG_ADDR(0x19)
+#define P_PREG_PAD_GPIO4_I PERIPHS_REG_ADDR(0x1a)
+#define P_PREG_PAD_GPIO5_EN_N PERIPHS_REG_ADDR(0x1b)
+#define P_PREG_PAD_GPIO5_O PERIPHS_REG_ADDR(0x1c)
+#define P_PREG_PAD_GPIO5_I PERIPHS_REG_ADDR(0x1d)
+
#define PERIPHS_PIN_MUX_0 0x2c /* register.h:419 */
-#define P_PERIPHS_PIN_MUX_0 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_0)
+#define P_PERIPHS_PIN_MUX_0 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_0)
#define PERIPHS_PIN_MUX_1 0x2d /* register.h:420 */
-#define P_PERIPHS_PIN_MUX_1 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define P_PERIPHS_PIN_MUX_1 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_1)
#define PERIPHS_PIN_MUX_2 0x2e /* register.h:421 */
-#define P_PERIPHS_PIN_MUX_2 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define P_PERIPHS_PIN_MUX_2 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_2)
#define PERIPHS_PIN_MUX_3 0x2f /* register.h:422 */
-#define P_PERIPHS_PIN_MUX_3 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define P_PERIPHS_PIN_MUX_3 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_3)
#define PERIPHS_PIN_MUX_4 0x30 /* register.h:423 */
-#define P_PERIPHS_PIN_MUX_4 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_4)
+#define P_PERIPHS_PIN_MUX_4 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_4)
#define PERIPHS_PIN_MUX_5 0x31 /* register.h:424 */
-#define P_PERIPHS_PIN_MUX_5 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define P_PERIPHS_PIN_MUX_5 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_5)
#define PERIPHS_PIN_MUX_6 0x32 /* register.h:425 */
-#define P_PERIPHS_PIN_MUX_6 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_6)
+#define P_PERIPHS_PIN_MUX_6 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_6)
#define PERIPHS_PIN_MUX_7 0x33 /* register.h:426 */
-#define P_PERIPHS_PIN_MUX_7 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define P_PERIPHS_PIN_MUX_7 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_7)
#define PERIPHS_PIN_MUX_8 0x34 /* register.h:427 */
-#define P_PERIPHS_PIN_MUX_8 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_8)
+#define P_PERIPHS_PIN_MUX_8 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_8)
#define PERIPHS_PIN_MUX_9 0x35 /* register.h:428 */
-#define P_PERIPHS_PIN_MUX_9 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_9)
+#define P_PERIPHS_PIN_MUX_9 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_9)
#define PERIPHS_PIN_MUX_10 0x36 /* register.h:429 */
-#define P_PERIPHS_PIN_MUX_10 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_10)
+#define P_PERIPHS_PIN_MUX_10 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_10)
#define PERIPHS_PIN_MUX_11 0x37 /* register.h:430 */
-#define P_PERIPHS_PIN_MUX_11 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_11)
+#define P_PERIPHS_PIN_MUX_11 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_11)
#define PERIPHS_PIN_MUX_12 0x38 /* register.h:431 */
-#define P_PERIPHS_PIN_MUX_12 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_12)
+#define P_PERIPHS_PIN_MUX_12 PERIPHS_REG_ADDR(PERIPHS_PIN_MUX_12)
#define PAD_PULL_UP_REG0 0x3a
-#define P_PAD_PULL_UP_REG0 nCBUS_REG_ADDR(PAD_PULL_UP_REG0)
+#define P_PAD_PULL_UP_REG0 PERIPHS_REG_ADDR(PAD_PULL_UP_REG0)
#define PAD_PULL_UP_REG1 0x3d
-#define P_PAD_PULL_UP_REG1 nCBUS_REG_ADDR(PAD_PULL_UP_REG1)
+#define P_PAD_PULL_UP_REG1 PERIPHS_REG_ADDR(PAD_PULL_UP_REG1)
#define PAD_PULL_UP_REG2 0x3c
-#define P_PAD_PULL_UP_REG2 nCBUS_REG_ADDR(PAD_PULL_UP_REG2)
+#define P_PAD_PULL_UP_REG2 PERIPHS_REG_ADDR(PAD_PULL_UP_REG2)
#define PAD_PULL_UP_REG3 0x3d
-#define P_PAD_PULL_UP_REG3 nCBUS_REG_ADDR(PAD_PULL_UP_REG3)
+#define P_PAD_PULL_UP_REG3 PERIPHS_REG_ADDR(PAD_PULL_UP_REG3)
#define PAD_PULL_UP_REG4 0x3d
-#define P_PAD_PULL_UP_REG4 nCBUS_REG_ADDR(PAD_PULL_UP_REG4)
+#define P_PAD_PULL_UP_REG4 PERIPHS_REG_ADDR(PAD_PULL_UP_REG4)
#define PAD_PULL_UP_EN_REG0 0x48
-#define P_PAD_PULL_UP_EN_REG0 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG0)
+#define P_PAD_PULL_UP_EN_REG0 PERIPHS_REG_ADDR(PAD_PULL_UP_EN_REG0)
#define PAD_PULL_UP_EN_REG1 0x49
-#define P_PAD_PULL_UP_EN_REG1 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG1)
+#define P_PAD_PULL_UP_EN_REG1 PERIPHS_REG_ADDR(PAD_PULL_UP_EN_REG1)
#define PAD_PULL_UP_EN_REG2 0x4a
-#define P_PAD_PULL_UP_EN_REG2 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG2)
+#define P_PAD_PULL_UP_EN_REG2 PERIPHS_REG_ADDR(PAD_PULL_UP_EN_REG2)
#define PAD_PULL_UP_EN_REG3 0x4b
-#define P_PAD_PULL_UP_EN_REG3 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG3)
+#define P_PAD_PULL_UP_EN_REG3 PERIPHS_REG_ADDR(PAD_PULL_UP_EN_REG3)
#define PAD_PULL_UP_EN_REG4 0x4c
-#define P_PAD_PULL_UP_EN_REG4 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG4)
+#define P_PAD_PULL_UP_EN_REG4 PERIPHS_REG_ADDR(PAD_PULL_UP_EN_REG4)
-#define P_HHI_MEM_PD_REG0 (0xc883c000 + (0x40 << 2))
-#define P_HHI_VPU_MEM_PD_REG0 (0xc883c000 + (0x41 << 2))
-#define P_HHI_VPU_MEM_PD_REG1 (0xc883c000 + (0x42 << 2))
-#define P_HHI_AUD_DAC_CTRL (0xc883c000 + (0x44 << 2))
-#define P_HHI_VIID_CLK_DIV (0xc883c000 + (0x4a << 2))
-/* [19] -enable clk_div0 */
-/* [18:16] - cntl_clk_in_sel */
-#define P_HHI_VIID_CLK_CNTL (0xc883c000 + (0x4b << 2))
-#define P_HHI_VIID_DIVIDER_CNTL (0xc883c000 + (0x4c << 2))
+#define HHI_MEM_PD_REG0 0x40
+#define P_HHI_MEM_PD_REG0 HHI_REG_ADDR(HHI_MEM_PD_REG0)
+#define HHI_VPU_MEM_PD_REG0 0x41
+#define P_HHI_VPU_MEM_PD_REG0 HHI_REG_ADDR(HHI_VPU_MEM_PD_REG0)
+#define HHI_VPU_MEM_PD_REG1 0x42
+#define P_HHI_VPU_MEM_PD_REG1 HHI_REG_ADDR(HHI_VPU_MEM_PD_REG1)
+#define HHI_AUD_DAC_CTRL 0x44
+#define P_HHI_AUD_DAC_CTRL HHI_REG_ADDR(HHI_AUD_DAC_CTRL)
+#define HHI_VIID_CLK_DIV 0x4a
+#define P_HHI_VIID_CLK_DIV HHI_REG_ADDR(HHI_VIID_CLK_DIV)
+#define HHI_VIID_CLK_CNTL 0x4b
+#define P_HHI_VIID_CLK_CNTL HHI_REG_ADDR(HHI_VIID_CLK_CNTL)
+#define HHI_VIID_DIVIDER_CNTL 0x4c
+#define P_HHI_VIID_DIVIDER_CNTL HHI_REG_ADDR(HHI_VIID_DIVIDER_CNTL)
-/*
- *========================================================================
- * Global Control Registers (12'h000 - 12'h0ff)
- *
- *========================================================================
- * -----------------------------------------------
- * CBUS_BASE: RESET_CBUS_BASE = 0x11
- * -----------------------------------------------
- */
-#define P_VERSION_CTRL ((0x00 << 2) + 0xc1104400)
-#define P_RESET0_REGISTER ((0x01 << 2) + 0xc1104400)
-#define P_RESET1_REGISTER ((0x02 << 2) + 0xc1104400)
-#define P_RESET2_REGISTER ((0x03 << 2) + 0xc1104400)
-#define P_RESET3_REGISTER ((0x04 << 2) + 0xc1104400)
-#define P_RESET4_REGISTER ((0x05 << 2) + 0xc1104400)
-#define P_RESET5_REGISTER ((0x06 << 2) + 0xc1104400)
-#define P_RESET6_REGISTER ((0x07 << 2) + 0xc1104400)
-#define P_RESET7_REGISTER ((0x08 << 2) + 0xc1104400)
-#define P_RESET0_MASK ((0x10 << 2) + 0xc1104400)
-#define P_RESET1_MASK ((0x11 << 2) + 0xc1104400)
-#define P_RESET2_MASK ((0x12 << 2) + 0xc1104400)
-#define P_RESET3_MASK ((0x13 << 2) + 0xc1104400)
-#define P_RESET4_MASK ((0x14 << 2) + 0xc1104400)
-#define P_RESET5_MASK ((0x15 << 2) + 0xc1104400)
-#define P_RESET6_MASK ((0x16 << 2) + 0xc1104400)
+#define HHI_GCLK_MPEG0 0x50
+#define P_HHI_GCLK_MPEG0 HHI_REG_ADDR(HHI_GCLK_MPEG0)
+#define HHI_GCLK_MPEG1 0x51
+#define P_HHI_GCLK_MPEG1 HHI_REG_ADDR(HHI_GCLK_MPEG1)
+#define HHI_GCLK_MPEG2 0x52
+#define P_HHI_GCLK_MPEG2 HHI_REG_ADDR(HHI_GCLK_MPEG2)
+#define HHI_GCLK_OTHER 0x54
+#define P_HHI_GCLK_OTHER HHI_REG_ADDR(HHI_GCLK_OTHER)
+#define HHI_GCLK_AO 0x55
+#define P_HHI_GCLK_AO HHI_REG_ADDR(HHI_GCLK_AO)
+#define HHI_VID_CLK_DIV 0x59
+#define P_HHI_VID_CLK_DIV HHI_REG_ADDR(HHI_VID_CLK_DIV)
+#define HHI_VID_CLK_CNTL 0x5f
+#define P_HHI_VID_CLK_CNTL HHI_REG_ADDR(HHI_VID_CLK_CNTL)
+#define HHI_VID_CLK_CNTL2 0x65
+#define P_HHI_VID_CLK_CNTL2 HHI_REG_ADDR(HHI_VID_CLK_CNTL2)
+#define HHI_VID_DIVIDER_CNTL 0x66
+#define P_HHI_VID_DIVIDER_CNTL HHI_REG_ADDR(HHI_VID_DIVIDER_CNTL)
+#define HHI_VID_PLL_CLK_DIV 0x68
+#define P_HHI_VID_PLL_CLK_DIV HHI_REG_ADDR(HHI_VID_PLL_CLK_DIV)
+#define HHI_VPU_CLK_CNTL 0x6f
+#define P_HHI_VPU_CLK_CNTL HHI_REG_ADDR(HHI_VPU_CLK_CNTL)
+#define HHI_OTHER_PLL_CNTL 0x70
+#define P_HHI_OTHER_PLL_CNTL HHI_REG_ADDR(HHI_OTHER_PLL_CNTL)
+#define HHI_OTHER_PLL_CNTL2 0x71
+#define P_HHI_OTHER_PLL_CNTL2 HHI_REG_ADDR(HHI_OTHER_PLL_CNTL2)
+#define HHI_OTHER_PLL_CNTL3 0x72
+#define P_HHI_OTHER_PLL_CNTL3 HHI_REG_ADDR(HHI_OTHER_PLL_CNTL3)
+#define HHI_HDMI_CLK_CNTL 0x73
+#define P_HHI_HDMI_CLK_CNTL HHI_REG_ADDR(HHI_HDMI_CLK_CNTL)
+#define HHI_HDCP22_CLK_CNTL 0x7c
+#define P_HHI_HDCP22_CLK_CNTL HHI_REG_ADDR(HHI_HDCP22_CLK_CNTL)
+#define HHI_VAPBCLK_CNTL 0x7d
+#define P_HHI_VAPBCLK_CNTL HHI_REG_ADDR(HHI_VAPBCLK_CNTL)
+#define HHI_VP9DEC_CLK_CNTL 0x7e
+#define P_HHI_VP9DEC_CLK_CNTL HHI_REG_ADDR(HHI_VP9DEC_CLK_CNTL)
+#define HHI_HDMI_AFC_CNTL 0x7f
+#define P_HHI_HDMI_AFC_CNTL HHI_REG_ADDR(HHI_HDMI_AFC_CNTL)
+#define HHI_VPU_CLKB_CNTL 0x83
+#define P_HHI_VPU_CLKB_CNTL HHI_REG_ADDR(HHI_VPU_CLKB_CNTL)
+#define HHI_VDAC_CNTL0 0xbd
+#define P_HHI_VDAC_CNTL0 HHI_REG_ADDR(HHI_VDAC_CNTL0)
+#define HHI_VDAC_CNTL1 0xbe
+#define P_HHI_VDAC_CNTL1 HHI_REG_ADDR(HHI_VDAC_CNTL1)
+#define HHI_HDMI_PLL_CNTL 0xc8
+#define P_HHI_HDMI_PLL_CNTL HHI_REG_ADDR(HHI_HDMI_PLL_CNTL)
+#define HHI_HDMI_PLL_CNTL2 0xc9
+#define P_HHI_HDMI_PLL_CNTL2 HHI_REG_ADDR(HHI_HDMI_PLL_CNTL2)
+#define HHI_HDMI_PLL_CNTL3 0xca
+#define P_HHI_HDMI_PLL_CNTL3 HHI_REG_ADDR(HHI_HDMI_PLL_CNTL3)
+#define HHI_HDMI_PLL_CNTL4 0xcb
+#define P_HHI_HDMI_PLL_CNTL4 HHI_REG_ADDR(HHI_HDMI_PLL_CNTL4)
+#define HHI_HDMI_PLL_CNTL5 0xcc
+#define P_HHI_HDMI_PLL_CNTL5 HHI_REG_ADDR(HHI_HDMI_PLL_CNTL5)
+#define HHI_HDMI_PLL_CNTL6 0xcd
+#define P_HHI_HDMI_PLL_CNTL6 HHI_REG_ADDR(HHI_HDMI_PLL_CNTL6)
+#define HHI_HDMI_PLL_CNTL_I 0xce
+#define P_HHI_HDMI_PLL_CNTL_I HHI_REG_ADDR(HHI_HDMI_PLL_CNTL_I)
+#define HHI_HDMI_PLL_CNTL7 0xcf
+#define P_HHI_HDMI_PLL_CNTL7 HHI_REG_ADDR(HHI_HDMI_PLL_CNTL7)
+#define HHI_HDMI_PHY_CNTL0 0xe8
+#define P_HHI_HDMI_PHY_CNTL0 HHI_REG_ADDR(HHI_HDMI_PHY_CNTL0)
+#define HHI_HDMI_PHY_CNTL1 0xe9
+#define P_HHI_HDMI_PHY_CNTL1 HHI_REG_ADDR(HHI_HDMI_PHY_CNTL1)
+#define HHI_HDMI_PHY_CNTL2 0xea
+#define P_HHI_HDMI_PHY_CNTL2 HHI_REG_ADDR(HHI_HDMI_PHY_CNTL2)
+#define HHI_HDMI_PHY_CNTL3 0xeb
+#define P_HHI_HDMI_PHY_CNTL3 HHI_REG_ADDR(HHI_HDMI_PHY_CNTL3)
+#define HHI_VID_LOCK_CLK_CNTL 0xf2
+#define P_HHI_VID_LOCK_CLK_CNTL HHI_REG_ADDR(HHI_VID_LOCK_CLK_CNTL)
-/* Gated clock enables.
- * There are 64 enables for the MPEG clocks and 32 enables for other
- * clock domains.
- */
-#define P_HHI_GCLK_MPEG0 (0xc883c000 + (0x50 << 2))
-#define P_HHI_GCLK_MPEG1 (0xc883c000 + (0x51 << 2))
-#define P_HHI_GCLK_MPEG2 (0xc883c000 + (0x52 << 2))
-#define P_HHI_GCLK_OTHER (0xc883c000 + (0x54 << 2))
-#define P_HHI_GCLK_AO (0xc883c000 + (0x55 << 2))
-#define P_HHI_SYS_OSCIN_CNTL (0xc883c000 + (0x56 << 2))
-#define P_HHI_SYS_CPU_CLK_CNTL1 (0xc883c000 + (0x57 << 2))
-#define P_HHI_SYS_CPU_RESET_CNTL (0xc883c000 + (0x58 << 2))
-/* [7:0] - cntl_xd0 */
-#define P_HHI_VID_CLK_DIV (0xc883c000 + (0x59 << 2))
-#define P_HHI_MPEG_CLK_CNTL (0xc883c000 + (0x5d << 2))
-#define P_HHI_AUD_CLK_CNTL (0xc883c000 + (0x5e << 2))
-/* [18:16] - cntl_clk_in_sel */
-#define P_HHI_VID_CLK_CNTL (0xc883c000 + (0x5f << 2))
-#define P_HHI_WIFI_CLK_CNTL (0xc883c000 + (0x60 << 2))
-#define P_HHI_WIFI_PLL_CNTL (0xc883c000 + (0x61 << 2))
-#define P_HHI_WIFI_PLL_CNTL2 (0xc883c000 + (0x62 << 2))
-#define P_HHI_WIFI_PLL_CNTL3 (0xc883c000 + (0x63 << 2))
-#define P_HHI_AUD_CLK_CNTL2 (0xc883c000 + (0x64 << 2))
-#define P_HHI_VID_CLK_CNTL2 (0xc883c000 + (0x65 << 2))
-#define P_HHI_VID_DIVIDER_CNTL (0xc883c000 + (0x66 << 2))
-#define P_HHI_SYS_CPU_CLK_CNTL (0xc883c000 + (0x67 << 2))
-#define P_HHI_VID_PLL_CLK_DIV (0xc883c000 + (0x68 << 2))
-#define P_HHI_AUD_CLK_CNTL3 (0xc883c000 + (0x69 << 2))
-#define P_HHI_MALI_CLK_CNTL (0xc883c000 + (0x6c << 2))
-#define P_HHI_MIPI_PHY_CLK_CNTL (0xc883c000 + (0x6e << 2))
-#define P_HHI_VPU_CLK_CNTL (0xc883c000 + (0x6f << 2))
-#define P_HHI_OTHER_PLL_CNTL (0xc883c000 + (0x70 << 2))
-#define P_HHI_OTHER_PLL_CNTL2 (0xc883c000 + (0x71 << 2))
-#define P_HHI_OTHER_PLL_CNTL3 (0xc883c000 + (0x72 << 2))
-#define P_HHI_HDMI_CLK_CNTL (0xc883c000 + (0x73 << 2))
-#define P_HHI_DEMOD_CLK_CNTL (0xc883c000 + (0x74 << 2))
-#define P_HHI_SATA_CLK_CNTL (0xc883c000 + (0x75 << 2))
-#define P_HHI_ETH_CLK_CNTL (0xc883c000 + (0x76 << 2))
-#define P_HHI_CLK_DOUBLE_CNTL (0xc883c000 + (0x77 << 2))
-#define P_HHI_VDEC_CLK_CNTL (0xc883c000 + (0x78 << 2))
-#define P_HHI_VDEC2_CLK_CNTL (0xc883c000 + (0x79 << 2))
-#define P_HHI_VDEC3_CLK_CNTL (0xc883c000 + (0x7a << 2))
-#define P_HHI_VDEC4_CLK_CNTL (0xc883c000 + (0x7b << 2))
-#define P_HHI_HDCP22_CLK_CNTL (0xc883c000 + (0x7c << 2))
-#define P_HHI_VAPBCLK_CNTL (0xc883c000 + (0x7d << 2))
-#define P_HHI_VP9DEC_CLK_CNTL (0xc883c000 + (0x7e << 2))
-#define P_HHI_HDMI_AFC_CNTL (0xc883c000 + (0x7f << 2))
-#define P_HHI_HDMIRX_CLK_CNTL (0xc883c000 + (0x80 << 2))
-#define P_HHI_HDMIRX_AUD_CLK_CNTL (0xc883c000 + (0x81 << 2))
-#define P_HHI_EDP_APB_CLK_CNTL (0xc883c000 + (0x82 << 2))
-#define P_HHI_VPU_CLKB_CNTL (0xc883c000 + (0x83 << 2))
-#define P_HHI_VID_PLL_MOD_CNTL0 (0xc883c000 + (0x84 << 2))
-#define P_HHI_VID_PLL_MOD_LOW_TCNT (0xc883c000 + (0x85 << 2))
-#define P_HHI_VID_PLL_MOD_HIGH_TCNT (0xc883c000 + (0x86 << 2))
-#define P_HHI_VID_PLL_MOD_NOM_TCNT (0xc883c000 + (0x87 << 2))
-#define P_HHI_USB_CLK_CNTL (0xc883c000 + (0x88 << 2))
-#define P_HHI_32K_CLK_CNTL (0xc883c000 + (0x89 << 2))
-#define P_HHI_GEN_CLK_CNTL (0xc883c000 + (0x8a << 2))
-#define P_HHI_GEN_CLK_CNTL2 (0xc883c000 + (0x8b << 2))
-#define P_HHI_JTAG_CONFIG (0xc883c000 + (0x8e << 2))
-#define P_HHI_VAFE_CLKXTALIN_CNTL (0xc883c000 + (0x8f << 2))
-#define P_HHI_VAFE_CLKOSCIN_CNTL (0xc883c000 + (0x90 << 2))
-#define P_HHI_VAFE_CLKIN_CNTL (0xc883c000 + (0x91 << 2))
-#define P_HHI_TVFE_AUTOMODE_CLK_CNTL (0xc883c000 + (0x92 << 2))
-#define P_HHI_VAFE_CLKPI_CNTL (0xc883c000 + (0x93 << 2))
-#define P_HHI_VDIN_MEAS_CLK_CNTL (0xc883c000 + (0x94 << 2))
-#define P_HHI_PCM_CLK_CNTL (0xc883c000 + (0x96 << 2))
-#define P_HHI_NAND_CLK_CNTL (0xc883c000 + (0x97 << 2))
-#define P_HHI_ISP_LED_CLK_CNTL (0xc883c000 + (0x98 << 2))
-#define P_HHI_SD_EMMC_CLK_CNTL (0xc883c000 + (0x99 << 2))
-#define P_HHI_EDP_TX_PHY_CNTL0 (0xc883c000 + (0x9c << 2))
-#define P_HHI_EDP_TX_PHY_CNTL1 (0xc883c000 + (0x9d << 2))
-#define P_HHI_MPLL_CNTL (0xc883c000 + (0xa0 << 2))
-#define P_HHI_MPLL_CNTL2 (0xc883c000 + (0xa1 << 2))
-#define P_HHI_MPLL_CNTL3 (0xc883c000 + (0xa2 << 2))
-#define P_HHI_MPLL_CNTL4 (0xc883c000 + (0xa3 << 2))
-#define P_HHI_MPLL_CNTL5 (0xc883c000 + (0xa4 << 2))
-#define P_HHI_MPLL_CNTL6 (0xc883c000 + (0xa5 << 2))
-#define P_HHI_MPLL_CNTL7 (0xc883c000 + (0xa6 << 2))
-#define P_HHI_MPLL_CNTL8 (0xc883c000 + (0xa7 << 2))
-#define P_HHI_MPLL_CNTL9 (0xc883c000 + (0xa8 << 2))
-#define P_HHI_MPLL_CNTL10 (0xc883c000 + (0xa9 << 2))
-#define P_HHI_ADC_PLL_CNTL (0xc883c000 + (0xaa << 2))
-#define P_HHI_ADC_PLL_CNTL2 (0xc883c000 + (0xab << 2))
-#define P_HHI_ADC_PLL_CNTL3 (0xc883c000 + (0xac << 2))
-#define P_HHI_ADC_PLL_CNTL4 (0xc883c000 + (0xad << 2))
-#define P_HHI_ADC_PLL_CNTL_I (0xc883c000 + (0xae << 2))
-#define P_HHI_AUDCLK_PLL_CNTL (0xc883c000 + (0xb0 << 2))
-#define P_HHI_AUDCLK_PLL_CNTL2 (0xc883c000 + (0xb1 << 2))
-#define P_HHI_AUDCLK_PLL_CNTL3 (0xc883c000 + (0xb2 << 2))
-#define P_HHI_AUDCLK_PLL_CNTL4 (0xc883c000 + (0xb3 << 2))
-#define P_HHI_AUDCLK_PLL_CNTL5 (0xc883c000 + (0xb4 << 2))
-#define P_HHI_AUDCLK_PLL_CNTL6 (0xc883c000 + (0xb5 << 2))
-#define P_HHI_L2_DDR_CLK_CNTL (0xc883c000 + (0xb6 << 2))
-#define P_HHI_MPLL3_CNTL0 (0xc883c000 + (0xb8 << 2))
-#define P_HHI_MPLL3_CNTL1 (0xc883c000 + (0xb9 << 2))
-#define P_HHI_VDAC_CNTL0 (0xc883c000 + (0xbd << 2))
-#define P_HHI_VDAC_CNTL1 (0xc883c000 + (0xbe << 2))
-#define P_HHI_SYS_PLL_CNTL (0xc883c000 + (0xc0 << 2))
-#define P_HHI_SYS_PLL_CNTL2 (0xc883c000 + (0xc1 << 2))
-#define P_HHI_SYS_PLL_CNTL3 (0xc883c000 + (0xc2 << 2))
-#define P_HHI_SYS_PLL_CNTL4 (0xc883c000 + (0xc3 << 2))
-#define P_HHI_SYS_PLL_CNTL5 (0xc883c000 + (0xc4 << 2))
-#define P_HHI_DPLL_TOP_I (0xc883c000 + (0xc6 << 2))
-#define P_HHI_DPLL_TOP2_I (0xc883c000 + (0xc7 << 2))
-#define P_HHI_HDMI_PLL_CNTL (0xc883c000 + (0xc8 << 2))
-#define P_HHI_HDMI_PLL_CNTL2 (0xc883c000 + (0xc9 << 2))
-#define P_HHI_HDMI_PLL_CNTL3 (0xc883c000 + (0xca << 2))
-#define P_HHI_HDMI_PLL_CNTL4 (0xc883c000 + (0xcb << 2))
-#define P_HHI_HDMI_PLL_CNTL5 (0xc883c000 + (0xcc << 2))
-#define P_HHI_HDMI_PLL_CNTL6 (0xc883c000 + (0xcd << 2))
-#define P_HHI_HDMI_PLL_CNTL_I (0xc883c000 + (0xce << 2))
-#define P_HHI_HDMI_PLL_CNTL7 (0xc883c000 + (0xcf << 2))
-#define P_HHI_DSI_LVDS_EDP_CNTL0 (0xc883c000 + (0xd1 << 2))
-#define P_HHI_DSI_LVDS_EDP_CNTL1 (0xc883c000 + (0xd2 << 2))
-#define P_HHI_CSI_PHY_CNTL0 (0xc883c000 + (0xd3 << 2))
-#define P_HHI_CSI_PHY_CNTL1 (0xc883c000 + (0xd4 << 2))
-#define P_HHI_CSI_PHY_CNTL2 (0xc883c000 + (0xd5 << 2))
-#define P_HHI_CSI_PHY_CNTL3 (0xc883c000 + (0xd6 << 2))
-#define P_HHI_CSI_PHY_CNTL4 (0xc883c000 + (0xd7 << 2))
-#define P_HHI_DIF_CSI_PHY_CNTL0 (0xc883c000 + (0xd8 << 2))
-#define P_HHI_DIF_CSI_PHY_CNTL1 (0xc883c000 + (0xd9 << 2))
-#define P_HHI_DIF_CSI_PHY_CNTL2 (0xc883c000 + (0xda << 2))
-#define P_HHI_DIF_CSI_PHY_CNTL3 (0xc883c000 + (0xdb << 2))
-#define P_HHI_DIF_CSI_PHY_CNTL4 (0xc883c000 + (0xdc << 2))
-#define P_HHI_DIF_CSI_PHY_CNTL5 (0xc883c000 + (0xdd << 2))
-#define P_HHI_LVDS_TX_PHY_CNTL0 (0xc883c000 + (0xde << 2))
-#define P_HHI_LVDS_TX_PHY_CNTL1 (0xc883c000 + (0xdf << 2))
-#define P_HHI_VID2_PLL_CNTL (0xc883c000 + (0xe0 << 2))
-#define P_HHI_VID2_PLL_CNTL2 (0xc883c000 + (0xe1 << 2))
-#define P_HHI_VID2_PLL_CNTL3 (0xc883c000 + (0xe2 << 2))
-#define P_HHI_VID2_PLL_CNTL4 (0xc883c000 + (0xe3 << 2))
-#define P_HHI_VID2_PLL_CNTL5 (0xc883c000 + (0xe4 << 2))
-#define P_HHI_VID2_PLL_CNTL_I (0xc883c000 + (0xe5 << 2))
-#define P_HHI_HDMI_PHY_CNTL0 (0xc883c000 + (0xe8 << 2))
-#define P_HHI_HDMI_PHY_CNTL1 (0xc883c000 + (0xe9 << 2))
-#define P_HHI_HDMI_PHY_CNTL2 (0xc883c000 + (0xea << 2))
-#define P_HHI_HDMI_PHY_CNTL3 (0xc883c000 + (0xeb << 2))
-#define P_HHI_VID_LOCK_CLK_CNTL (0xc883c000 + (0xf2 << 2))
-#define P_HHI_ATV_DMD_SYS_CLK_CNTL (0xc883c000 + (0xf3 << 2))
-#define P_HHI_BT656_CLK_CNTL (0xc883c000 + (0xf5 << 2))
-#define P_HHI_SAR_CLK_CNTL (0xc883c000 + (0xf6 << 2))
-#define P_HHI_HDMIRX_AUD_PLL_CNTL (0xc883c000 + (0xf8 << 2))
-#define P_HHI_HDMIRX_AUD_PLL_CNTL2 (0xc883c000 + (0xf9 << 2))
-#define P_HHI_HDMIRX_AUD_PLL_CNTL3 (0xc883c000 + (0xfa << 2))
-#define P_HHI_HDMIRX_AUD_PLL_CNTL4 (0xc883c000 + (0xfb << 2))
-#define P_HHI_HDMIRX_AUD_PLL_CNTL5 (0xc883c000 + (0xfc << 2))
-#define P_HHI_HDMIRX_AUD_PLL_CNTL6 (0xc883c000 + (0xfd << 2))
-#define P_HHI_HDMIRX_AUD_PLL_CNTL_I (0xc883c000 + (0xfe << 2))
+#define VERSION_CTRL 0x00
+#define P_VERSION_CTRL RESET_CBUS_REG_ADDR(VERSION_CTRL)
+#define RESET0_REGISTER 0x01
+#define P_RESET0_REGISTER RESET_CBUS_REG_ADDR(RESET0_REGISTER)
+#define RESET1_REGISTER 0x02
+#define P_RESET1_REGISTER RESET_CBUS_REG_ADDR(RESET1_REGISTER)
+#define RESET2_REGISTER 0x03
+#define P_RESET2_REGISTER RESET_CBUS_REG_ADDR(RESET2_REGISTER)
+#define RESET3_REGISTER 0x04
+#define P_RESET3_REGISTER RESET_CBUS_REG_ADDR(RESET3_REGISTER)
+#define RESET4_REGISTER 0x05
+#define P_RESET4_REGISTER RESET_CBUS_REG_ADDR(RESET4_REGISTER)
+#define RESET5_REGISTER 0x06
+#define P_RESET5_REGISTER RESET_CBUS_REG_ADDR(RESET5_REGISTER)
+#define RESET6_REGISTER 0x07
+#define P_RESET6_REGISTER RESET_CBUS_REG_ADDR(RESET6_REGISTER)
+#define RESET7_REGISTER 0x08
+#define P_RESET7_REGISTER RESET_CBUS_REG_ADDR(RESET7_REGISTER)
+#define RESET0_MASK 0x10
+#define P_RESET0_MASK RESET_CBUS_REG_ADDR(RESET0_MASK)
+#define RESET1_MASK 0x11
+#define P_RESET1_MASK RESET_CBUS_REG_ADDR(RESET1_MASK)
+#define RESET2_MASK 0x12
+#define P_RESET2_MASK RESET_CBUS_REG_ADDR(RESET2_MASK)
+#define RESET3_MASK 0x13
+#define P_RESET3_MASK RESET_CBUS_REG_ADDR(RESET3_MASK)
+#define RESET4_MASK 0x14
+#define P_RESET4_MASK RESET_CBUS_REG_ADDR(RESET4_MASK)
+#define RESET5_MASK 0x15
+#define P_RESET5_MASK RESET_CBUS_REG_ADDR(RESET5_MASK)
+#define RESET6_MASK 0x16
+#define P_RESET6_MASK RESET_CBUS_REG_ADDR(RESET6_MASK)
#define AIU_HDMI_CLK_DATA_CTRL 0x152a /* register.h:2466 */
#define P_AIU_HDMI_CLK_DATA_CTRL CBUS_REG_ADDR(AIU_HDMI_CLK_DATA_CTRL)
-
#define ISA_DEBUG_REG0 0x2600
#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0)
+
#define VENC_DVI_SETTING 0x1b62 /* register.h:8014 */
#define P_VENC_DVI_SETTING VCBUS_REG_ADDR(VENC_DVI_SETTING)
#define VPP_POSTBLEND_H_SIZE 0x1d21
#define P_VPP_POSTBLEND_H_SIZE VCBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE)
-/* [3:2] cntl_viu2_sel_venc: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. */
-/* [1:0] cntl_viu1_sel_venc: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. */
+
#define VPU_VIU_VENC_MUX_CTRL 0x271a /* register.h:9214 */
#define P_VPU_VIU_VENC_MUX_CTRL VCBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL)
#define VPU_HDMI_SETTING 0x271b /* register.h:9229 */
#define P_VPU_HDMI_DITH_CNTL VCBUS_REG_ADDR(VPU_HDMI_DITH_CNTL)
/* c_always_on_pointer.h:71 */
-#define AO_RTI_PULL_UP_REG ((0x00 << 10) | (0x0B << 2))
+#define AO_RTI_PULL_UP_REG 0x0B
#define P_AO_RTI_PULL_UP_REG AOBUS_REG_ADDR(AO_RTI_PULL_UP_REG)
-#define AO_RTI_PIN_MUX_REG ((0x00 << 10) | (0x05 << 2))
+#define AO_RTI_PIN_MUX_REG 0x05
#define P_AO_RTI_PIN_MUX_REG AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG)
-#define AO_RTI_PIN_MUX_REG2 ((0x00 << 10) | (0x06 << 2))
+#define AO_RTI_PIN_MUX_REG2 0x06
#define P_AO_RTI_PIN_MUX_REG2 AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG2)
-#define AO_CRT_CLK_CNTL1 ((0x00 << 10) | (0x1A << 2))
+#define AO_CRT_CLK_CNTL1 0x1A
#define P_AO_CRT_CLK_CNTL1 AOBUS_REG_ADDR(AO_CRT_CLK_CNTL1)
-#define AO_DEBUG_REG0 ((0x00 << 10) | (0x28 << 2))
+#define AO_DEBUG_REG0 0x28
#define P_AO_DEBUG_REG0 AOBUS_REG_ADDR(AO_DEBUG_REG0)
-#define AO_DEBUG_REG1 ((0x00 << 10) | (0x29 << 2))
+#define AO_DEBUG_REG1 0x29
#define P_AO_DEBUG_REG1 AOBUS_REG_ADDR(AO_DEBUG_REG1)
-#define AO_DEBUG_REG2 ((0x00 << 10) | (0x2a << 2))
+#define AO_DEBUG_REG2 0x2a
#define P_AO_DEBUG_REG2 AOBUS_REG_ADDR(AO_DEBUG_REG2)
-#define AO_DEBUG_REG3 ((0x00 << 10) | (0x2b << 2))
+#define AO_DEBUG_REG3 0x2b
#define P_AO_DEBUG_REG3 AOBUS_REG_ADDR(AO_DEBUG_REG3)
+#define AO_RTI_GEN_PWR_SLEEP0 0x3a
+#define P_AO_RTI_GEN_PWR_SLEEP0 AOBUS_REG_ADDR(AO_RTI_GEN_PWR_SLEEP0)
-#define P_AO_RTI_GEN_PWR_SLEEP0 (0xc8100000 + (0x3a << 2))
+#define HDMITX_ADDR_PORT_SEC 0x00
+#define P_HDMITX_ADDR_PORT_SEC HDMITX_SEC_REG_ADDR(HDMITX_ADDR_PORT_SEC)
+#define HDMITX_DATA_PORT_SEC 0x01
+#define P_HDMITX_DATA_PORT_SEC HDMITX_SEC_REG_ADDR(HDMITX_DATA_PORT_SEC)
+#define HDMITX_CTRL_PORT_SEC 0x02
+#define P_HDMITX_CTRL_PORT_SEC HDMITX_SEC_REG_ADDR(HDMITX_CTRL_PORT_SEC)
+#define HDMITX_ADDR_PORT 0x00
+#define P_HDMITX_ADDR_PORT HDMITX_REG_ADDR(HDMITX_ADDR_PORT)
+#define HDMITX_DATA_PORT 0x01
+#define P_HDMITX_DATA_PORT HDMITX_REG_ADDR(HDMITX_DATA_PORT)
+#define HDMITX_CTRL_PORT 0x02
+#define P_HDMITX_CTRL_PORT HDMITX_REG_ADDR(HDMITX_CTRL_PORT)
-#define P_HDMITX_ADDR_PORT_SEC 0xda83a000
-#define P_HDMITX_DATA_PORT_SEC 0xda83a004
-#define P_HDMITX_CTRL_PORT_SEC 0xda83a008
-/* secure address P_HDMITX_ADDR_PORT 0xda83a000 */
-#define P_HDMITX_ADDR_PORT 0xc883a000
-#define P_HDMITX_DATA_PORT 0xc883a004
-#define P_HDMITX_CTRL_PORT 0xc883a008
+#define ELP_ESM_HPI_REG_BASE 0x0
+#define P_ELP_ESM_HPI_REG_BASE ELP_ESM_REG_ADDR(ELP_ESM_HPI_REG_BASE)
-#define P_ELP_ESM_HPI_REG_BASE 0xd0044000
#endif
unsigned int phy_addr;
unsigned int size;
void __iomem *p;
- int flag;
};
-static struct reg_map reg_maps[] = {
- { /* CBUS */
- .phy_addr = 0xc0800000,
+/* For gxb/gxl/gxm */
+static struct reg_map reg_maps_def[] = {
+ [CBUS_REG_IDX] = { /* CBUS */
+ .phy_addr = 0xc1100000,
.size = 0xa00000,
},
- { /* RESET */
- .phy_addr = 0xc1104400,
- .size = 0x100,
+ [PERIPHS_REG_IDX] = { /* PERIPHS */
+ .phy_addr = 0xc8834400,
+ .size = 0x200,
},
- { /* RTI */
+ [VCBUS_REG_IDX] = { /* VPU */
+ .phy_addr = 0xd0100000,
+ .size = 0x40000,
+ },
+ [AOBUS_REG_IDX] = { /* RTI */
.phy_addr = 0xc8100000,
.size = 0x100000,
},
- { /* PERIPHS */
- .phy_addr = 0xc8834000,
+ [HHI_REG_IDX] = { /* HIU */
+ .phy_addr = 0xc883c000,
+ .size = 0x2000,
+ },
+ [RESET_CBUS_REG_IDX] = { /* RESET */
+ .phy_addr = 0xc1104400,
+ .size = 0x100,
+ },
+ [HDMITX_SEC_REG_IDX] = { /* HDMITX SECURE */
+ .phy_addr = 0xda83a000,
.size = 0x2000,
},
- { /* HDMITX NON-SECURE*/
+ [HDMITX_REG_IDX] = { /* HDMITX NON-SECURE*/
.phy_addr = 0xc883a000,
.size = 0x2000,
},
- { /* HIU */
- .phy_addr = 0xc883c000,
+ [ELP_ESM_REG_IDX] = {
+ .phy_addr = 0xd0044000,
+ .size = 0x100,
+ },
+};
+
+/* For txlx */
+static struct reg_map reg_maps_txlx[] = {
+ [CBUS_REG_IDX] = { /* CBUS */
+ .phy_addr = 0xffd00000,
+ .size = 0xa00000,
+ },
+ [PERIPHS_REG_IDX] = { /* PERIPHS */
+ .phy_addr = 0xff634400,
.size = 0x2000,
},
- { /* VPU */
- .phy_addr = 0xd0100000,
+ [VCBUS_REG_IDX] = { /* VPU */
+ .phy_addr = 0xff900000,
.size = 0x40000,
},
- { /* HDMITX SECURE */
- .phy_addr = 0xda83a000,
+ [AOBUS_REG_IDX] = { /* RTI */
+ .phy_addr = 0xff800000,
+ .size = 0x100000,
+ },
+ [HHI_REG_IDX] = { /* HIU */
+ .phy_addr = 0xff63c000,
+ .size = 0x2000,
+ },
+ [RESET_CBUS_REG_IDX] = { /* RESET */
+ .phy_addr = 0xffd01000,
+ .size = 0x100,
+ },
+ [HDMITX_SEC_REG_IDX] = { /* HDMITX SECURE */
+ .phy_addr = 0xff63a000,
+ .size = 0x2000,
+ },
+ [HDMITX_REG_IDX] = { /* HDMITX NON-SECURE*/
+ .phy_addr = 0xff63a000,
.size = 0x2000,
},
+ [ELP_ESM_REG_IDX] = {
+ .phy_addr = 0xffe01000,
+ .size = 0x100,
+ },
};
-static int in_reg_maps_idx(unsigned int addr)
+static struct reg_map *map;
+
+void init_reg_map(unsigned int type)
{
int i;
- for (i = 0; i < ARRAY_SIZE(reg_maps); i++) {
- if ((addr >= reg_maps[i].phy_addr) &&
- (addr < (reg_maps[i].phy_addr + reg_maps[i].size))) {
- return i;
- }
+ switch (type) {
+ case 1:
+ map = reg_maps_txlx;
+ break;
+ default:
+ map = reg_maps_def;
+ break;
}
- return -1;
-}
-
-static int check_map_flag(unsigned int addr)
-{
- int idx;
-
- idx = in_reg_maps_idx(addr);
- if ((idx != -1) && (reg_maps[idx].flag))
- return 1;
- return 0;
-}
-
-void init_reg_map(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(reg_maps); i++) {
- reg_maps[i].p = ioremap(reg_maps[i].phy_addr, reg_maps[i].size);
- if (!reg_maps[i].p) {
+ for (i = 0; i < REG_IDX_END; i++) {
+ map[i].p = ioremap(map[i].phy_addr, map[i].size);
+ if (!map[i].p) {
pr_info("hdmitx20: failed Mapped PHY: 0x%x\n",
- reg_maps[i].phy_addr);
+ map[i].phy_addr);
} else {
- reg_maps[i].flag = 1;
pr_info("hdmitx20: Mapped PHY: 0x%x\n",
- reg_maps[i].phy_addr);
+ map[i].phy_addr);
}
}
}
+unsigned int get_hdcp22_base(void)
+{
+ if (map)
+ return map[ELP_ESM_REG_IDX].phy_addr;
+ else
+ return reg_maps_def[ELP_ESM_REG_IDX].phy_addr;
+}
+
+#define TO_PHY_ADDR(addr) \
+ (map[(addr) >> BASE_REG_OFFSET].phy_addr + \
+ ((addr) & (((1 << BASE_REG_OFFSET) - 1))))
+#define TO_PMAP_ADDR(addr) \
+ (map[(addr) >> BASE_REG_OFFSET].p + \
+ ((addr) & (((1 << BASE_REG_OFFSET) - 1))))
+
unsigned int hd_read_reg(unsigned int addr)
{
- int ret = 0;
- int idx = in_reg_maps_idx(addr);
unsigned int val = 0;
- unsigned int type = (addr >> OFFSET);
- unsigned int reg = addr & ((1 << OFFSET) - 1);
+ unsigned int paddr = TO_PHY_ADDR(addr);
- if ((idx != -1) && check_map_flag(addr)) {
- val = readl(reg_maps[idx].p + (addr - reg_maps[idx].phy_addr));
- goto end;
- }
-
- ret = aml_reg_read(type, reg, &val);
+ val = readl(TO_PMAP_ADDR(addr));
- if (ret < 0) {
- pr_info("Rd[0x%x] Error\n", addr);
- return val;
- }
-end:
if (dbg_en)
- pr_info("Rd[0x%x] 0x%x\n", addr, val);
+ pr_info("Rd[0x%x] 0x%x\n", paddr, val);
+
return val;
}
void hd_write_reg(unsigned int addr, unsigned int val)
{
- int ret = 0;
- int idx = in_reg_maps_idx(addr);
- unsigned int type = (addr >> OFFSET);
- unsigned int reg = addr & ((1 << OFFSET) - 1);
-
- if ((idx != -1) && check_map_flag(addr)) {
- writel(val, reg_maps[idx].p + (addr - reg_maps[idx].phy_addr));
- goto end;
- }
+ unsigned int paddr = TO_PHY_ADDR(addr);
- ret = aml_reg_write(type, reg, val);
-
- if (ret < 0) {
- pr_info("Wr[0x%x] 0x%x Error\n", addr, val);
- return;
- }
+ writel(val, TO_PMAP_ADDR(addr));
-end:
if (dbg_en)
- pr_info("Wr[0x%x] 0x%x\n", addr, val);
+ pr_info("Wr[0x%x] 0x%x\n", paddr, val);
}
void hd_set_reg_bits(unsigned int addr, unsigned int value,
unsigned int data = 0;
unsigned long offset = (addr & DWC_OFFSET_MASK) >> 24;
unsigned long flags, fiq_flag;
-
if (addr & SEC_OFFSET) {
addr = addr & 0xffff;
sec_reg_write((unsigned int *)(unsigned long)
- (P_HDMITX_ADDR_PORT_SEC + offset), addr);
+ TO_PHY_ADDR(P_HDMITX_ADDR_PORT_SEC + offset), addr);
sec_reg_write((unsigned int *)(unsigned long)
- (P_HDMITX_ADDR_PORT_SEC + offset), addr);
+ TO_PHY_ADDR(P_HDMITX_ADDR_PORT_SEC + offset), addr);
data = sec_reg_read((unsigned int *)(unsigned long)
- (P_HDMITX_DATA_PORT_SEC + offset));
+ TO_PHY_ADDR(P_HDMITX_DATA_PORT_SEC + offset));
} else {
addr = addr & 0xffff;
spin_lock_irqsave(®_lock, flags);
if (addr & SEC_OFFSET) {
addr = addr & 0xffff;
sec_reg_write((unsigned int *)(unsigned long)
- (P_HDMITX_ADDR_PORT_SEC + offset), addr);
+ TO_PHY_ADDR(P_HDMITX_ADDR_PORT_SEC + offset), addr);
sec_reg_write((unsigned int *)(unsigned long)
- (P_HDMITX_ADDR_PORT_SEC + offset), addr);
+ TO_PHY_ADDR(P_HDMITX_ADDR_PORT_SEC + offset), addr);
sec_reg_write((unsigned int *)(unsigned long)
- (P_HDMITX_DATA_PORT_SEC + offset), data);
+ TO_PHY_ADDR(P_HDMITX_DATA_PORT_SEC + offset), data);
} else {
addr = addr & 0xffff;
spin_lock_irqsave(®_lock, flags);
unsigned int mask)
{
unsigned long rd_data;
-
rd_data = hdmitx_rd_reg(addr);
if ((rd_data | mask) != (exp_data | mask)) {
pr_info("HDMITX-DWC addr=0x%04x rd_data=0x%02x\n",
void hdcp22_wr_reg(uint32_t addr, uint32_t data)
{
sec_reg_write((unsigned int *)(unsigned long)
- (P_ELP_ESM_HPI_REG_BASE + addr), data);
+ TO_PHY_ADDR(P_ELP_ESM_HPI_REG_BASE + addr), data);
}
uint32_t hdcp22_rd_reg(uint32_t addr)
{
return (uint32_t)sec_reg_read((unsigned int *)(unsigned long)
- (P_ELP_ESM_HPI_REG_BASE + addr));
+ TO_PHY_ADDR(P_ELP_ESM_HPI_REG_BASE + addr));
}
MODULE_PARM_DESC(dbg_en, "\n debug_level\n");
module_param(dbg_en, int, 0664);
+
COLORDEPTH_30B = 5,
COLORDEPTH_36B = 6,
COLORDEPTH_48B = 7,
+ COLORDEPTH_RESERVED,
};
enum hdmi_color_space {
unsigned char hdr_lum_max;
unsigned char hdr_lum_avg;
unsigned char hdr_lum_min;
- unsigned char ReceiverBrandName[4];
+ unsigned char IDManufacturerName[4];
+ unsigned char IDProductCode[2];
+ unsigned char IDSerialNumber[4];
unsigned char ReceiverProductName[16];
unsigned char manufacture_week;
unsigned char manufacture_year;
+ unsigned char physcial_weight;
+ unsigned char physcial_height;
unsigned char edid_version;
unsigned char edid_revision;
unsigned int ColorDeepSupport;
u32 sync_num_dec;
u32 sync_den_dec;
};
+
#define EDID_MAX_BLOCK 4
#define HDMI_TMP_BUF_SIZE 1024
struct hdmitx_dev {
struct task_struct *task_hdcp;
struct notifier_block nb;
struct workqueue_struct *hdmi_wq;
+ struct workqueue_struct *rxsense_wq;
struct device *hdtx_dev;
struct delayed_work work_hpd_plugin;
struct delayed_work work_hpd_plugout;
+ struct delayed_work work_rxsense;
struct work_struct work_internal_intr;
struct work_struct work_hdr;
+ struct delayed_work work_do_hdcp;
+#ifdef CONFIG_AML_HDMI_TX_14
+ struct delayed_work cec_work;
+#endif
struct timer_list hdcp_timer;
const char *hpd_pin;
const char *ddc_pin;
+ int chip_type;
int hdcp_try_times;
/* -1, no hdcp; 0, NULL; 1, 1.4; 2, 2.2 */
int hdcp_mode;
+ int hdcp_bcaps_repeater;
int ready; /* 1, hdmi stable output, others are 0 */
int hdcp_hpd_stick; /* 1 not init & reset at plugout */
struct {
unsigned int output_blank_flag;
unsigned int audio_notify_flag;
unsigned int audio_step;
+ unsigned int repeater_tx;
+ /* 0.1% clock shift, 1080p60hz->59.94hz */
unsigned int frac_rate_policy;
+ unsigned int rxsense_policy;
/* configure for I2S: 8ch in, 2ch out */
/* 0: default setting 1:ch0/1 2:ch2/3 3:ch4/5 4:ch6/7 */
unsigned int aud_output_ch;
#define HDCP14_OFF 0x2
#define HDCP22_ON 0x3
#define HDCP22_OFF 0x4
-#define DDC_HDCP_BYP (CMD_DDC_OFFSET + 0x03)
#define DDC_IS_HDCP_ON (CMD_DDC_OFFSET + 0x04)
#define DDC_HDCP_GET_AKSV (CMD_DDC_OFFSET + 0x05)
#define DDC_HDCP_GET_BKSV (CMD_DDC_OFFSET + 0x06)
#define DDC_HDCP_14_LSTORE (CMD_DDC_OFFSET + 0x0f)
#define DDC_HDCP_22_LSTORE (CMD_DDC_OFFSET + 0x10)
#define DDC_SCDC_DIV40_SCRAMB (CMD_DDC_OFFSET + 0x20)
+#define DDC_HDCP14_GET_BCAPS_RP (CMD_DDC_OFFSET + 0x30)
/***********************************************************************
* CONFIG CONTROL //CntlConfig
#define YCC_RANGE_LIM 0
#define YCC_RANGE_FUL 1
#define YCC_RANGE_RSVD 2
+#define CONF_VIDEO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x04)
+#define VIDEO_MUTE 0x1
+#define VIDEO_UNMUTE 0x2
/***********************************************************************
* MISC control, hpd, hpll //CntlMisc
#define TMDS_PHY_ENABLE 0x1
#define TMDS_PHY_DISABLE 0x2
#define MISC_VIID_IS_USING (CMD_MISC_OFFSET + 0x05)
+#define MISC_CONF_MODE420 (CMD_MISC_OFFSET + 0x06)
#define MISC_TMDS_CLK_DIV40 (CMD_MISC_OFFSET + 0x07)
#define MISC_COMP_HPLL (CMD_MISC_OFFSET + 0x08)
#define COMP_HPLL_SET_OPTIMISE_HPLL1 0x1
#define MISC_HPLL_FAKE (CMD_MISC_OFFSET + 0x0c)
#define MISC_ESM_RESET (CMD_MISC_OFFSET + 0x0d)
#define MISC_HDCP_CLKDIS (CMD_MISC_OFFSET + 0x0e)
+#define MISC_TMDS_RXSENSE (CMD_MISC_OFFSET + 0x0f)
/***********************************************************************
* Get State //GetState
/* reduce a little time, previous setting is 4000/10 */
#define AUTH_PROCESS_TIME (1000/100)
-#define HDMITX_VER "2014May6"
+#define HDMITX_VER "20170622"
/***********************************************************************
* hdmitx protocol level interface
extern int hdmitx_event_notifier_regist(struct notifier_block *nb);
extern int hdmitx_event_notifier_unregist(struct notifier_block *nb);
extern void hdmitx_event_notify(unsigned long state, void *arg);
+extern void hdmitx_hdcp_status(int hdmi_authenticated);
#else
static inline struct hdmitx_dev *get_hdmitx_device(void)
{
extern struct vinfo_s *hdmi_get_current_vinfo(void);
void phy_pll_off(void);
+extern int get_hpd_state(void);
+void hdmitx_hdcp_do_work(struct hdmitx_dev *hdev);
/***********************************************************************
* hdmitx hardware level interface
extern void HDMITX_Meson_Init(struct hdmitx_dev *hdmitx_device);
extern unsigned char hdmi_audio_off_flag;
+extern unsigned int get_hdcp22_base(void);
/*
* hdmitx_audio_mute_op() is used by external driver call
* flag: 0: audio off 1: audio_on
* 2: for EDID auto mode
*/
extern void hdmitx_audio_mute_op(unsigned int flag);
+extern void hdmitx_video_mute_op(unsigned int flag);
#define HDMITX_HWCMD_MUX_HPD_IF_PIN_HIGH 0x3
#define HDMITX_HWCMD_TURNOFF_HDMIHW 0x4
projects / platform / kernel / linux-amlogic.git / commitdiff