drm/amdgpu: cleanup idh event/req for NV headers
authorMonk Liu <Monk.Liu@amd.com>
Tue, 3 Mar 2020 08:40:00 +0000 (16:40 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Apr 2020 18:44:43 +0000 (14:44 -0400)
1) drop the headers from AI in mxgpu_nv.c, should refer to mxgpu_nv.h

2) the IDH_EVENT_MAX is not used and not aligned with host side
   so drop it
3) the IDH_TEXT_MESSAG was provided in host but not defined in guest

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h

index 37dbe0f..52a6975 100644 (file)
@@ -46,7 +46,8 @@ enum idh_event {
        IDH_SUCCESS,
        IDH_FAIL,
        IDH_QUERY_ALIVE,
-       IDH_EVENT_MAX
+
+       IDH_TEXT_MESSAGE = 255,
 };
 
 extern const struct amdgpu_virt_ops xgpu_ai_virt_ops;
index 237fa5e..d9ce12c 100644 (file)
@@ -30,7 +30,6 @@
 #include "navi10_ih.h"
 #include "soc15_common.h"
 #include "mxgpu_nv.h"
-#include "mxgpu_ai.h"
 
 static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
 {
index 99b15f6..c80bbc7 100644 (file)
 #define NV_MAILBOX_POLL_MSG_TIMEDOUT   12000
 #define NV_MAILBOX_POLL_FLR_TIMEDOUT   500
 
+enum idh_request {
+       IDH_REQ_GPU_INIT_ACCESS = 1,
+       IDH_REL_GPU_INIT_ACCESS,
+       IDH_REQ_GPU_FINI_ACCESS,
+       IDH_REL_GPU_FINI_ACCESS,
+       IDH_REQ_GPU_RESET_ACCESS,
+
+       IDH_LOG_VF_ERROR       = 200,
+};
+
+enum idh_event {
+       IDH_CLR_MSG_BUF = 0,
+       IDH_READY_TO_ACCESS_GPU,
+       IDH_FLR_NOTIFICATION,
+       IDH_FLR_NOTIFICATION_CMPL,
+       IDH_SUCCESS,
+       IDH_FAIL,
+       IDH_QUERY_ALIVE,
+
+       IDH_TEXT_MESSAGE = 255,
+};
+
 extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;
 
 void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);
index f13dc6c..713ee66 100644 (file)
@@ -43,7 +43,8 @@ enum idh_event {
        IDH_READY_TO_ACCESS_GPU,
        IDH_FLR_NOTIFICATION,
        IDH_FLR_NOTIFICATION_CMPL,
-       IDH_EVENT_MAX
+
+       IDH_TEXT_MESSAGE = 255
 };
 
 extern const struct amdgpu_virt_ops xgpu_vi_virt_ops;