drm/amd/powerplay: set FCLK DPM for sienna_cichlid

Support for FCLK DPM for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 4a60b688d3c3c64e9fb601a22f5e104e02456bf2..f1aeef79e204f857067ede5b73a4f3b30db7a597 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -43,7 +43,8 @@
 #define SMC_DPM_FEATURE ( \
        FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
        FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
-       FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))
+       FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
+       FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
 
 #define MSG_MAP(msg, index) \
        [SMU_MSG_##msg] = {1, (index)}
@@ -267,7 +268,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 
        memset(feature_mask, 0, sizeof(uint32_t) * num);
 
-       *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
+       *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
+                               | FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
 
        if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);