Add the AMD SSE4a and LZCNT instructions

Add AMD SSE4a and LZCNT

diff --git a/insns.dat b/insns.dat
index 428b252..9002d43 100644 (file)
--- a/insns.dat
+++ b/insns.dat
@@ -1958,6 +1958,19 @@ PSIGNW           xmmreg,xmmrm            \366\3\x0F\x38\x09\110          SSSE3
 PSIGND         mmxreg,mmxrm            \364\3\x0F\x38\x0A\110          SSSE3,MMX,SQ
 PSIGND         xmmreg,xmmrm            \366\3\x0F\x38\x0A\110          SSSE3
 
+; AMD SSE4A
+EXTRQ          xmmreg,imm,imm          \366\2\x0F\x78\200\25\26        SSE4A,AMD
+EXTRQ          xmmreg,xmmreg           \366\2\x0F\x79\110              SSE4A,AMD
+INSERTQ                xmmreg,xmmreg,imm,imm   \332\2\x0F\x78\110\26\27        SSE4A,AMD
+INSERTQ                xmmreg,xmmreg           \332\2\x0F\x79\110              SSE4A,AMD
+MOVNTSD                mem,xmmreg              \332\2\x0F\x2B\101              SSE4A,AMD,SQ
+MOVNTSS                mem,xmmreg              \333\2\x0F\x2B\101              SSE4A,AMD,SD
+
+; New instructions in Barcelona
+LZCNT          reg16,rm16              \320\333\2\x0F\xBD\110          P6,AMD
+LZCNT          reg32,rm32              \321\333\2\x0F\xBD\110          P6,AMD
+LZCNT          reg64,rm64              \324\333\2\x0F\xBD\110          P6,AMD
+
 ; Penryn New Instructions (SSE4.1)
 BLENDPD                xmmreg,xmmrm,imm        \366\3\x0F\x3A\x0D\110\26       SSE41
 BLENDPS                xmmreg,xmmrm,imm        \366\3\x0F\x3A\x0C\110\26       SSE41

diff --git a/insns.h b/insns.h
index 314737a..33cf9f4 100644 (file)
--- a/insns.h
+++ b/insns.h
@@ -98,8 +98,9 @@ extern const struct disasm_index itable[256];
 #define IF_VMX   0x00080000UL  /* it's a VMX instruction */
 #define IF_LONG   0x00100000UL /* long mode instruction */
 #define IF_SSSE3  0x00200000UL  /* it's an SSSE3 instruction */
-#define IF_SSE41  0x00400000UL  /* it's an SSE4.1 instruction */
-#define IF_SSE42  0x00800000UL  /* it's an SSE4.2 instruction */
+#define IF_SSE4A  0x00400000UL  /* AMD SSE4a */
+#define IF_SSE41  0x00800000UL  /* it's an SSE4.1 instruction */
+#define IF_SSE42  0x00800000UL  /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_SSE5   0x00800000UL  /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_PMASK  0xFF000000UL  /* the mask for processor types */
 #define IF_PLEVEL 0x0F000000UL  /* the mask for processor instr. level */