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powerpc/mpc8xxx: disable rcw_en bit for non-DDR3
author
York Sun
<yorksun@freescale.com>
Thu, 17 Mar 2011 18:18:12 +0000
(11:18 -0700)
committer
Kumar Gala
<galak@kernel.crashing.org>
Thu, 24 Mar 2011 14:20:50 +0000
(09:20 -0500)
rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
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diff --git
a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index
8ef6ca8
..
cefabe7
100644
(file)
--- a/
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@
-682,7
+682,9
@@
static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((obc_cfg & 0x1) << 6)
| ((ap_en & 0x1) << 5)
| ((d_init & 0x1) << 4)
+#ifdef CONFIG_FSL_DDR3
| ((rcw_en & 0x1) << 2)
+#endif
| ((md_en & 0x1) << 0)
);
debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);