rtlwifi: set proper udelay within rf_serial_read
authorPing-Ke Shih <pkshih@realtek.com>
Mon, 18 Nov 2019 03:14:55 +0000 (11:14 +0800)
committerKalle Valo <kvalo@codeaurora.org>
Wed, 20 Nov 2019 07:41:30 +0000 (09:41 +0200)
Since read RF register is an indirect access that hardware needs time to
accomplish read action, but there's no ready bit, so delay is required to
guarantee the read value is correct. After investigating internal documents,
these delays are reduced as proper values.

Reported-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c
drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c

index 01206651c7df9075710e172735b1c7da11b3d6ce..5ca900f97d66465c4afbd9af7f80ef281c398004 100644 (file)
@@ -164,9 +164,9 @@ static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
            (newoffset << 23) | BLSSIREADEDGE;
        rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
                      tmplong & (~BLSSIREADEDGE));
-       mdelay(1);
+       udelay(10);
        rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
-       mdelay(2);
+       udelay(120);
        if (rfpath == RF90_PATH_A)
                rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
                                                BIT(8));
index 75265b4fdf7efb15a73c58e4438b477e977e5663..6dba576aa81ef2dc5220bf93666e9e6e20e29a27 100644 (file)
@@ -158,9 +158,8 @@ static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
                   (newoffset << 23) | BLSSIREADEDGE;
        rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
                      tmplong & (~BLSSIREADEDGE));
-       mdelay(1);
        rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
-       mdelay(2);
+       udelay(20);
        if (rfpath == RF90_PATH_A)
                rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
                                                BIT(8));
index aae14c68bf69efb4aacb83f70f65f93bc65ef5ff..debecc623a01177c9ccecacab6e19b8a1f7dddb8 100644 (file)
@@ -89,12 +89,10 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
            (newoffset << 23) | BLSSIREADEDGE;
        rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
                      tmplong & (~BLSSIREADEDGE));
-       mdelay(1);
        rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
-       mdelay(1);
        rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
                      tmplong | BLSSIREADEDGE);
-       mdelay(1);
+       udelay(120);
        if (rfpath == RF90_PATH_A)
                rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
                                                 BIT(8));