Merge branch 'CR_1843_515_I2S_vol_Xingyu.Wu' into 'jh7110-5.15.y-devel'

CR_1843 515 i2 s vol xingyu.wu

See merge request sdk/linux!400

diff --combined arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0fe7c82,9efe2c8..fc25056
--- 1/arch/riscv/boot/dts/starfive/jh7110.dtsi
--- 2/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@@ -17,55 -17,6 +17,55 @@@
        #address-cells = <2>;
        #size-cells = <2>;
  
 +      cluster0_opp: opp-table-0 {
 +                      compatible = "operating-points-v2";
 +                      opp-shared;
 +                      opp-375000000 {
 +                                      opp-hz = /bits/ 64 <375000000>;
 +                                      opp-microvolt = <880000>;
 +                      };
 +                      opp-500000000 {
 +                                      opp-hz = /bits/ 64 <500000000>;
 +                                      opp-microvolt = <880000>;
 +                      };
 +                      opp-625000000 {
 +                                      opp-hz = /bits/ 64 <625000000>;
 +                                      opp-microvolt = <880000>;
 +                      };
 +                      opp-750000000 {
 +                                      opp-hz = /bits/ 64 <750000000>;
 +                                      opp-microvolt = <880000>;
 +                      };
 +                      opp-875000000 {
 +                                      opp-hz = /bits/ 64 <875000000>;
 +                                      opp-microvolt = <880000>;
 +                      };
 +                      opp-1000000000 {
 +                                      opp-hz = /bits/ 64 <1000000000>;
 +                                      opp-microvolt = <900000>;
 +                      };
 +                      opp-1250000000 {
 +                                      opp-hz = /bits/ 64 <1250000000>;
 +                                      opp-microvolt = <950000>;
 +                      };
 +                      opp-1375000000 {
 +                                      opp-hz = /bits/ 64 <1375000000>;
 +                                      opp-microvolt = <1000000>;
 +                      };
 +                      opp-1500000000 {
 +                                      opp-hz = /bits/ 64 <1500000000>;
 +                                      opp-microvolt = <1100000>;
 +                      };
 +                      opp-1625000000 {
 +                                      opp-hz = /bits/ 64 <1625000000>;
 +                                      opp-microvolt = <1100000>;
 +                      };
 +                      opp-1750000000 {
 +                                      opp-hz = /bits/ 64 <1750000000>;
 +                                      opp-microvolt = <1200000>;
 +                      };
 +      };
 +
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@@ -120,7 -71,6 +120,7 @@@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
 +                      operating-points-v2 = <&cluster0_opp>;
  
                        cpu1intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@@ -150,7 -100,6 +150,7 @@@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
 +                      operating-points-v2 = <&cluster0_opp>;
  
                        cpu2intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@@ -180,7 -129,6 +180,7 @@@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
 +                      operating-points-v2 = <&cluster0_opp>;
  
                        cpu3intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@@ -210,7 -158,6 +210,7 @@@
                        riscv,isa = "rv64imafdc";
                        tlb-split;
                        status = "okay";
 +                      operating-points-v2 = <&cluster0_opp>;
  
                        cpu4intctrl: interrupt-controller {
                                #interrupt-cells = <1>;
@@@ -332,7 -279,7 +332,7 @@@
                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
                                 <&tdm_ext>, <&mclk_ext>,
                                 <&jtag_tck_inner>, <&bist_apb>,
-                                <&stg_apb>, <&clk_rtc>,
+                                <&clk_rtc>,
                                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
                        clock-names = "osc", "gmac1_rmii_refin",
                                "gmac1_rgmii_rxin",
@@@ -340,7 -287,7 +340,7 @@@
                                "i2srx_bclk_ext", "i2srx_lrck_ext",
                                "tdm_ext", "mclk_ext",
                                "jtag_tck_inner", "bist_apb",
-                               "stg_apb", "clk_rtc",
+                               "clk_rtc",
                                "gmac0_rmii_refin", "gmac0_rgmii_rxin";
                        #clock-cells = <1>;
                        starfive,sys-syscon = <&sys_syscon 0x18 0x1c
@@@ -1800,13 -1747,5 +1800,13 @@@
                        dsp@0 {
                        };
                };
 +
 +              stf_cpufreq: starfive,stf-cpufreq {
 +                      compatible = "starfive,stf-cpufreq";
 +                      clocks = <&clkgen JH7110_PLL0_OUT>,
 +                                       <&clkgen JH7110_CPU_ROOT>,
 +                                       <&osc>;
 +                      clock-names = "pll0", "cpu_clk", "osc";
 +              };
        };
  };