2015-08-19 Jiong Wang <jiong.wang@arm.com>
+ * reloc.c (BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC.
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC): New entries.
+ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise.
+ * bfd-in2.h: Regenerate.
+ * libbfd.h: Regenerate.
+
+2015-08-19 Jiong Wang <jiong.wang@arm.com>
+
PR ld/18276
* elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize new relocation
types, including BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
/* GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction. */
BFD_RELOC_AARCH64_TLSLD_ADR_PREL21,
+/* bit[11:1] of byte offset to module TLS base address, encoded in ldst
+instructions. */
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
+
+/* Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. */
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
+
+/* bit[11:2] of byte offset to module TLS base address, encoded in ldst
+instructions. */
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
+
+/* Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. */
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
+
+/* bit[11:3] of byte offset to module TLS base address, encoded in ldst
+instructions. */
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
+
+/* Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. */
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
+
+/* bit[11:0] of byte offset to module TLS base address, encoded in ldst
+instructions. */
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
+
+/* Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. */
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC,
+
/* bit[15:0] of byte offset to module TLS base address. */
BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST_LO12,
+/* AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
+used internally by the AArch64 assembler and not (currently) written to
+any object files. */
+ BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
+
+/* Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. */
+ BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
+
/* AArch64 pseudo relocation code to be used internally by the AArch64
assembler and not (currently) written to any object files. */
BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
0x1fffff, /* dst_mask */
TRUE), /* pcrel_offset */
+ /* LD/ST16: bit[11:1] of byte offset to module TLS base address. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST16_DTPREL_LO12), /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 11, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST16_DTPREL_LO12), /* name */
+ FALSE, /* partial_inplace */
+ 0x1ffc00, /* src_mask */
+ 0x1ffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Same as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST16_DTPREL_LO12_NC), /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 11, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST16_DTPREL_LO12_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0x1ffc00, /* src_mask */
+ 0x1ffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* LD/ST32: bit[11:2] of byte offset to module TLS base address. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST32_DTPREL_LO12), /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST32_DTPREL_LO12), /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffc00, /* src_mask */
+ 0x3ffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Same as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST32_DTPREL_LO12_NC), /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 10, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST32_DTPREL_LO12_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0xffc00, /* src_mask */
+ 0xffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* LD/ST64: bit[11:3] of byte offset to module TLS base address. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST64_DTPREL_LO12), /* type */
+ 3, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 9, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST64_DTPREL_LO12), /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffc00, /* src_mask */
+ 0x3ffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Same as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST64_DTPREL_LO12_NC), /* type */
+ 3, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 9, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST64_DTPREL_LO12_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0x7fc00, /* src_mask */
+ 0x7fc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* LD/ST8: bit[11:0] of byte offset to module TLS base address. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST8_DTPREL_LO12), /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST8_DTPREL_LO12), /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffc00, /* src_mask */
+ 0x3ffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Same as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. */
+ HOWTO64 (AARCH64_R (TLSLD_LDST8_DTPREL_LO12_NC), /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 10, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (TLSLD_LDST8_DTPREL_LO12_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffc00, /* src_mask */
+ 0x3ffc00, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
/* MOVZ: bit[15:0] of byte offset to module TLS base address. */
HOWTO (AARCH64_R (TLSLD_MOVW_DTPREL_G0), /* type */
0, /* rightshift */
"BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC",
"BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21",
"BFD_RELOC_AARCH64_TLSLD_ADR_PREL21",
+ "BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12",
+ "BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12",
+ "BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12",
+ "BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC",
+ "BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12",
+ "BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC",
"BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0",
"BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC",
"BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1",
"BFD_RELOC_AARCH64_RELOC_END",
"BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP",
"BFD_RELOC_AARCH64_LDST_LO12",
+ "BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12",
+ "BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC",
"BFD_RELOC_AARCH64_LD_GOT_LO12_NC",
"BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC",
"BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC",
ENUMDOC
GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
+ENUMDOC
+ bit[11:1] of byte offset to module TLS base address, encoded in ldst
+ instructions.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
+ENUMDOC
+ Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
+ENUMDOC
+ bit[11:2] of byte offset to module TLS base address, encoded in ldst
+ instructions.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
+ENUMDOC
+ Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
+ENUMDOC
+ bit[11:3] of byte offset to module TLS base address, encoded in ldst
+ instructions.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
+ENUMDOC
+ Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
+ENUMDOC
+ bit[11:0] of byte offset to module TLS base address, encoded in ldst
+ instructions.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
+ENUMDOC
+ Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
+ENUM
BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
ENUMDOC
bit[15:0] of byte offset to module TLS base address.
AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
+ENUMDOC
+ AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
+ used internally by the AArch64 assembler and not (currently) written to
+ any object files.
+ENUM
+ BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
+ENUMDOC
+ Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
+ENUM
BFD_RELOC_AARCH64_LD_GOT_LO12_NC
ENUMDOC
AArch64 pseudo relocation code to be used internally by the AArch64
ENUMDOC
AArch64 pseudo relocation code to be used internally by the AArch64
assembler and not (currently) written to any object files.
-
ENUM
BFD_RELOC_TILEPRO_COPY
ENUMX
2015-08-19 Jiong Wang <jiong.wang@arm.com>
+ * config/tc-aarch64.c (reloc_table): New relocation types support for
+ dtprel_lo12.
+ (ldst_lo12_determine_real_reloc_type): Support
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC.
+ (parse_operands): Likewise.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+ (process_movw_reloc_info): Likewise.
+
+2015-08-19 Jiong Wang <jiong.wang@arm.com>
+
* config/tc-aarch64.c (reloc_table): New relocation modifiers,
"dtprel_hi12", "dtprel_g0", "dtprel_g0_nc", "dtprel_g1",
"dtprel_g1_nc", "dtprel_g2".
0,
0,
BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12,
- 0,
+ BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
0},
/* Same as dtprel_lo12, no overflow check. */
0,
0,
BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC,
- 0,
+ BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
0},
/* bits[23:12] of offset to the module TLS base address. */
static inline bfd_reloc_code_real_type
ldst_lo12_determine_real_reloc_type (void)
{
- int logsz;
+ unsigned logsz;
enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
- const bfd_reloc_code_real_type reloc_ldst_lo12[5] = {
- BFD_RELOC_AARCH64_LDST8_LO12, BFD_RELOC_AARCH64_LDST16_LO12,
- BFD_RELOC_AARCH64_LDST32_LO12, BFD_RELOC_AARCH64_LDST64_LO12,
+ const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = {
+ {
+ BFD_RELOC_AARCH64_LDST8_LO12,
+ BFD_RELOC_AARCH64_LDST16_LO12,
+ BFD_RELOC_AARCH64_LDST32_LO12,
+ BFD_RELOC_AARCH64_LDST64_LO12,
BFD_RELOC_AARCH64_LDST128_LO12
+ },
+ {
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
+ BFD_RELOC_AARCH64_NONE
+ },
+ {
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_NONE
+ }
};
- gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12);
+ gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
+ || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
+ || (inst.reloc.type
+ == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC));
gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
if (opd1_qlf == AARCH64_OPND_QLF_NIL)
gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
- gas_assert (logsz >= 0 && logsz <= 4);
+ if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
+ || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
+ gas_assert (logsz <= 3);
+ else
+ gas_assert (logsz <= 4);
- return reloc_ldst_lo12[logsz];
+ /* In reloc.c, these pseudo relocation types should be defined in similar
+ order as above reloc_ldst_lo12 array. Because the array index calcuation
+ below relies on this. */
+ return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
}
/* Check whether a register list REGINFO is valid. The registers must be
}
if (inst.reloc.type == BFD_RELOC_UNUSED)
aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
- else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12)
+ else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
+ || (inst.reloc.type
+ == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
+ || (inst.reloc.type
+ == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC))
inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
/* Leave qualifier to be determined by libopcodes. */
break;
case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
+ case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
+ case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
+ case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
2015-08-19 Jiong Wang <jiong.wang@arm.com>
+ * gas/aarch64/reloc-dtprel-lo12-ldst8.s: New testcase.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst8.s: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12-ldst16.s: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst16.s: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12-ldst32.s: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst32.s: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12-ldst64.s: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst64.s: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12-ldst8.d: New expectation file.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst8.d: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12-ldst16.d: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst16.d: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12-ldst32.d: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst32.d: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12-ldst64.d: Likewise.
+ * gas/aarch64/reloc-dtprel-lo12_nc-ldst64.d: Likewise.
+
+2015-08-19 Jiong Wang <jiong.wang@arm.com>
+
* gas/aarch64/reloc-dtprel_g0.s: New testcase.
* gas/aarch64/reloc-dtprel_g0-ilp32.s: Likewise.
* gas/aarch64/reloc-dtprel_g0_nc.s: Likewise.
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 7980009b ldrsh x27, \[x4\]
+ 0: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12 for LDST16
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
+ ldrsh x27, [x4, #:dtprel_lo12:sym]
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: b980009b ldrsw x27, \[x4\]
+ 0: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12 for LDST32
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
+ ldrsw x27, [x4, #:dtprel_lo12:sym]
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: f940009b ldr x27, \[x4\]
+ 0: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12 for LDST64
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
+ ldr x27, [x4, #:dtprel_lo12:sym]
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 39800115 ldrsb x21, \[x8\]
+ 0: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12 for LDST8
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
+ ldrsb x21, [x8, #:dtprel_lo12:sym]
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 7940009b ldrh w27, \[x4\]
+ 0: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12_nc for LDST16
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
+ ldrh w27, [x4, #:dtprel_lo12_nc:sym]
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: b98000f4 ldrsw x20, \[x7\]
+ 0: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12_nc for LDST32
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
+ ldrsw x20, [x7, #:dtprel_lo12_nc:sym]
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: f940009b ldr x27, \[x4\]
+ 0: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12_nc for LDST64
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
+ ldr x27, [x4, #:dtprel_lo12_nc:sym]
+
--- /dev/null
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 3940005d ldrb w29, \[x2\]
+ 0: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
+
--- /dev/null
+// Test file for AArch64 GAS -- dtprel_lo12_nc for LDST8
+
+func:
+ // BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
+ ldrb w29, [x2, #:dtprel_lo12_nc:sym]
+