drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controller

Currently the controller by default enables the Receive Detect feature in P3
mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
detection in P3 mode.
Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
Detect feature is required.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 183bf2b..f2bffba 100644 (file)
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -190,4 +190,30 @@ bool has_erratum_a008751(void)
        return false;
 }
 
+bool has_erratum_a010151(void)
+{
+       u32 svr = get_svr();
+       u32 soc = SVR_SOC_VER(svr);
+
+       switch (soc) {
+#ifdef CONFIG_ARM64
+       case SVR_LS2080A:
+       case SVR_LS2085A:
+       case SVR_LS1046A:
+       case SVR_LS1012A:
+               return IS_SVR_REV(svr, 1, 0);
+       case SVR_LS1043A:
+               return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+#ifdef CONFIG_LS102XA
+       case SOC_VER_LS1020:
+       case SOC_VER_LS1021:
+       case SOC_VER_LS1022:
+       case SOC_VER_SLS1020:
+               return IS_SVR_REV(svr, 2, 0);
+#endif
+       }
+       return false;
+}
+
 #endif

diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 2529d0e..798c358 100644 (file)
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -84,6 +84,19 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
        /* Change beat burst and outstanding pipelined transfers requests */
        fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
 
+       /*
+        * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
+        * reliably support Rx Detect in P3 mode(P3 is the default
+        * setting). Therefore, some USB3.0 devices may not be detected
+        * reliably in Super Speed mode. So, USB controller to configure
+        * USB in P2 mode whenever the Receive Detect feature is required.
+        * whenever the Receive Detect feature is required.
+        */
+       if (has_erratum_a010151())
+               clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
+                               DWC3_GUSB3PIPECTL_DISRXDETP3,
+                               DWC3_GUSB3PIPECTL_DISRXDETP3);
+
        return ret;
 }
 

diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index fc72fb9..73235b8 100644 (file)
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -95,5 +95,6 @@ bool has_erratum_a007792(void);
 bool has_erratum_a005697(void);
 bool has_erratum_a004477(void);
 bool has_erratum_a008751(void);
+bool has_erratum_a010151(void);
 #endif
 #endif /*_ASM_FSL_USB_H_ */

diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index a027446..c1b23b2 100644 (file)
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -198,6 +198,7 @@ struct dwc3 {                                       /* offset: 0xC100 */
 
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST           (1 << 31)
+#define DWC3_GUSB3PIPECTL_DISRXDETP3           (1 << 28)
 #define DWC3_GUSB3PIPECTL_SUSPHY               (1 << 17)
 
 /* Global TX Fifo Size Register */