Merge with git+ssh://fifi/home/wd/git/u-boot/master

diff --git a/CHANGELOG b/CHANGELOG
index 961e073..ff6eadb 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,21 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Update for SC520 board.
+  Patch by David Updegraff, 02 Dec 2005
+
+* Fixed common.h spelling error.
+  Patch by Cory Tusar, 30 Nov 2005
+
+* Fix typo.
+  Patch by Andreas Engel, 28 Nov 2005
+
+* Fix fatload command on FAT32 formatted partitions.
+  Patch by Joachim Jaeger, 18 Nov 2005
+
+* Fix drivers/dm9000.c when configured in 32 bit mode.
+  Patch by Eric Benard, 17 Nov 2005
+
 * Cleanup debug code for yucca board.
 
 * MCC200: restrict addressable flash space to 32 MB

diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index c83f0bb..1c4370b 100644 (file)
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -31,7 +31,9 @@
 #include <common.h>
 #include <config.h>
 #include <pci.h>
+#ifdef CONFIG_SC520_SSI
 #include <ssi.h>
+#endif
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
@@ -143,7 +145,15 @@ unsigned long init_sc520_dram(void)
 
        u32 dram_present=0;
        u32 dram_ctrl;
-
+#ifdef CFG_SDRAM_DRCTMCTL
+       /* these memory control registers are set up in the assember part,
+        * in sc520_asm.S, during 'mem_init'.  If we muck with them here,
+        * after we are running a stack in RAM, we have troubles.  Besides,
+        * these refresh and delay values are better ? simply specified 
+        * outright in the include/configs/{cfg} file since the HW designer
+        * simply dictates it.
+        */
+#else
        int val;
 
        int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
@@ -162,6 +172,7 @@ unsigned long init_sc520_dram(void)
        } else {
                val = 3;  /* 62.4us */
        }
+
        write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
 
        val = read_mmcr_byte(SC520_DRCTMCTL);
@@ -181,13 +192,12 @@ unsigned long init_sc520_dram(void)
                val |= 1;
        }
        write_mmcr_byte(SC520_DRCTMCTL, val);
-
+#endif
 
        /* We read-back the configuration of the dram
         * controller that the assembly code wrote */
        dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
 
-
        bd->bi_dram[0].start = 0;
        if (dram_ctrl & 0x80) {
                /* bank 0 enabled */
@@ -274,7 +284,7 @@ int pci_sc520_set_irq(int pci_pin, int irq)
 {
        int i;
 
-# if 0
+# if 1
        printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
 #endif
        if (irq < 0 || irq > 15) {

diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index 80464fa..e1fa37a 100644 (file)
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -113,6 +113,7 @@
 .equ            DRCCFG,     0x0fffef014   /* DRAM bank configuration register */
 .equ            DRCBENDADR, 0x0fffef018   /* DRAM bank ending address register */
 .equ            ECCCTL,     0x0fffef020   /* DRAM ECC control register */
+.equ            ECCINT,     0x0fffefd18   /* DRAM ECC nmi-INT mapping */
 .equ            DBCTL,      0x0fffef040   /* DRAM buffer control register */
 
 .equ            CACHELINESZ, 0x00000010   /* size of our cache line (read buffer) */
@@ -459,6 +460,12 @@ emptybank:
        incl    %edi
        loop    cleanuplp
 
+#if defined CFG_SDRAM_DRCTMCTL
+       /* just have your hardware desinger _GIVE_ you what you need here! */
+       movl    $DRCTMCTL, %edi   
+       movb    $CFG_SDRAM_DRCTMCTL,%al
+       movb    (%edi), %al
+#else
 #if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
        /* set the CAS latency now since it is hard to do
         * when we run from the RAM */
@@ -470,7 +477,8 @@ emptybank:
 #ifdef CFG_SDRAM_CAS_LATENCY_3T
        orb     $0x10, %al
 #endif
-       movb    %al, (%edi)
+       movb    %al, (%edi) 
+#endif
 #endif
        movl    $DRCCTL, %edi            /* DRAM Control register */
        movb    $0x3,%al                 /* Load mode register cmd */
@@ -528,9 +536,49 @@ bank0:     movl    (%edi), %eax
        shll    $22, %eax
        movl    %eax, %ebx
 
-done:  movl    %ebx, %eax
 
+done:  
+       movl    %ebx, %eax
+
+#if CFG_SDRAM_ECC_ENABLE
+       /* A nominal memory test: just a byte at each address line */
+       movl    %eax, %ecx
+       shrl    $0x1, %ecx
+       movl    $0x1, %edi
+memtest0:
+       movb    $0xa5, (%edi)
+       cmpb    $0xa5, (%edi) 
+       jne     out
+       shrl    $1, %ecx
+       andl    %ecx,%ecx
+       jz      set_ecc
+       shll    $1, %edi
+       jmp     memtest0
+
+set_ecc:
+       /* clear all ram with a memset */
+       movl    %eax, %ecx
+       xorl    %esi, %esi
+       xorl    %edi, %edi
+       xorl    %eax, %eax
+       shrl    $2, %ecx
+       cld
+       rep     stosl
+                       /* enable read, write buffers */
+       movb    $0x11, %al
+       movl    $DBCTL, %edi
+       movb    %al, (%edi)
+                       /* enable NMI mapping for ECC */
+       movl    $ECCINT, %edi
+       mov     $0x10, %al
+       movb    %al, (%edi) 
+                       /* Turn on ECC */
+       movl    $ECCCTL, %edi
+       mov     $0x05, %al
+       movb    %al, (%edi) 
+#endif
+out:
+       movl    %ebx, %eax
        jmp     *%ebp
 
-
 #endif /* CONFIG_SC520 */

diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c
index 0e475d4..6877076 100644 (file)
--- a/drivers/dm9000x.c
+++ b/drivers/dm9000x.c
@@ -436,6 +436,9 @@ eth_rx(void)
        u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
        u16 RxStatus, RxLen = 0;
        u32 tmplen, i;
+#ifdef CONFIG_DM9000_USE_32BIT
+       u32 tmpdata;
+#endif
 
        /* Check packet ready or not */
        DM9000_ior(DM9000_MRCMDX);      /* Dummy read */

diff --git a/include/common.h b/include/common.h
index bd41ae1..9a19001 100644 (file)
--- a/include/common.h
+++ b/include/common.h
@@ -603,7 +603,7 @@ void        show_boot_progress (int status);
 #endif
 
 #ifdef CONFIG_INIT_CRITICAL
-#error CONFIG_INIT_CRITICAL is depracted!
+#error CONFIG_INIT_CRITICAL is deprecated!
 #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
 #endif
 

diff --git a/include/fat.h b/include/fat.h
index 0645458..92638d5 100644 (file)
--- a/include/fat.h
+++ b/include/fat.h
@@ -175,15 +175,19 @@ typedef struct dir_slot {
        __u8    name11_12[4];   /* Last 2 characters in name */
 } dir_slot;
 
-/* Private filesystem parameters */
+/* Private filesystem parameters
+ *
+ * Note: FAT buffer has to be 32 bit aligned
+ * (see FAT32 accesses)
+ */
 typedef struct {
+       __u8    fatbuf[FATBUFSIZE]; /* Current FAT buffer */
        int     fatsize;        /* Size of FAT in bits */
        __u16   fatlength;      /* Length of FAT in sectors */
        __u16   fat_sect;       /* Starting sector of the FAT */
        __u16   rootdir_sect;   /* Start sector of root directory */
        __u16   clust_size;     /* Size of clusters in sectors */
        short   data_begin;     /* The sector of the first cluster, can be negative */
-       __u8    fatbuf[FATBUFSIZE]; /* Current FAT buffer */
        int     fatbufnum;      /* Used by get_fatent, init to -1 */
 } fsdata;
 

diff --git a/net/tftp.c b/net/tftp.c
index eca21d2..f3a5471 100644 (file)
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -225,7 +225,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
                if (TftpBlock == 0) {
                        TftpBlockWrap++;
                        TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE;
-                       printf ("\n\t %lu MB reveived\n\t ", TftpBlockWrapOffset>>20);
+                       printf ("\n\t %lu MB received\n\t ", TftpBlockWrapOffset>>20);
                } else {
                        if (((TftpBlock - 1) % 10) == 0) {
                                putc ('#');