Divide the old device tree into several files according to different layers.
Make the device tree clearer and more readable.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE_JH7110) += starfive_jh7110.dtb
+dtb-$(CONFIG_SOC_STARFIVE_JH7110) += jh7110-visionfive-v2.dtb jh7110-evb.dtb jh7110-fpga.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include "jh7110_pinctrl.dtsi"
+
+/ {
+ aliases {
+ spi0="/soc/spi@13010000";
+ gpio0="/soc/gpio@13040000";
+ ethernet0="/soc/gmac0@16030000";
+ mmc0="/soc/sdio0@16010000";
+ mmc1="/soc/sdio1@16020000";
+ };
+
+ chosen {
+ linux,initrd-start = <0x0 0x46100000>;
+ linux,initrd-end = <0x0 0x4c000000>;
+ stdout-path = "/soc/serial@10000000:115200";
+ #bootargs = "debug console=ttyS0 rootwait";
+ };
+
+ cpus {
+ timebase-frequency = <2000000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x20000000>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&dma {
+ status = "okay";
+};
+
+&trng {
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <3000>;
+ i2c-scl-falling-time-ns = <3000>;
+ auto_calc_scl_lhcnt;
+ status = "okay";
+
+ sc2235@30 {
+ compatible = "sc2235";
+ reg = <0x30>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ powerdown-gpios = <&gpio 0 0>;
+ reset-gpios = <&gpio 0 0>;
+ sc2235-18-gpios = <&gpio 11 0>;
+ sc2235-15-gpios = <&gpio 12 0>;
+ sc2235-28-gpios = <&gpio 10 0>;
+ sc2235-reset-gpios = <&gpio 16 0>;
+ sc2235-pwdn-gpios = <&gpio 15 0>;
+ sc2235-esync-gpios = <&gpio 17 0>;
+ sc2235-oen-gpios = <&gpio 18 0>;
+
+ port {
+ /* Parallel bus endpoint */
+ sc2235_to_parallel: endpoint {
+ remote-endpoint = <¶llel_from_sc2235>;
+ bus-type = <5>; /* Parallel */
+ bus-width = <8>;
+ data-shift = <2>; /* lines 13:6 are used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <1>;
+ };
+ };
+ };
+
+ ov13850@10 {
+ compatible = "ovti,ov13850";
+ reg = <0x10>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ powerdown-gpio = <&gpio 15 0>;
+ reset-gpio = <&gpio 16 0>;
+ rotation = <0>;
+
+ port {
+ /* CSI2 bus endpoint */
+ ov13850_to_csi2rx0: endpoint {
+ remote-endpoint = <&csi2rx0_from_ov13850>;
+ bus-type = <4>; /* MIPI CSI-2 D-PHY */
+ clock-lanes = <2>;
+ data-lanes = <0 1>;
+ };
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <3000>;
+ i2c-scl-falling-time-ns = <3000>;
+ auto_calc_scl_lhcnt;
+ status = "okay";
+
+ ac108_a: ac108@3b {
+ compatible = "x-power,ac108_0";
+ reg = <0x3b>;
+ #sound-dai-cells = <0>;
+ data-protocol = <0>;
+ };
+
+ wm8960: codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+
+ wlf,shared-lrclk;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <3000>;
+ i2c-scl-falling-time-ns = <3000>;
+ auto_calc_scl_lhcnt;
+ status = "okay";
+
+ adv7513@39 {
+ compatible = "adi,adv7513";
+ reg = <0x39>, <0x49>, <0x29>, <0x59>;
+ reg-names = "main", "edid", "cec", "packet";
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7513_0_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7513_1_out: endpoint {
+ };
+ };
+ };
+ };
+};
+
+&sdio0 {
+ clock-frequency = <4000000>;
+ max-frequency = <1000000>;
+ card-detect-delay = <300>;
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ cap-mmc-hw-reset;
+ non-removable;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ cap-mmc-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&sdio1 {
+ clock-frequency = <4000000>;
+ max-frequency = <1000000>;
+ card-detect-delay = <300>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ cap-mmc-hw-reset;
+ non-removable;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ cap-mmc-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&vin_sysctl {
+ status = "okay";
+
+ ports {
+ port@3 {
+ reg = <2>;
+
+ /* Parallel bus endpoint */
+ parallel_from_sc2235: endpoint {
+ remote-endpoint = <&sc2235_to_parallel>;
+ bus-type = <5>; /* Parallel */
+ bus-width = <8>;
+ data-shift = <2>; /* lines 9:2 are used */
+ hsync-active = <1>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ status = "okay";
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+
+ /* Parallel bus endpoint */
+ csi2rx0_from_ov13850: endpoint {
+ remote-endpoint = <&ov13850_to_csi2rx0>;
+ bus-type = <4>; /* MIPI CSI-2 D-PHY */
+ clock-lanes = <2>;
+ data-lanes = <0 1>;
+ status = "okay";
+ };
+ };
+ };
+};
+
+&jpu {
+ status = "okay";
+};
+
+&vpu_dec {
+ status = "okay";
+};
+
+&vpu_enc {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&ipmscan0 {
+ status = "okay";
+};
+
+&ipmscan1 {
+ status = "okay";
+};
+
+&tdm {
+ status = "okay";
+};
+
+&spdif0 {
+ status = "okay";
+};
+
+&pwmdac {
+ status = "okay";
+};
+
+&i2stx {
+ status = "okay";
+};
+
+&pdm {
+ status = "okay";
+};
+
+&i2srx_3ch {
+ status = "okay";
+};
+
+&i2stx_4ch0 {
+ status = "okay";
+};
+
+&i2stx_4ch1 {
+ status = "okay";
+};
+
+&ptc {
+ status = "okay";
+};
+
+&spdif_transmitter {
+ status = "okay";
+};
+
+&spdif_receiver {
+ status = "okay";
+};
+
+&pwmdac_codec {
+ status = "okay";
+};
+
+&dmic_codec {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ spi_dev0: spi@0 {
+ compatible = "rohm,dh2228fv";
+ pl022,com-mode = <1>;
+ spi-max-frequency = <10000000>;
+ reg = <0>;
+ status = "okay";
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&mailbox_contrl0 {
+ status = "okay";
+};
+
+&mailbox_client0 {
+ status = "okay";
+};
+
+&display {
+ status = "okay";
+};
+
+&encoder {
+ encoder-type = <2>;
+ status = "okay";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7513_0_in>;
+ };
+ };
+
+ port@1 {
+ endpoint {
+ remote-endpoint = <&dc_out_dpi0>;
+ };
+ };
+ };
+};
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+ model = "StarFive JH7110 EVB";
+ compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+ model = "StarFive JH7110 FPGA";
+ compatible = "starfive,jh7110-fpga", "starfive,jh7110";
+};
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,visionfive-v2", "starfive,jh7110";
+};
\ No newline at end of file
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
/dts-v1/;
+#include "jh7110_clk.dtsi"
#include <dt-bindings/reset/starfive-jh7110.h>
-#include "starfive_jh7110_clk.dtsi"
#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
#include <dt-bindings/clock/starfive-jh7110-vout.h>
/ {
+ compatible = "starfive,jh7110";
#address-cells = <2>;
#size-cells = <2>;
- compatible = "sifive,freedom-u74-arty";
- model = "sifive,freedom-u74-arty";
-
- chosen {
- linux,initrd-start = <0x0 0x46100000>;
- linux,initrd-end = <0x0 0x4c000000>;
- stdout-path = "/soc/serial@10000000:115200";
- #bootargs = "debug console=ttyS0 rootwait";
- };
- aliases {
- spi0="/soc/spi@13010000";
- gpio0="/soc/gpio@13040000";
- ethernet0="/soc/gmac0@16030000";
- mmc0="/soc/sdio0@16010000";
- mmc1="/soc/sdio1@16020000";
- };
- cpus: cpus {
+
+ cpus {
#address-cells = <1>;
#size-cells = <0>;
- timebase-frequency = <2000000>;
- compatible = "starfive,fu74-g000";
- cpu@0 {
- clock-frequency = <0>;
- compatible = "starfive,rocket0", "riscv";
+
+ cpu0: cpu@0 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
- d-cache-size = <32768>;
+ d-cache-size = <8192>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
- i-cache-size = <32768>;
+ i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- reg = <0>;
riscv,isa = "rv64imac";
- status = "disabled";
tlb-split;
+ status = "disabled";
+
cpu0intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
- cpu@1 {
- clock-frequency = <0>;
- compatible = "starfive,rocket0", "riscv";
+
+ cpu1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- reg = <1>;
riscv,isa = "rv64imafdc";
- status = "okay";
tlb-split;
+ status = "okay";
+
cpu1intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
- cpu@2 {
- clock-frequency = <0>;
- compatible = "starfive,rocket0", "riscv";
+
+ cpu2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- reg = <2>;
riscv,isa = "rv64imafdc";
- status = "okay";
tlb-split;
+ status = "okay";
+
cpu2intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
- cpu@3 {
- clock-frequency = <0>;
- compatible = "starfive,rocket0", "riscv";
+
+ cpu3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- reg = <3>;
riscv,isa = "rv64imafdc";
- status = "okay";
tlb-split;
+ status = "okay";
+
cpu3intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
- cpu@4 {
- clock-frequency = <0>;
- compatible = "starfive,rocket0", "riscv";
+
+ cpu4: cpu@4 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <4>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- reg = <4>;
riscv,isa = "rv64imafdc";
- status = "okay";
tlb-split;
+ status = "okay";
+
cpu4intctrl: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
};
};
};
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0x1 0x0>;
- };
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x20000000>;
- alignment = <0x0 0x1000>;
- alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
- linux,cma-default;
- };
- };
soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
- compatible = "starfive,freedom-u74-arty", "simple-bus", "arm,amba-bus";
ranges;
cachectrl: cache-controller@2010000 {
+ compatible = "sifive,fu740-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
+ reg-names = "control", "sideband";
+ interrupts = <1 3 4 2>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
- compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
- interrupt-parent = <&plic>;
- interrupts = <1 3 4 2>;
- /*next-level-cache = <&L40 &L36>;*/
- reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
- reg-names = "control", "sideband";
};
+
clint: clint@2000000 {
- #interrupt-cells = <1>;
compatible = "riscv,clint0";
- /*interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;*/
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ reg-names = "control";
interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
&cpu1intctrl 3 &cpu1intctrl 7
&cpu2intctrl 3 &cpu2intctrl 7
&cpu3intctrl 3 &cpu3intctrl 7
&cpu4intctrl 3 &cpu4intctrl 7>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- reg-names = "control";
+ #interrupt-cells = <1>;
};
+
plic: plic@c000000 {
- #interrupt-cells = <1>;
compatible = "riscv,plic0";
- interrupt-controller;
- /*interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;*/
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ reg-names = "control";
interrupts-extended = <&cpu0intctrl 11
&cpu1intctrl 11 &cpu1intctrl 9
&cpu2intctrl 11 &cpu2intctrl 9
&cpu3intctrl 11 &cpu3intctrl 9
&cpu4intctrl 11 &cpu4intctrl 9>;
- reg = <0x0 0xc000000 0x0 0x4000000>;
- reg-names = "control";
+ interrupt-controller;
+ #interrupt-cells = <1>;
riscv,max-priority = <7>;
riscv,ndev = <136>;
};
compatible = "starfive,jh7110-clkgen";
reg = <0x0 0x13020000 0x0 0x10000>,
<0x0 0x10230000 0x0 0x10000>,
- <0x0 0x17000000 0x0 0x10000>;
+ <0x0 0x17000000 0x0 0x10000>;
reg-names = "sys", "stg", "aon";
- clocks = <&osc>, <&gmac1_rmii_refin>,
- <&gmac1_rgmii_rxin>,
- <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
- <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
- <&tdm_ext>, <&mclk_ext>,
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>,
<&jtag_tck_inner>, <&bist_apb>,
<&stg_apb>, <&clk_rtc>,
<&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
- clock-names = "osc", "gmac1_rmii_refin",
- "gmac1_rgmii_rxin",
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
- "tdm_ext", "mclk_ext",
+ "tdm_ext", "mclk_ext",
"jtag_tck_inner", "bist_apb",
"stg_apb", "clk_rtc",
"gmac0_rmii_refin", "gmac0_rgmii_rxin";
compatible = "starfive,jh7110-clk-vout";
reg = <0x0 0x295C0000 0x0 0x10000>;
reg-names = "vout";
- clocks = <&hdmitx0_pixelclk>,
- <&mipitx_dphy_rxesc>,
+ clocks = <&hdmitx0_pixelclk>,
+ <&mipitx_dphy_rxesc>,
<&mipitx_dphy_txbytehs>;
- clock-names = "hdmitx0_pixelclk",
- "mipitx_dphy_rxesc",
+ clock-names = "hdmitx0_pixelclk",
+ "mipitx_dphy_rxesc",
"mipitx_dphy_txbytehs";
#clock-cells = <1>;
status = "disabled";
status = "disabled";
};
+ qspi: qspi@13010000 {
+ compatible = "cadence,qspi","cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x13010000 0x0 0x10000
+ 0x0 0x21000000 0x0 0x400000>;
+ clocks = <&clkgen JH7110_QSPI_CLK_REF>;
+ clock-names = "clk_ref";
+ resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
+ <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
+ <&rstgen RSTN_U0_CDNS_QSPI_REF>;
+ resets-names = "rst_apb", "rst_ahb", "rst_ref";
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ spi-max-frequency = <250000000>;
+
+ nor_flash: nor-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg=<0>;
+ spi-max-frequency = <100000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+ };
+ };
+
+ otp: otp@17050000 {
+ compatible = "starfive,jh7110-otp";
+ reg = <0x0 0x17050000 0x0 0x10000>;
+ clock-frequency = <4000000>;
+ clocks = <&clkgen JH7110_OTPC_CLK_APB>;
+ clock-names = "apb";
+ };
+
+ USB30: usb@10100000 {
+ compatible = "cdns,usb3";
+ reg = <0x0 0x10100000 0x0 0x10000>,
+ <0x0 0x10110000 0x0 0x10000>,
+ <0x0 0x10120000 0x0 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+ clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
+ <&clkgen JH7110_USB0_CLK_LPM>,
+ <&clkgen JH7110_USB0_CLK_STB>,
+ <&clkgen JH7110_USB0_CLK_USB_APB>,
+ <&clkgen JH7110_USB0_CLK_AXI>,
+ <&clkgen JH7110_USB0_CLK_UTMI_APB>;
+ clock-names = "app","lpm","stb","apb","axi","utmi";
+ resets = <&rstgen RSTN_U0_CDN_USB_PWEUP>,
+ <&rstgen RSTN_U0_CDN_USB_APB>,
+ <&rstgen RSTN_U0_CDN_USB_AXI>,
+ <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
+ reset-names = "rst_pweup","rst_apb","rst_axi","rst_utmi";
+ };
+
timer: timer@13050000 {
- compatible = "starfive,si5-timers";
- reg = <0x0 0x13050000 0x0 0x10000>;
- interrupt-parent = <&plic>;
- interrupts = <69>, <70>, <71> ,<72>;
- interrupt-names = "timer0", "timer1", "timer2", "timer3";
- clock-frequency = <2000000>;
- status = "disabled";
- };
-
- wdog: wdog@13070000 {
- compatible = "starfive,dskit-wdt";
- reg = <0x0 0x13070000 0x0 0x10000>;
- interrupt-parent = <&plic>;
- interrupts = <68>;
- interrupt-names = "wdog";
- clock-frequency = <2000000>;
+ compatible = "starfive,si5-timers";
+ reg = <0x0 0x13050000 0x0 0x10000>;
+ interrupts = <69>, <70>, <71> ,<72>;
+ interrupt-names = "timer0", "timer1", "timer2", "timer3";
+ clock-frequency = <2000000>;
+ status = "disabled";
+ };
+
+ wdog: wdog@13070000 {
+ compatible = "starfive,dskit-wdt";
+ reg = <0x0 0x13070000 0x0 0x10000>;
+ interrupts = <68>;
+ interrupt-names = "wdog";
+ clock-frequency = <2000000>;
timeout-sec = <15>;
- status = "okay";
- };
+ status = "okay";
+ };
rtc: rtc@17040000 {
compatible = "starfive,rtc_hms";
reg = <0x0 0x17040000 0x0 0x10000>;
- interrupt-parent = <&plic>;
interrupts = <10>, <11>, <12>;
interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
clocks = <&rtc_hmsclk>, <&oscclk>;
pmu: pmu@17030000 {
compatible = "starfive,jh7110-pmu";
reg = <0x0 0x17030000 0x0 0x10000>;
- interrupt-parent = <&plic>;
interrupts = <111>;
status = "okay";
};
uart0: serial@10000000 {
compatible = "snps,dw-apb-uart";
- interrupt-parent = <&plic>;
- interrupts = <32>;
reg = <0x0 0x10000000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&clkgen JH7110_UART0_CLK_CORE>,
<&clkgen JH7110_UART0_CLK_APB>;
clock-names = "baudclk", "apb_pclk";
- status = "okay";
+ interrupts = <32>;
+ status = "disabled";
};
+
uart1: serial@10010000 {
compatible = "snps,dw-apb-uart";
- interrupt-parent = <&plic>;
- interrupts = <33>;
reg = <0x0 0x10010000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&oscclk>, <&apb0clk>;
clock-names = "baudclk", "apb_pclk";
- status = "okay";
+ interrupts = <33>;
+ status = "disabled";
};
+
uart2: serial@10020000 {
compatible = "snps,dw-apb-uart";
- interrupt-parent = <&plic>;
- interrupts = <34>;
reg = <0x0 0x10020000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&oscclk>, <&apb0clk>;
clock-names = "baudclk", "apb_pclk";
- status = "okay";
+ interrupts = <34>;
+ status = "disabled";
};
+
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
- interrupt-parent = <&plic>;
- interrupts = <45>;
reg = <0x0 0x12000000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&uartclk>, <&apb0clk>;
clock-names = "baudclk", "apb_pclk";
- status = "okay";
+ interrupts = <45>;
+ status = "disabled";
};
+
uart4: serial@12010000 {
compatible = "snps,dw-apb-uart";
- interrupt-parent = <&plic>;
- interrupts = <46>;
reg = <0x0 0x12010000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&uartclk>, <&apb0clk>;
clock-names = "baudclk", "apb_pclk";
- status = "okay";
+ interrupts = <46>;
+ status = "disabled";
};
+
uart5: serial@12020000 {
compatible = "snps,dw-apb-uart";
- interrupt-parent = <&plic>;
- interrupts = <47>;
reg = <0x0 0x12020000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&uartclk>, <&apb0clk>;
clock-names = "baudclk", "apb_pclk";
- status = "okay";
+ interrupts = <47>;
+ status = "disabled";
};
+
dma: dma-controller@16050000 {
compatible = "starfive,axi-dma";
reg = <0x0 0x16050000 0x0 0x10000>;
clocks = <&stg_axiahb_clk>, <&stg_apbclk>;
clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <&plic>;
interrupts = <73>;
#dma-cells = <2>;
dma-channels = <4>;
snps,block-size = <65536 65536 65536 65536>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <16>;
- status = "okay";
+ status = "disabled";
};
+
gpio: gpio@13040000 {
- /*compatible = "starfive,gpio7110";*/
compatible = "starfive_jh7110-sys-pinctrl";
- interrupt-parent = <&plic>;
- interrupts = <91>;
reg = <0x0 0x13040000 0x0 0x10000>;
reg-names = "control";
+ interrupts = <91>;
interrupt-controller;
#gpio-cells = <2>;
ngpios = <64>;
gpioa: gpio@17020000 {
compatible = "starfive_jh7110-aon-pinctrl";
- interrupt-parent = <&plic>;
- interrupts = <90>;
reg = <0x0 0x17020000 0x0 0x10000>;
reg-names = "control";
+ interrupts = <90>;
interrupt-controller;
#gpio-cells = <2>;
ngpios = <4>;
status = "okay";
};
-
+
trng: trng@1600C000 {
compatible = "starfive,trng";
reg = <0x0 0x1600C000 0x0 0x4000>;
- interrupt-parent = <&plic>;
- interrupts = <30>;
clocks = <&apb12clk>;
- status = "okay";
+ interrupts = <30>;
+ status = "disabled";
};
-
i2c6: i2c@12060000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x12060000 0x0 0x10000>;
- interrupt-parent = <&plic>;
interrupts = <51>;
- clock-frequency = <100000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <3000>;
- i2c-scl-falling-time-ns = <3000>;
- auto_calc_scl_lhcnt;
-
- status = "okay";
-
- sc2235@30 {
- compatible = "sc2235";
- reg = <0x30>;
- clocks = <&clk_ext_camera>;
- clock-names = "xclk";
- powerdown-gpios = <&gpio 0 0>;
- reset-gpios = <&gpio 0 0>;
- sc2235-18-gpios = <&gpio 11 0>;
- sc2235-15-gpios = <&gpio 12 0>;
- sc2235-28-gpios = <&gpio 10 0>;
- sc2235-reset-gpios = <&gpio 16 0>;
- sc2235-pwdn-gpios = <&gpio 15 0>;
- sc2235-esync-gpios = <&gpio 17 0>;
- sc2235-oen-gpios = <&gpio 18 0>;
- //DOVDD-supply = <&v2v8>;
-
- port {
- /* Parallel bus endpoint */
- sc2235_to_parallel: endpoint {
- remote-endpoint = <¶llel_from_sc2235>;
- bus-type = <5>; /* Parallel */
- bus-width = <8>;
- data-shift = <2>; /* lines 13:6 are used */
- hsync-active = <1>;
- vsync-active = <1>;
- pclk-sample = <1>;
- };
- };
- };
-
- ov13850@10 {
- compatible = "ovti,ov13850";
- reg = <0x10>;
- clocks = <&clk_ext_camera>;
- clock-names = "xclk";
- powerdown-gpio = <&gpio 15 0>;
- reset-gpio = <&gpio 16 0>;
- //DOVDD-supply = <&v2v8>;
- rotation = <0>;
-
- port {
- /* CSI2 bus endpoint */
- ov13850_to_csi2rx0: endpoint {
- remote-endpoint = <&csi2rx0_from_ov13850>;
- bus-type = <4>; /* MIPI CSI-2 D-PHY */
- clock-lanes = <2>;
- data-lanes = <0 1>;
- };
- };
- };
- };
- i2c0: i2c@10030000 {
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@10030000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10030000 0x0 0x10000>;
- interrupt-parent = <&plic>;
interrupts = <35>;
- /*clocks = <&hfclk>; */
- clock-frequency = <100000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <3000>;
- i2c-scl-falling-time-ns = <3000>;
- auto_calc_scl_lhcnt;
- status = "okay";
-
- ac108_a: ac108@3b {
- compatible = "x-power,ac108_0";
- reg = <0x3b>;
- #sound-dai-cells = <0>;
- data-protocol = <0>;
- };
-
- wm8960: codec@1a {
- compatible = "wlf,wm8960";
- reg = <0x1a>;
- #sound-dai-cells = <0>;
-
- wlf,shared-lrclk;
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
i2c1: i2c@10040000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x10040000 0x0 0x10000>;
- interrupt-parent = <&plic>;
interrupts = <36>;
- /*clocks = <&hfclk>; */
- clock-frequency = <100000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <3000>;
- i2c-scl-falling-time-ns = <3000>;
- auto_calc_scl_lhcnt;
-
- adv7513@39 {
- compatible = "adi,adv7513";
- reg = <0x39>, <0x49>, <0x29>, <0x59>;
- reg-names = "main", "edid", "cec", "packet";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7513_0_in: endpoint {
- };
- };
-
- port@1 {
- reg = <1>;
- adv7513_1_out: endpoint {
- };
- };
- };
- };
- /*
- seeed_plane_i2c@45 { //next to do handle this node to i2cX
- compatible = "seeed_panel";
- reg = <0x45>;
-
- port {
- panel_dsi_port: endpoint {
- remote-endpoint = <&dsi_out_port>;
- };
- };
- };*/
- };
- /*emmc*/
- sdio0:sdio0@16010000{
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sdio0: sdio0@16010000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x16010000 0x0 0x10000>;
- interrupts = <74>;
- interrupt-parent = <&plic>;
clocks = <&dwmmc_biuclk>,<&dwmmc_ciuclk>;
clock-names = "biu","ciu";
- clock-frequency = <4000000>;
- max-frequency = <1000000>;
+ interrupts = <74>;
fifo-depth = <32>;
- card-detect-delay = <300>;
fifo-watermark-aligned;
data-addr = <0>;
- bus-width = <8>;
- cap-sd-highspeed;
- /*broken-cd;*/
- cap-sdio-irq;
- cap-mmc-hw-reset;
- non-removable;
- enable-sdio-wakeup;
- keep-power-in-suspend;
- /*cap-power-off-card;*/
- cap-mmc-highspeed;
- /*fixed-emmc-driver-type;*/
- post-power-on-delay-ms = <200>;
-
- };
- /*SD*/
- sdio1:sdio1@16020000{
+ status = "disabled";
+ };
+
+ sdio1: sdio1@16020000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x16020000 0x0 0x10000>;
- interrupts = <75>;
- interrupt-parent = <&plic>;
clocks = <&dwmmc_biuclk>,<&dwmmc_ciuclk>;
clock-names = "biu","ciu";
- clock-frequency = <4000000>;
- max-frequency = <1000000>;
+ interrupts = <75>;
fifo-depth = <32>;
- card-detect-delay = <300>;
fifo-watermark-aligned;
data-addr = <0>;
- bus-width = <4>;
- cap-sd-highspeed;
- /*broken-cd;*/
- cap-sdio-irq;
- cap-mmc-hw-reset;
- non-removable;
- enable-sdio-wakeup;
- keep-power-in-suspend;
- /*cap-power-off-card;*/
- cap-mmc-highspeed;
- /*fixed-emmc-driver-type;*/
- post-power-on-delay-ms = <200>;
- };
- vin_sysctl:vin_sysctl@19800000 {
+ status = "disabled";
+ };
+
+ vin_sysctl: vin_sysctl@19800000 {
compatible = "starfive,stf-vin";
- reg = <0x0 0x19800000 0x0 0x10000>,//mipi-csi-0 mipi0
- <0x0 0x19810000 0x0 0x10000>,//dom-isp-cfg vclk
- <0x0 0x19820000 0x0 0x10000>,//mipirx-dphyapb config vrst
- <0x0 0x19830000 0x0 0x10000>,//reserved mipi1
- <0x0 0x19840000 0x0 0x10000>,//dom-isp-syscon sctrl
- <0x0 0x19870000 0x0 0x30000>,//ispv1-mini isp0
- <0x0 0x198a0000 0x0 0x30000>,//reserved isp1
- <0x0 0x11800000 0x0 0x10000>,//reserved tclk
- <0x0 0x11840000 0x0 0x10000>,//reserved trst
- <0x0 0x11858000 0x0 0x10000>,//reserved iopad
- <0x0 0x17030000 0x0 0x10000>, //pmu
- <0x0 0x13020000 0x0 0x10000>; //sys_crg
+ reg = <0x0 0x19800000 0x0 0x10000>,
+ <0x0 0x19810000 0x0 0x10000>,
+ <0x0 0x19820000 0x0 0x10000>,
+ <0x0 0x19830000 0x0 0x10000>,
+ <0x0 0x19840000 0x0 0x10000>,
+ <0x0 0x19870000 0x0 0x30000>,
+ <0x0 0x198a0000 0x0 0x30000>,
+ <0x0 0x11800000 0x0 0x10000>,
+ <0x0 0x11840000 0x0 0x10000>,
+ <0x0 0x11858000 0x0 0x10000>,
+ <0x0 0x17030000 0x0 0x10000>,
+ <0x0 0x13020000 0x0 0x10000>;
reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad", "pmu", "syscrg";
- interrupt-parent = <&plic>;
interrupts = <92 87 86>;
- // memory-region = <&vin_reserved>;
-
- ports {
- port@3 {
- reg = <2>; //dvp sensor
-
- /* Parallel bus endpoint */
- parallel_from_sc2235: endpoint {
- remote-endpoint = <&sc2235_to_parallel>;
- bus-type = <5>; /* Parallel */
- bus-width = <8>;
- data-shift = <2>; /* lines 9:2 are used */
- hsync-active = <1>;
- vsync-active = <0>;
- pclk-sample = <1>;
- status = "okay";
- };
- };
-
- port@4 {
- reg = <3>; //csi2rx0 sensor
-
- /* Parallel bus endpoint */
- csi2rx0_from_ov13850: endpoint {
- remote-endpoint = <&ov13850_to_csi2rx0>;
- bus-type = <4>; /* MIPI CSI-2 D-PHY */
- clock-lanes = <2>;
- data-lanes = <0 1>;
- status = "okay";
- };
- };
- };
+ status = "disabled";
};
+
jpu: jpu@11900000 {
- compatible = "starfive,jpu";
- reg = <0x0 0x13090000 0x0 0x300>;
- interrupt-parent = <&plic>;
- interrupts = <14>;
- clocks = <&jpuclk>;
- clock-names = "axi_clk", "core_clk", "apb_clk";
+ compatible = "starfive,jpu";
+ reg = <0x0 0x13090000 0x0 0x300>;
+ clocks = <&jpuclk>;
+ clock-names = "axi_clk", "core_clk", "apb_clk";
resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
<&rstgen RSTN_U0_CODAJ12_CORE>,
<&rstgen RSTN_U0_CODAJ12_APB>;
reset-names = "rst_axi",
"rst_core",
"rst_apb";
- status = "okay";
+ interrupts = <14>;
+ status = "disabled";
};
vpu_dec: vpu_dec@130A0000 {
- compatible = "starfive,vdec";
- reg = <0 0x130A0000 0 0x10000>;
- interrupt-parent = <&plic>;
- interrupts = <13>;
- clocks = <&vdec_rootclk>;
- clock-names = "axi_clk",
+ compatible = "starfive,vdec";
+ reg = <0 0x130A0000 0 0x10000>;
+ clocks = <&vdec_rootclk>;
+ clock-names = "axi_clk",
"bpu_clk",
"vce_clk",
"apb_clk",
"aximem_128b";
- //starfive,vdec_noc_ctrl;
- resets = <&rstgen RSTN_U0_WAVE511_AXI>,
+ resets = <&rstgen RSTN_U0_WAVE511_AXI>,
<&rstgen RSTN_U0_WAVE511_BPU>,
<&rstgen RSTN_U0_WAVE511_VCE>,
<&rstgen RSTN_U0_WAVE511_APB>,
<&rstgen RSTN_U0_AXIMEM_128B_AXI>;
- reset-names = "rst_axi",
+ reset-names = "rst_axi",
"rst_bpu",
"rst_vce",
"rst_apb",
"rst_sram";
- status = "okay";
+ interrupts = <13>;
+ status = "disabled";
};
- vpu_enc:vpu_enc@130B0000 {
+
+ vpu_enc: vpu_enc@130B0000 {
compatible = "cnm,cnm420l-vpu";
reg = <0x0 0x130B0000 0x0 0x10000>;
- interrupt-parent = <&plic>;
- interrupts = <15>;
+ reg-names = "control";
clocks = <&venc_rootclk>;
clock-names = "vcodec";
- reg-names = "control";
+ interrupts = <15>;
+ status = "disabled";
};
+
rstgen: reset-controller {
compatible = "starfive,jh7110-reset";
reg = <0x0 0x13020000 0x0 0x10000>,
status = "okay";
};
- /*gmac device configuration*/
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <256 128 64 32 0 0 0>;
};
- gmac0:gmac0@16030000{
+
+ gmac0: gmac0@16030000 {
compatible = "snps,dwc-qos-ethernet-5.10a";
reg = <0x0 0x16030000 0x0 0x10000>;
- interrupt-parent = <&plic>;
+ clocks = <&gmac_bus_clk>, <&gmac_rxtx_clk>, <&gmac_bus_clk>,<&gmac_ptp_clk>;
+ clock-names = "stmmaceth","phy_ref_clk", "apb_pclk","ptp_ref";
interrupts = <7>;
phy-reset-gpios = <&gpio 63 0>;
max-frame-size = <9000>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <262144>;
tx-fifo-depth = <131072>;
- clock-names = "stmmaceth","phy_ref_clk", "apb_pclk","ptp_ref";
- clocks = <&gmac_bus_clk>, <&gmac_rxtx_clk>, <&gmac_bus_clk>,<&gmac_ptp_clk>;
snps,fixed-burst;
snps,no-pbl-x8;
- /*snps,force_sf_dma_mode;*/
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,tso;
snps,burst-map = <0x7>;
snps,txpbl = <16>;
snps,rxpbl = <16>;
+ status = "disabled";
};
- gpu:gpu@18000000{
+ gpu: gpu@18000000 {
compatible = "img-gpu";
- interrupt-parent = <&plic>;
- interrupts = <82>;
reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
clocks = <&gpu_core_clk>, <&gpu_sys_clk>;
clock-names = "gpu_core_clk","gpu_sys_clk";
+ interrupts = <82>;
current-clock = <8000000>;
- status = "okay";
- };
+ status = "disabled";
+ };
- ipmscan0: can@130d0000 {
+ ipmscan0: can@130d0000 {
compatible = "ipms,can";
reg = <0x0 0x130d0000 0x0 0x1000>;
- interrupts = <112>;
- interrupt-parent = <&plic>;
clocks = <&canclk>;
clock-names = "ipms_can_clk";
+ interrupts = <112>;
+ status = "disabled";
};
- ipmscan1: can@130c0000 {
+ ipmscan1: can@130c0000 {
compatible = "ipms,canfd";
reg = <0x0 0x130c0000 0x0 0x1000>;
- interrupts = <113>;
- interrupt-parent = <&plic>;
clocks = <&canclk>;
clock-names = "ipms_can_clk";
+ interrupts = <113>;
+ status = "disabled";
};
- tdm: tdm@10090000 {
+ tdm: tdm@10090000 {
compatible = "starfive,tdm";
reg = <0x0 0x10090000 0x0 0x1000>;
reg-names = "tdm";
dmas = <&dma 20 1>, <&dma 21 1>;
dma-names = "rx","tx";
#sound-dai-cells = <0>;
+ status = "disabled";
};
spdif0: spdif0@100a0000 {
compatible = "starfive,sf-spdif";
reg = <0x0 0x100a0000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <84>;
- interrupt-names = "tx";
clocks = <&audioclk>;
clock-names = "audioclk";
+ interrupts = <84>;
+ interrupt-names = "tx";
#sound-dai-cells = <0>;
+ status = "disabled";
};
pwmdac: pwmdac@100b0000 {
dmas = <&dma 22 1>;
dma-names = "tx";
#sound-dai-cells = <0>;
+ status = "disabled";
};
- i2stx: i2stx@100c0000 {
+ i2stx: i2stx@100c0000 {
compatible = "snps,designware-i2stx";
reg = <0x0 0x100c0000 0x0 0x1000>;
- interrupt-names = "tx";
clocks = <&apb0clk>;
clock-names = "i2sclk";
+ interrupt-names = "tx";
#sound-dai-cells = <0>;
- dmas = <&dma 28>;
+ dmas = <&dma 28 1>;
dma-names = "rx";
+ status = "disabled";
};
pdm: pdm@100d0000 {
clocks = <&audioclk>;
clock-names = "audioclk";
#sound-dai-cells = <0>;
+ status = "disabled";
};
i2srx_3ch: i2srx-3ch@100e0000 {
compatible = "snps,designware-i2srx";
reg = <0x0 0x100e0000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- /*interrupts = <42>, <43>, <44>;*/
- /*interrupt-names = "rx-ch0","rx-ch1","rx-ch2";*/
- interrupts = <42>;
- interrupt-names = "rx";
clocks = <&apb0clk>;
clock-names = "i2sclk";
+ interrupts = <42>;
+ interrupt-names = "rx";
#sound-dai-cells = <0>;
+ status = "disabled";
};
i2stx_4ch0: i2stx-4ch0@120b0000 {
compatible = "snps,designware-i2stx-4ch0";
reg = <0x0 0x120b0000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <58>;
- interrupt-names = "tx";
clocks = <&apb0clk>;
clock-names = "i2sclk";
+ interrupts = <58>;
+ interrupt-names = "tx";
#sound-dai-cells = <0>;
+ status = "disabled";
};
i2stx_4ch1: i2sdac1@120c0000 {
compatible = "snps,designware-i2stx-4ch1";
reg = <0x0 0x120c0000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <59>;
- interrupt-names = "tx";
clocks = <&apb0clk>;
clock-names = "i2sclk";
+ interrupts = <59>;
+ interrupt-names = "tx";
#sound-dai-cells = <0>;
+ status = "disabled";
};
ptc: pwm@120d0000 {
compatible = "starfive,pwm0";
reg = <0x0 0x120d0000 0x0 0x10000>;
reg-names = "control";
- sifive,approx-period = <1000000>;
clocks = <&pwmclk>;
+ sifive,approx-period = <1000000>;
#pwm-cells=<3>;
sifive,npwm = <8>;
- };
-
- ac108_mclk: ac108_mclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- wm8960_mclk: wm8960_mclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <4000000>;
+ status = "disabled";
};
spdif_transmitter: spdif_transmitter {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
+ status = "disabled";
};
spdif_receiver: spdif_receiver {
compatible = "linux,spdif-dir";
#sound-dai-cells = <0>;
+ status = "disabled";
};
pwmdac_codec: pwmdac-transmitter {
compatible = "linux,pwmdac-dit";
#sound-dai-cells = <0>;
+ status = "disabled";
};
dmic_codec: dmic_codec {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
+ status = "disabled";
};
- spi0:spi0@10060000 {
+ spi0: spi0@10060000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x10060000 0x0 0x10000>;
clocks = <&ahb1clk>;
clock-names = "apb_pclk";
+ interrupts = <38>;
dmas = <&dma 14 1>, <&dma 15 1>;
dma-names = "rx","tx";
- #address-cells = <1>;
- #size-cells = <0>;
arm,primecell-periphid = <0x00041022>;
- interrupt-parent = <&plic>;
- interrupts = <38>;
num-cs = <1>;
- spi_dev0: spi@0 {
- compatible = "rohm,dh2228fv";
- pl022,com-mode = <1>;
- spi-max-frequency = <10000000>;
- reg = <0>;
- status = "okay";
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
- pcie0:pcie0@2B000000 {
+ pcie0: pcie0@2B000000 {
compatible = "plda,pci-xpressrich3-axi";
reg = <0x0 0x2B000000 0x0 0x1000000
0x9 0x40000000 0x0 0x10000000>;
reg-names = "reg", "config";
- device_type = "pci";
- bus-range = <0x0 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x06000000>;
- msi-parent = <&plic>;
interrupts = <56>;
interrupt-controller;
interrupt-names = "msi";
- interrupt-parent = <&plic>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
<0x0 0x0 0x0 0x2 &plic 0x2>,
<0x0 0x0 0x0 0x3 &plic 0x3>,
<0x0 0x0 0x0 0x4 &plic 0x4>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ msi-parent = <&plic>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x06000000>;
+ status = "disabled";
};
mailbox_contrl0: mailbox@0 {
compatible = "starfive,mail_box";
reg = <0x0 0x13060000 0x0 0x0001000>;
- interrupt-parent = <&plic>;
interrupts = <26 27>;
#mbox-cells = <2>;
+ status = "disabled";
};
- mailbox_client@0 {
+ mailbox_client0: mailbox_client@0 {
compatible = "starfive,mailbox-test";
- interrupt-parent = <&plic>;
mbox-names = "rx", "tx";
mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
+ status = "disabled";
};
- display-subsystem {
+ display: display-subsystem {
compatible = "verisilicon,display-subsystem";
- //memory-region = <&sffb_reserved>;
ports = <&dc_out_dpi0>;
- status = "okay";
+ status = "disabled";
};
- display-encoder {
+ encoder: display-encoder {
compatible = "starfive,display-encoder";
- encoder-type = <2>; //2-TMDS, 3-LVDS, 6-DSI, 8-DPI
- status = "okay";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7513_0_in>;
- //remote-endpoint = <&dsi_0_in>;
- };
- };
-
- port@1 {
- endpoint {
- remote-endpoint = <&dc_out_dpi0>;
- };
- };
-
- };
+ status = "disabled";
};
dc8200@29400000 {
compatible = "verisilicon,dc8200";
reg = <0x0 0x29400000 0x0 0x100>,<0x0 0x29400800 0x0 0x2000>;
- interrupt-parent = <&plic>;
interrupts = <95>;
port {
remote-endpoint = <&vd_input>;*/
};
};
+ };
- /*port: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
+ sound_pwmdac: snd-card_pwmdac {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
+ simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
+ simple-audio-card,frame-master = <&pwmdac_dailink_master>;
+ simple-audio-card,format = "left_j";
+ status = "disabled";
- crtc_0_out: endpoint {
- };
- };*/
+ pwmdac_dailink_master: simple-audio-card,cpu {
+ sound-dai = <&pwmdac>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&pwmdac_codec>;
+ };
};
};
};
-
-#include "starfive_jh7110_pinctrl.dtsi"
-#include "starfive_jh7110_audio.dtsi"
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
/ {
- oscclk:oscclk{
- #clock-cells = <0>;
+ oscclk: oscclk {
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "oscclk";
};
- pll0clk:pll0clk{
- #clock-cells = <0>;
+
+ pll0clk: pll0clk {
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <1000000000>;
clock-output-names = "pll0clk";
};
- pll1clk:pll1clk{
- #clock-cells = <0>;
+
+ pll1clk: pll1clk {
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <1066000000>;
clock-output-names = "pll1clk";
};
- pll2clk:pll2clk{
- #clock-cells = <0>;
+
+ pll2clk: pll2clk {
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <1228800000>;
clock-output-names = "pll2clk";
};
+
rtcclk: rtcclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <4000000>;
clock-output-names = "rtcclk";
};
+
rtc_hmsclk: rtc_hmsclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <32768>;
};
+
perh_rootclk: perh_rootclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <500000000>;
};
+
ahb0clk: ahb0clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <204800000>;
};
+
ahb1clk: ahb1clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <204800000>;
};
+
apb0clk: apb0clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <512000000>;
};
+
apb2clk: apb2clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <49500000>;
};
+
apb12clk: apb12clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <49500000>;
};
+
jpuclk: jpuclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <204800000>;
};
+
vdec_rootclk: vdec_rootclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <400000000>;
};
+
venc_rootclk: venc_rootclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <245760000>;
};
+
gmac_bus_clk: gmac_bus_clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <4000000>;
};
+
gmac_rxtx_clk: gmac_rxtx_clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <2500000>;
};
+
gmac_ptp_clk: gmac_ptp_clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <2500000>;
};
+
qspi_clk: qspi-clk@0 {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <50000000>;
};
+
uartclk: uartclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <51200000>;
};
+
dwmmc_biuclk: dwmmc_biuclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <4000000>;
};
+
dwmmc_ciuclk: dwmmc_ciuclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <4000000>;
};
+
stg_axiahb_clk: stg_axiahb_clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <204800000>;
};
+
stg_apbclk: stg_apbclk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <51200000>;
};
gpu_core_clk: gpu_core_clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <24000000>;
};
+
gpu_sys_clk: gpu_sys_clk {
- #clock-cells = <0>;
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <24000000>;
};
+
pwmclk: pwmclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- };
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
audioclk: audioclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12288000>;
- };
- clk_ext_camera: clk-ext-camera {
+ compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ clk_ext_camera: clk-ext-camera {
compatible = "fixed-clock";
+ #clock-cells = <0>;
clock-frequency = <24000000>;
};
+
canclk: canclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
/* clock tree external clocks */
osc: osc {
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
sf,pin-gpio-doen = <OEN_LOW>;
};
};
-
+
gmac1_pins: gmac1-pins {
gmac1-pins0 {
sf,pins = <PAD_GMAC1_MDC>;
sf,pin-gpio-doen = <OEN_I2C0_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C0_IC_CLK_IN_A>;
};
-
+
i2c0-pins-sda {
sf,pins = <PAD_GPIO51>;
sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
sf,pin-gpio-din = <GPI_I2C0_IC_DATA_IN_A>;
};
};
-
+
i2c6_pins: i2c6-pins {
i2c6-pins-scl {
sf,pins = <PAD_GPIO20>;
sf,pin-gpio-doen = <OEN_I2C6_IC_CLK_OE>;
sf,pin-gpio-din = <GPI_I2C6_IC_CLK_IN_A>;
};
-
+
i2c6-pins-sda {
sf,pins = <PAD_GPIO19>;
sf,pinmux = <PAD_GPIO19_FUNC_SEL 0>;
sf,pin-gpio-din = <GPI_I2C6_IC_DATA_IN_A>;
};
};
-
+
mmc0_pins: mmc0-pins {
mmc0-pins-rest {
sf,pins = <PAD_GPIO62>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
-
+
mmc1_pins: mmc1-pins {
mmc1-pins0 {
sf,pins = <PAD_GPIO10>;
sf,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
mmc1-pins1 {
sf,pins = <PAD_GPIO9>;
sf,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
sf,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
};
-
+
mmc1-pins2 {
sf,pins = <PAD_GPIO11>;
sf,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
};
-
+
mmc1-pins3 {
sf,pins = <PAD_GPIO12>;
sf,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
};
-
+
mmc1-pins4 {
sf,pins = <PAD_GPIO7>;
sf,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
};
};
-
+
pwmdac0_pins: pwmdac0-pins {
pwmdac0-pins-left {
sf,pins = <PAD_GPIO19>;
sf,pin-gpio-dout = <GPO_PWMDAC0_LEFT_OUTPUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
pwmdac0-pins-right {
sf,pins = <PAD_GPIO42>;
sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
-
+
i2s_clk_pins: i2s-clk0 {
i2s-clk0_mclk {
sf,pins = <PAD_GPIO32>;
sf,pinmux = <PAD_GPIO32_FUNC_SEL 0>;
sf,pin-ioconfig = <IO(GPIO_IE(1))>;
- sf,pin-gpio-dout = <GPO_CRG0_MCLK_OUT>;
+ sf,pin-gpio-dout = <GPO_CRG0_MCLK_OUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
i2s-clk0_bclk {
sf,pins = <PAD_GPIO37>;
sf,pinmux = <PAD_GPIO37_FUNC_SEL 0>;
sf,pin-gpio-dout = <GPO_I2SRX0_BCLK_MST>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
i2s-clk0_lrclk {
sf,pins = <PAD_GPIO25>;
sf,pinmux = <PAD_GPIO25_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
-
+
i2stx_pins: i2stx-pins {
i2stx-pins0 {
sf,pins = <PAD_GPIO18>;
sf,pin-gpio-dout = <GPO_CAN0_CTRL_TXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
can0-pins1 {
sf,pins = <PAD_GPIO27>;
sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_CAN0_CTRL_RXD>;
};
-
+
can0-pins2 {
sf,pins = <PAD_GPIO45>;
sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
-
+
can1_pins: can1-pins {
can1-pins0 {
sf,pins = <PAD_GPIO28>;
sf,pin-gpio-dout = <GPO_CAN1_CTRL_TXD>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
can1-pins1 {
sf,pins = <PAD_GPIO27>;
sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_CAN1_CTRL_RXD>;
};
-
+
can1-pins2 {
sf,pins = <PAD_GPIO45>;
sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_PTC0_PWM_0_OE_N>;
};
};
-
+
ssp0_pins: ssp0-pins {
ssp0-pins_tx {
sf,pins = <PAD_GPIO57>;
sf,pin-gpio-doen = <OEN_HIGH>;
sf,pin-gpio-din = <GPI_SPI0_SSPRXD>;
};
-
+
ssp0-pins_clk {
sf,pins = <PAD_GPIO61>;
sf,pinmux = <PAD_GPIO61_FUNC_SEL 0>;
sf,pin-gpio-dout = <GPO_SPI0_SSPCLKOUT>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
ssp0-pins_cs {
sf,pins = <PAD_GPIO14>;
sf,pinmux = <PAD_GPIO14_FUNC_SEL 0>;
sf,pin-gpio-doen = <OEN_LOW>;
};
};
-
+
sc2235_pins: sc2235-pins {
sc2235-1V8-pins {
sf,pins = <PAD_GPIO11>;
sf,pin-gpio-dout = <GPO_HIGH>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
sc2235-1V5-pins {
sf,pins = <PAD_GPIO12>;
sf,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
sf,pin-gpio-dout = <GPO_HIGH>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
sc2235-2V8-pins {
sf,pins = <PAD_GPIO10>;
sf,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
sf,pin-gpio-dout = <GPO_HIGH>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
sc2235-reset-pins {
sf,pins = <PAD_GPIO16>;
sf,pinmux = <PAD_GPIO16_FUNC_SEL 0>;
sf,pin-gpio-dout = <GPO_HIGH>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
sc2235-pwdn-pins {
sf,pins = <PAD_GPIO15>;
sf,pinmux = <PAD_GPIO15_FUNC_SEL 0>;
sf,pin-gpio-dout = <GPO_HIGH>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
sc2235-esync-pins {
sf,pins = <PAD_GPIO17>;
sf,pinmux = <PAD_GPIO17_FUNC_SEL 0>;
sf,pin-gpio-dout = <GPO_LOW>;
sf,pin-gpio-doen = <OEN_LOW>;
};
-
+
sc2235-oen-pins {
sf,pins = <PAD_GPIO18>;
sf,pinmux = <PAD_GPIO18_FUNC_SEL 0>;
};
&gpioa {
-
pwm_ch4_pins: pwm_ch4-pins {
pwm_ch4-pins0 {
sf,pins = <PAD_RGPIO2>;
sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_4>;
};
};
-
};
&gmac0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "okay";
-};
-
+};
\ No newline at end of file
+++ /dev/null
-&soc{
- sound_pwmdac:snd-card_pwmdac{
- compatible = "simple-audio-card";
- simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
- simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
- simple-audio-card,frame-master = <&pwmdac_dailink_master>;
- simple-audio-card,format = "left_j";
- pwmdac_dailink_master:simple-audio-card,cpu {
- sound-dai = <&pwmdac>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&pwmdac_codec>;
- };
- };
-
- sound_wm8960:snd-card-wm8960{
- compatible = "simple-audio-card";
- simple-audio-card,name = "Starfive-wm8960-Sound-Card";
- /* i2s + wm8960 */
- simple-audio-card,dai-link@0 {
- reg = <0>;
- status = "okay";
- format = "i2s";
- bitclock-master = <&sndcodec0>;
- frame-master = <&sndcodec0>;
-
- widgets =
- "Microphone", "Mic Jack",
- "Line", "Line In",
- "Line", "Line Out",
- "Speaker", "Speaker",
- "Headphone", "Headphone Jack";
- routing =
- "Headphone Jack", "HP_L",
- "Headphone Jack", "HP_R",
- "Speaker", "SPK_LP",
- "Speaker", "SPK_LN",
- "LINPUT1", "Mic Jack",
- "LINPUT3", "Mic Jack",
- "RINPUT1", "Mic Jack",
- "RINPUT2", "Mic Jack";
- cpu0 {
- sound-dai = <&i2stx_4ch1>;
- };
- cpu1 {
- sound-dai = <&i2srx_3ch>;
- };
-
- sndcodec0:codec {
- sound-dai = <&wm8960>;
- clocks = <&audioclk>;
- clock-names = "mclk";
- };
- };
- };
-
- sound_spdif:snd-card-spdif{
- compatible = "simple-audio-card";
- simple-audio-card,name = "SF-SPDIF-Sound-Card";
- simple-audio-card,bitclock-master = <&spdif_dailink_master>;
- simple-audio-card,frame-master = <&spdif_dailink_master>;
- simple-audio-card,format = "left_j";
- spdif_dailink_master:simple-audio-card,cpu {
- sound-dai = <&spdif0>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&spdif_transmitter>;
- };
- };
-
- sound_pdm:snd-card-pdm{
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "SF-PDM-Sound-Card";
- simple-audio-card,bitclock-master = <&pdm_dailink_master>;
- simple-audio-card,frame-master = <&pdm_dailink_master>;
- status = "okay";
- simple-audio-card,cpu {
- sound-dai = <&i2srx_3ch>;
- };
-
- pdm_dailink_master:simple-audio-card,codec {
- sound-dai = <&pdm>;
- };
- };
-};
\ No newline at end of file
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
#ifndef _DT_BINDINGS_PINCTRL_STARFIVE_H
#define _DT_BINDINGS_PINCTRL_STARFIVE_H
#define U0_SYS_CRG_CLK_GCLK0 7
#define U0_SYS_CRG_CLK_GCLK1 8
#define U0_SYS_CRG_CLK_GCLK2 9
-
+
//===============================GPIO_OEN_SELECT=======================================
// gpio_oen config:
// every define below is a couple of signal and signal idx
//gpo(n)_dout signal pool
#define GPO_LOW 0
#define GPO_HIGH 1
-#define GPO_CAN0_CTRL_STBY GPO_SYS_IOMUX_U0_CAN_CTRL_STBY
-#define GPO_CAN0_CTRL_TST_NEXT_BIT GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT
-#define GPO_CAN0_CTRL_TST_SAMPLE_POINT GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT
-#define GPO_CAN0_CTRL_TXD GPO_SYS_IOMUX_U0_CAN_CTRL_TXD
-#define GPO_CAN1_CTRL_STBY GPO_SYS_IOMUX_U1_CAN_CTRL_STBY
-#define GPO_CAN1_CTRL_TST_NEXT_BIT GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT
-#define GPO_CAN1_CTRL_TST_SAMPLE_POINT GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT
-#define GPO_CAN1_CTRL_TXD GPO_SYS_IOMUX_U1_CAN_CTRL_TXD
-#define GPO_CRG0_MCLK_OUT GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT
-#define GPO_GMAC0_CLK_PHY GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY
-#define GPO_HDMI0_CEC_SDA_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT
-#define GPO_HDMI0_DDC_SCL_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT
-#define GPO_HDMI0_DDC_SDA_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT
-#define GPO_I2C0_IC_CLK_OUT_A GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A
-#define GPO_I2C0_IC_DATA_OUT_A GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A
-#define GPO_I2C1_IC_CLK_OUT_A GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A
-#define GPO_I2C1_IC_DATA_OUT_A GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A
-#define GPO_I2C2_IC_CLK_OUT_A GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A
-#define GPO_I2C2_IC_DATA_OUT_A GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A
-#define GPO_I2C3_IC_CLK_OUT_A GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A
-#define GPO_I2C3_IC_DATA_OUT_A GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A
-#define GPO_I2C4_IC_CLK_OUT_A GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A
-#define GPO_I2C4_IC_DATA_OUT_A GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A
-#define GPO_I2C5_IC_CLK_OUT_A GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A
-#define GPO_I2C5_IC_DATA_OUT_A GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A
-#define GPO_I2C6_IC_CLK_OUT_A GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A
-#define GPO_I2C6_IC_DATA_OUT_A GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A
-#define GPO_I2SRX0_BCLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST
-#define GPO_I2SRX0_LRCK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST
-#define GPO_I2STX_4CH1_SDO0 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0
-#define GPO_I2STX_4CH1_SDO1 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1
-#define GPO_I2STX_4CH1_SDO2 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2
-#define GPO_I2STX_4CH1_SDO3 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3
-#define GPO_I2STX0_BCLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST
-#define GPO_I2STX0_LRCK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST
-#define GPO_JTAG_CPU_CERTIFICATION_TDO GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO
-#define GPO_JTAG_DSP_TDO GPO_SYS_IOMUX_U0_HIFI4_JTDO
-#define GPO_PDM_4MIC0_DMIC_MCLK GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK
-#define GPO_PTC0_PWM_0 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0
-#define GPO_PTC0_PWM_1 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1
-#define GPO_PTC0_PWM_2 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2
-#define GPO_PTC0_PWM_3 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3
-#define GPO_PWMDAC0_LEFT_OUTPUT GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT
-#define GPO_PWMDAC0_RIGHT_OUTPUT GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT
-#define GPO_QSPI0_CSN1 GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1
-#define GPO_SDIO0_BACK_END_POWER GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER
-#define GPO_SDIO0_CARD_POWER_EN GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN
-#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N
-#define GPO_SDIO0_RST_N GPO_SYS_IOMUX_U0_DW_SDIO_RST_N
-#define GPO_SDIO1_BACK_END_POWER GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER
-#define GPO_SDIO1_CARD_POWER_EN GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN
-#define GPO_SDIO1_CCLK_OUT GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT
-#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N
-#define GPO_SDIO1_CCMD_OUT GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT
-#define GPO_SDIO1_CDATA_OUT_0 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0
-#define GPO_SDIO1_CDATA_OUT_1 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1
-#define GPO_SDIO1_CDATA_OUT_2 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2
-#define GPO_SDIO1_CDATA_OUT_3 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3
-#define GPO_SDIO1_CDATA_OUT_4 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4
-#define GPO_SDIO1_CDATA_OUT_5 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5
-#define GPO_SDIO1_CDATA_OUT_6 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6
-#define GPO_SDIO1_CDATA_OUT_7 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7
-#define GPO_SDIO1_RST_N GPO_SYS_IOMUX_U1_DW_SDIO_RST_N
-#define GPO_SPDIF0_SPDIFO GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO
-#define GPO_SPI0_SSPCLKOUT GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT
-#define GPO_SPI0_SSPFSSOUT GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT
-#define GPO_SPI0_SSPTXD GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD
-#define GPO_SPI1_SSPCLKOUT GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT
-#define GPO_SPI1_SSPFSSOUT GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT
-#define GPO_SPI1_SSPTXD GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD
-#define GPO_SPI2_SSPCLKOUT GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT
-#define GPO_SPI2_SSPFSSOUT GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT
-#define GPO_SPI2_SSPTXD GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD
-#define GPO_SPI3_SSPCLKOUT GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT
-#define GPO_SPI3_SSPFSSOUT GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT
-#define GPO_SPI3_SSPTXD GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD
-#define GPO_SPI4_SSPCLKOUT GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT
-#define GPO_SPI4_SSPFSSOUT GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT
-#define GPO_SPI4_SSPTXD GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD
-#define GPO_SPI5_SSPCLKOUT GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT
-#define GPO_SPI5_SSPFSSOUT GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT
-#define GPO_SPI5_SSPTXD GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD
-#define GPO_SPI6_SSPCLKOUT GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT
-#define GPO_SPI6_SSPFSSOUT GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT
-#define GPO_SPI6_SSPTXD GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD
-#define GPO_TDM0_CLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST
-#define GPO_TDM0_PCM_SYNCOUT GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT
-#define GPO_TDM0_PCM_TXD GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD
-#define GPO_U7MC_TRACE0_TDATA_0 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0
-#define GPO_U7MC_TRACE0_TDATA_1 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1
-#define GPO_U7MC_TRACE0_TDATA_2 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2
-#define GPO_U7MC_TRACE0_TDATA_3 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3
-#define GPO_U7MC_TRACE0_TREF GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF
-#define GPO_UART0_SOUT GPO_SYS_IOMUX_U0_DW_UART_SOUT
-#define GPO_UART1_RTS_N GPO_SYS_IOMUX_U1_DW_UART_RTS_N
-#define GPO_UART1_SOUT GPO_SYS_IOMUX_U1_DW_UART_SOUT
-#define GPO_UART2_RTS_N GPO_SYS_IOMUX_U2_DW_UART_RTS_N
-#define GPO_UART2_SOUT GPO_SYS_IOMUX_U2_DW_UART_SOUT
-#define GPO_UART3_SOUT GPO_SYS_IOMUX_U3_DW_UART_SOUT
-#define GPO_UART4_RTS_N GPO_SYS_IOMUX_U4_DW_UART_RTS_N
-#define GPO_UART4_SOUT GPO_SYS_IOMUX_U4_DW_UART_SOUT
-#define GPO_UART5_RTS_N GPO_SYS_IOMUX_U5_DW_UART_RTS_N
-#define GPO_UART5_SOUT GPO_SYS_IOMUX_U5_DW_UART_SOUT
-#define GPO_USB0_DRIVE_VBUS_IO GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO
-#define GPO_WAVE511_0_O_UART_TXSOUT GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT
-#define GPO_WDT0_WDOGRES GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES
+#define GPO_CAN0_CTRL_STBY GPO_SYS_IOMUX_U0_CAN_CTRL_STBY
+#define GPO_CAN0_CTRL_TST_NEXT_BIT GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT
+#define GPO_CAN0_CTRL_TST_SAMPLE_POINT GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT
+#define GPO_CAN0_CTRL_TXD GPO_SYS_IOMUX_U0_CAN_CTRL_TXD
+#define GPO_CAN1_CTRL_STBY GPO_SYS_IOMUX_U1_CAN_CTRL_STBY
+#define GPO_CAN1_CTRL_TST_NEXT_BIT GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT
+#define GPO_CAN1_CTRL_TST_SAMPLE_POINT GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT
+#define GPO_CAN1_CTRL_TXD GPO_SYS_IOMUX_U1_CAN_CTRL_TXD
+#define GPO_CRG0_MCLK_OUT GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT
+#define GPO_GMAC0_CLK_PHY GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY
+#define GPO_HDMI0_CEC_SDA_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT
+#define GPO_HDMI0_DDC_SCL_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT
+#define GPO_HDMI0_DDC_SDA_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT
+#define GPO_I2C0_IC_CLK_OUT_A GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C0_IC_DATA_OUT_A GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C1_IC_CLK_OUT_A GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C1_IC_DATA_OUT_A GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C2_IC_CLK_OUT_A GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C2_IC_DATA_OUT_A GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C3_IC_CLK_OUT_A GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C3_IC_DATA_OUT_A GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C4_IC_CLK_OUT_A GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C4_IC_DATA_OUT_A GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C5_IC_CLK_OUT_A GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C5_IC_DATA_OUT_A GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C6_IC_CLK_OUT_A GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C6_IC_DATA_OUT_A GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2SRX0_BCLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST
+#define GPO_I2SRX0_LRCK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST
+#define GPO_I2STX_4CH1_SDO0 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0
+#define GPO_I2STX_4CH1_SDO1 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1
+#define GPO_I2STX_4CH1_SDO2 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2
+#define GPO_I2STX_4CH1_SDO3 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3
+#define GPO_I2STX0_BCLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST
+#define GPO_I2STX0_LRCK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST
+#define GPO_JTAG_CPU_CERTIFICATION_TDO GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO
+#define GPO_JTAG_DSP_TDO GPO_SYS_IOMUX_U0_HIFI4_JTDO
+#define GPO_PDM_4MIC0_DMIC_MCLK GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK
+#define GPO_PTC0_PWM_0 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0
+#define GPO_PTC0_PWM_1 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1
+#define GPO_PTC0_PWM_2 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2
+#define GPO_PTC0_PWM_3 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3
+#define GPO_PWMDAC0_LEFT_OUTPUT GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT
+#define GPO_PWMDAC0_RIGHT_OUTPUT GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT
+#define GPO_QSPI0_CSN1 GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1
+#define GPO_SDIO0_BACK_END_POWER GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER
+#define GPO_SDIO0_CARD_POWER_EN GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN
+#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N
+#define GPO_SDIO0_RST_N GPO_SYS_IOMUX_U0_DW_SDIO_RST_N
+#define GPO_SDIO1_BACK_END_POWER GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER
+#define GPO_SDIO1_CARD_POWER_EN GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN
+#define GPO_SDIO1_CCLK_OUT GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT
+#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N
+#define GPO_SDIO1_CCMD_OUT GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT
+#define GPO_SDIO1_CDATA_OUT_0 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0
+#define GPO_SDIO1_CDATA_OUT_1 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1
+#define GPO_SDIO1_CDATA_OUT_2 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2
+#define GPO_SDIO1_CDATA_OUT_3 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3
+#define GPO_SDIO1_CDATA_OUT_4 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4
+#define GPO_SDIO1_CDATA_OUT_5 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5
+#define GPO_SDIO1_CDATA_OUT_6 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6
+#define GPO_SDIO1_CDATA_OUT_7 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7
+#define GPO_SDIO1_RST_N GPO_SYS_IOMUX_U1_DW_SDIO_RST_N
+#define GPO_SPDIF0_SPDIFO GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO
+#define GPO_SPI0_SSPCLKOUT GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT
+#define GPO_SPI0_SSPFSSOUT GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT
+#define GPO_SPI0_SSPTXD GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD
+#define GPO_SPI1_SSPCLKOUT GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT
+#define GPO_SPI1_SSPFSSOUT GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT
+#define GPO_SPI1_SSPTXD GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD
+#define GPO_SPI2_SSPCLKOUT GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT
+#define GPO_SPI2_SSPFSSOUT GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT
+#define GPO_SPI2_SSPTXD GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD
+#define GPO_SPI3_SSPCLKOUT GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT
+#define GPO_SPI3_SSPFSSOUT GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT
+#define GPO_SPI3_SSPTXD GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD
+#define GPO_SPI4_SSPCLKOUT GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT
+#define GPO_SPI4_SSPFSSOUT GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT
+#define GPO_SPI4_SSPTXD GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD
+#define GPO_SPI5_SSPCLKOUT GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT
+#define GPO_SPI5_SSPFSSOUT GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT
+#define GPO_SPI5_SSPTXD GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD
+#define GPO_SPI6_SSPCLKOUT GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT
+#define GPO_SPI6_SSPFSSOUT GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT
+#define GPO_SPI6_SSPTXD GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD
+#define GPO_TDM0_CLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST
+#define GPO_TDM0_PCM_SYNCOUT GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT
+#define GPO_TDM0_PCM_TXD GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD
+#define GPO_U7MC_TRACE0_TDATA_0 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0
+#define GPO_U7MC_TRACE0_TDATA_1 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1
+#define GPO_U7MC_TRACE0_TDATA_2 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2
+#define GPO_U7MC_TRACE0_TDATA_3 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3
+#define GPO_U7MC_TRACE0_TREF GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF
+#define GPO_UART0_SOUT GPO_SYS_IOMUX_U0_DW_UART_SOUT
+#define GPO_UART1_RTS_N GPO_SYS_IOMUX_U1_DW_UART_RTS_N
+#define GPO_UART1_SOUT GPO_SYS_IOMUX_U1_DW_UART_SOUT
+#define GPO_UART2_RTS_N GPO_SYS_IOMUX_U2_DW_UART_RTS_N
+#define GPO_UART2_SOUT GPO_SYS_IOMUX_U2_DW_UART_SOUT
+#define GPO_UART3_SOUT GPO_SYS_IOMUX_U3_DW_UART_SOUT
+#define GPO_UART4_RTS_N GPO_SYS_IOMUX_U4_DW_UART_RTS_N
+#define GPO_UART4_SOUT GPO_SYS_IOMUX_U4_DW_UART_SOUT
+#define GPO_UART5_RTS_N GPO_SYS_IOMUX_U5_DW_UART_RTS_N
+#define GPO_UART5_SOUT GPO_SYS_IOMUX_U5_DW_UART_SOUT
+#define GPO_USB0_DRIVE_VBUS_IO GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO
+#define GPO_WAVE511_0_O_UART_TXSOUT GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT
+#define GPO_WDT0_WDOGRES GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES
#define GPO_NONE GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD + 1
//gpo(n)_doen signal pool
#define OEN_LOW 0
#define OEN_HIGH 1
-#define OEN_HDMI0_CEC_SDA_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN
-#define OEN_HDMI0_DDC_SCL_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN
-#define OEN_HDMI0_DDC_SDA_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN
-#define OEN_I2C0_IC_CLK_OE GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE
-#define OEN_I2C0_IC_DATA_OE GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE
-#define OEN_I2C1_IC_CLK_OE GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE
-#define OEN_I2C1_IC_DATA_OE GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE
-#define OEN_I2C2_IC_CLK_OE GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE
-#define OEN_I2C2_IC_DATA_OE GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE
-#define OEN_I2C3_IC_CLK_OE GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE
-#define OEN_I2C3_IC_DATA_OE GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE
-#define OEN_I2C4_IC_CLK_OE GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE
-#define OEN_I2C4_IC_DATA_OE GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE
-#define OEN_I2C5_IC_CLK_OE GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE
-#define OEN_I2C5_IC_DATA_OE GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE
-#define OEN_I2C6_IC_CLK_OE GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE
-#define OEN_I2C6_IC_DATA_OE GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE
-#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE
-#define OEN_JTAG_DSP_TDO_OEN GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN
-#define OEN_PTC0_PWM_0_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0
-#define OEN_PTC0_PWM_1_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1
-#define OEN_PTC0_PWM_2_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2
-#define OEN_PTC0_PWM_3_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3
-#define OEN_SDIO1_CCMD_OUT_EN GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN
-#define OEN_SDIO1_CDATA_OUT_EN_0 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0
-#define OEN_SDIO1_CDATA_OUT_EN_1 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1
-#define OEN_SDIO1_CDATA_OUT_EN_2 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2
-#define OEN_SDIO1_CDATA_OUT_EN_3 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3
-#define OEN_SDIO1_CDATA_OUT_EN_4 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4
-#define OEN_SDIO1_CDATA_OUT_EN_5 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5
-#define OEN_SDIO1_CDATA_OUT_EN_6 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6
-#define OEN_SDIO1_CDATA_OUT_EN_7 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7
-#define OEN_SPI0_NSSPCTLOE GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE
-#define OEN_SPI0_NSSPOE GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE
-#define OEN_SPI1_NSSPCTLOE GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE
-#define OEN_SPI1_NSSPOE GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE
-#define OEN_SPI2_NSSPCTLOE GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE
-#define OEN_SPI2_NSSPOE GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE
-#define OEN_SPI3_NSSPCTLOE GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE
-#define OEN_SPI3_NSSPOE GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE
-#define OEN_SPI4_NSSPCTLOE GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE
-#define OEN_SPI4_NSSPOE GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE
-#define OEN_SPI5_NSSPCTLOE GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE
-#define OEN_SPI5_NSSPOE GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE
-#define OEN_SPI6_NSSPCTLOE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE
-#define OEN_SPI6_NSSPOE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE
-#define OEN_TDM0_NPCM_SYNCOE GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE
-#define OEN_TDM0_NPCM_TXDOE GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE
-#define OEN_NONE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE + 1
+#define OEN_HDMI0_CEC_SDA_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN
+#define OEN_HDMI0_DDC_SCL_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN
+#define OEN_HDMI0_DDC_SDA_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN
+#define OEN_I2C0_IC_CLK_OE GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE
+#define OEN_I2C0_IC_DATA_OE GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE
+#define OEN_I2C1_IC_CLK_OE GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE
+#define OEN_I2C1_IC_DATA_OE GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE
+#define OEN_I2C2_IC_CLK_OE GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE
+#define OEN_I2C2_IC_DATA_OE GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE
+#define OEN_I2C3_IC_CLK_OE GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE
+#define OEN_I2C3_IC_DATA_OE GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE
+#define OEN_I2C4_IC_CLK_OE GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE
+#define OEN_I2C4_IC_DATA_OE GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE
+#define OEN_I2C5_IC_CLK_OE GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE
+#define OEN_I2C5_IC_DATA_OE GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE
+#define OEN_I2C6_IC_CLK_OE GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE
+#define OEN_I2C6_IC_DATA_OE GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE
+#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE
+#define OEN_JTAG_DSP_TDO_OEN GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN
+#define OEN_PTC0_PWM_0_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0
+#define OEN_PTC0_PWM_1_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1
+#define OEN_PTC0_PWM_2_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2
+#define OEN_PTC0_PWM_3_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3
+#define OEN_SDIO1_CCMD_OUT_EN GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN
+#define OEN_SDIO1_CDATA_OUT_EN_0 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0
+#define OEN_SDIO1_CDATA_OUT_EN_1 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1
+#define OEN_SDIO1_CDATA_OUT_EN_2 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2
+#define OEN_SDIO1_CDATA_OUT_EN_3 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3
+#define OEN_SDIO1_CDATA_OUT_EN_4 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4
+#define OEN_SDIO1_CDATA_OUT_EN_5 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5
+#define OEN_SDIO1_CDATA_OUT_EN_6 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6
+#define OEN_SDIO1_CDATA_OUT_EN_7 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7
+#define OEN_SPI0_NSSPCTLOE GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE
+#define OEN_SPI0_NSSPOE GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE
+#define OEN_SPI1_NSSPCTLOE GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE
+#define OEN_SPI1_NSSPOE GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE
+#define OEN_SPI2_NSSPCTLOE GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE
+#define OEN_SPI2_NSSPOE GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE
+#define OEN_SPI3_NSSPCTLOE GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE
+#define OEN_SPI3_NSSPOE GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE
+#define OEN_SPI4_NSSPCTLOE GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE
+#define OEN_SPI4_NSSPOE GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE
+#define OEN_SPI5_NSSPCTLOE GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE
+#define OEN_SPI5_NSSPOE GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE
+#define OEN_SPI6_NSSPCTLOE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE
+#define OEN_SPI6_NSSPOE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE
+#define OEN_TDM0_NPCM_SYNCOE GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE
+#define OEN_TDM0_NPCM_TXDOE GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE
+#define OEN_NONE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE + 1
//sys_iomux gpi din
#define GPI_CAN0_CTRL_RXD GPI_SYS_IOMUX_U0_CAN_CTRL_RXD
#define PADCFG_PAD_GMAC1_RXD2_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR
#define PADCFG_PAD_GMAC1_RXD3_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR
#define PADCFG_PAD_GMAC1_RXDV_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR
-#define PADCFG_PAD_GMAC1_RXC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR
+#define PADCFG_PAD_GMAC1_RXC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR
#define PADCFG_PAD_GMAC1_TXD0_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR
#define PADCFG_PAD_GMAC1_TXD1_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR
#define PADCFG_PAD_GMAC1_TXD2_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR
#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT 0x15U
#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK 0xE00000U
-#define PAD_GMAC1_RXC_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GMAC1_RXC_FUNC_SEL_SHIFT PAD_GMAC1_RXC_FUNC_SEL_MASK
-#define PAD_GPIO10_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO10_FUNC_SEL_SHIFT PAD_GPIO10_FUNC_SEL_MASK
-#define PAD_GPIO11_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO11_FUNC_SEL_SHIFT PAD_GPIO11_FUNC_SEL_MASK
-#define PAD_GPIO12_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO12_FUNC_SEL_SHIFT PAD_GPIO12_FUNC_SEL_MASK
-#define PAD_GPIO13_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO13_FUNC_SEL_SHIFT PAD_GPIO13_FUNC_SEL_MASK
-#define PAD_GPIO14_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO14_FUNC_SEL_SHIFT PAD_GPIO14_FUNC_SEL_MASK
-#define PAD_GPIO15_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO15_FUNC_SEL_SHIFT PAD_GPIO15_FUNC_SEL_MASK
-#define PAD_GPIO16_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO16_FUNC_SEL_SHIFT PAD_GPIO16_FUNC_SEL_MASK
-#define PAD_GPIO17_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO17_FUNC_SEL_SHIFT PAD_GPIO17_FUNC_SEL_MASK
-#define PAD_GPIO18_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO18_FUNC_SEL_SHIFT PAD_GPIO18_FUNC_SEL_MASK
-#define PAD_GPIO19_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO19_FUNC_SEL_SHIFT PAD_GPIO19_FUNC_SEL_MASK
-#define PAD_GPIO20_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO20_FUNC_SEL_SHIFT PAD_GPIO20_FUNC_SEL_MASK
-#define PAD_GPIO21_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO21_FUNC_SEL_SHIFT PAD_GPIO21_FUNC_SEL_MASK
-#define PAD_GPIO22_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO22_FUNC_SEL_SHIFT PAD_GPIO22_FUNC_SEL_MASK
-#define PAD_GPIO23_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO23_FUNC_SEL_SHIFT PAD_GPIO23_FUNC_SEL_MASK
-#define PAD_GPIO24_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO24_FUNC_SEL_SHIFT PAD_GPIO24_FUNC_SEL_MASK
-#define PAD_GPIO25_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO25_FUNC_SEL_SHIFT PAD_GPIO25_FUNC_SEL_MASK
-#define PAD_GPIO26_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO26_FUNC_SEL_SHIFT PAD_GPIO26_FUNC_SEL_MASK
-#define PAD_GPIO27_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO27_FUNC_SEL_SHIFT PAD_GPIO27_FUNC_SEL_MASK
-#define PAD_GPIO28_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO28_FUNC_SEL_SHIFT PAD_GPIO28_FUNC_SEL_MASK
-#define PAD_GPIO29_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO29_FUNC_SEL_SHIFT PAD_GPIO29_FUNC_SEL_MASK
-#define PAD_GPIO30_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO30_FUNC_SEL_SHIFT PAD_GPIO30_FUNC_SEL_MASK
-#define PAD_GPIO31_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO31_FUNC_SEL_SHIFT PAD_GPIO31_FUNC_SEL_MASK
-#define PAD_GPIO32_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO32_FUNC_SEL_SHIFT PAD_GPIO32_FUNC_SEL_MASK
-#define PAD_GPIO33_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO33_FUNC_SEL_SHIFT PAD_GPIO33_FUNC_SEL_MASK
-#define PAD_GPIO34_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO34_FUNC_SEL_SHIFT PAD_GPIO34_FUNC_SEL_MASK
-#define PAD_GPIO35_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO35_FUNC_SEL_SHIFT PAD_GPIO35_FUNC_SEL_MASK
-#define PAD_GPIO36_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO36_FUNC_SEL_SHIFT PAD_GPIO36_FUNC_SEL_MASK
-#define PAD_GPIO37_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO37_FUNC_SEL_SHIFT PAD_GPIO37_FUNC_SEL_MASK
-#define PAD_GPIO38_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO38_FUNC_SEL_SHIFT PAD_GPIO38_FUNC_SEL_MASK
-#define PAD_GPIO39_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO39_FUNC_SEL_SHIFT PAD_GPIO39_FUNC_SEL_MASK
-#define PAD_GPIO40_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO40_FUNC_SEL_SHIFT PAD_GPIO40_FUNC_SEL_MASK
-#define PAD_GPIO41_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO41_FUNC_SEL_SHIFT PAD_GPIO41_FUNC_SEL_MASK
-#define PAD_GPIO42_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO42_FUNC_SEL_SHIFT PAD_GPIO42_FUNC_SEL_MASK
-#define PAD_GPIO43_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO43_FUNC_SEL_SHIFT PAD_GPIO43_FUNC_SEL_MASK
-#define PAD_GPIO44_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO44_FUNC_SEL_SHIFT PAD_GPIO44_FUNC_SEL_MASK
-#define PAD_GPIO45_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO45_FUNC_SEL_SHIFT PAD_GPIO45_FUNC_SEL_MASK
-#define PAD_GPIO46_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO46_FUNC_SEL_SHIFT PAD_GPIO46_FUNC_SEL_MASK
-#define PAD_GPIO47_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO47_FUNC_SEL_SHIFT PAD_GPIO47_FUNC_SEL_MASK
-#define PAD_GPIO48_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO48_FUNC_SEL_SHIFT PAD_GPIO48_FUNC_SEL_MASK
-#define PAD_GPIO49_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO49_FUNC_SEL_SHIFT PAD_GPIO49_FUNC_SEL_MASK
-#define PAD_GPIO50_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO50_FUNC_SEL_SHIFT PAD_GPIO50_FUNC_SEL_MASK
-#define PAD_GPIO51_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO51_FUNC_SEL_SHIFT PAD_GPIO51_FUNC_SEL_MASK
-#define PAD_GPIO52_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO52_FUNC_SEL_SHIFT PAD_GPIO52_FUNC_SEL_MASK
-#define PAD_GPIO53_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO53_FUNC_SEL_SHIFT PAD_GPIO53_FUNC_SEL_MASK
-#define PAD_GPIO54_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO54_FUNC_SEL_SHIFT PAD_GPIO54_FUNC_SEL_MASK
-#define PAD_GPIO55_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO55_FUNC_SEL_SHIFT PAD_GPIO55_FUNC_SEL_MASK
-#define PAD_GPIO56_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO56_FUNC_SEL_SHIFT PAD_GPIO56_FUNC_SEL_MASK
-#define PAD_GPIO57_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO57_FUNC_SEL_SHIFT PAD_GPIO57_FUNC_SEL_MASK
-#define PAD_GPIO58_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO58_FUNC_SEL_SHIFT PAD_GPIO58_FUNC_SEL_MASK
-#define PAD_GPIO59_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO59_FUNC_SEL_SHIFT PAD_GPIO59_FUNC_SEL_MASK
-#define PAD_GPIO60_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO60_FUNC_SEL_SHIFT PAD_GPIO60_FUNC_SEL_MASK
-#define PAD_GPIO61_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO61_FUNC_SEL_SHIFT PAD_GPIO61_FUNC_SEL_MASK
-#define PAD_GPIO62_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO62_FUNC_SEL_SHIFT PAD_GPIO62_FUNC_SEL_MASK
-#define PAD_GPIO63_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO63_FUNC_SEL_SHIFT PAD_GPIO63_FUNC_SEL_MASK
-#define PAD_GPIO6_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO6_FUNC_SEL_SHIFT PAD_GPIO6_FUNC_SEL_MASK
-#define PAD_GPIO7_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO7_FUNC_SEL_SHIFT PAD_GPIO7_FUNC_SEL_MASK
-#define PAD_GPIO8_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO8_FUNC_SEL_SHIFT PAD_GPIO8_FUNC_SEL_MASK
+#define PAD_GMAC1_RXC_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GMAC1_RXC_FUNC_SEL_SHIFT PAD_GMAC1_RXC_FUNC_SEL_MASK
+#define PAD_GPIO10_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO10_FUNC_SEL_SHIFT PAD_GPIO10_FUNC_SEL_MASK
+#define PAD_GPIO11_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO11_FUNC_SEL_SHIFT PAD_GPIO11_FUNC_SEL_MASK
+#define PAD_GPIO12_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO12_FUNC_SEL_SHIFT PAD_GPIO12_FUNC_SEL_MASK
+#define PAD_GPIO13_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO13_FUNC_SEL_SHIFT PAD_GPIO13_FUNC_SEL_MASK
+#define PAD_GPIO14_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO14_FUNC_SEL_SHIFT PAD_GPIO14_FUNC_SEL_MASK
+#define PAD_GPIO15_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO15_FUNC_SEL_SHIFT PAD_GPIO15_FUNC_SEL_MASK
+#define PAD_GPIO16_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO16_FUNC_SEL_SHIFT PAD_GPIO16_FUNC_SEL_MASK
+#define PAD_GPIO17_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO17_FUNC_SEL_SHIFT PAD_GPIO17_FUNC_SEL_MASK
+#define PAD_GPIO18_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO18_FUNC_SEL_SHIFT PAD_GPIO18_FUNC_SEL_MASK
+#define PAD_GPIO19_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO19_FUNC_SEL_SHIFT PAD_GPIO19_FUNC_SEL_MASK
+#define PAD_GPIO20_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO20_FUNC_SEL_SHIFT PAD_GPIO20_FUNC_SEL_MASK
+#define PAD_GPIO21_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO21_FUNC_SEL_SHIFT PAD_GPIO21_FUNC_SEL_MASK
+#define PAD_GPIO22_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO22_FUNC_SEL_SHIFT PAD_GPIO22_FUNC_SEL_MASK
+#define PAD_GPIO23_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO23_FUNC_SEL_SHIFT PAD_GPIO23_FUNC_SEL_MASK
+#define PAD_GPIO24_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO24_FUNC_SEL_SHIFT PAD_GPIO24_FUNC_SEL_MASK
+#define PAD_GPIO25_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO25_FUNC_SEL_SHIFT PAD_GPIO25_FUNC_SEL_MASK
+#define PAD_GPIO26_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO26_FUNC_SEL_SHIFT PAD_GPIO26_FUNC_SEL_MASK
+#define PAD_GPIO27_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO27_FUNC_SEL_SHIFT PAD_GPIO27_FUNC_SEL_MASK
+#define PAD_GPIO28_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO28_FUNC_SEL_SHIFT PAD_GPIO28_FUNC_SEL_MASK
+#define PAD_GPIO29_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO29_FUNC_SEL_SHIFT PAD_GPIO29_FUNC_SEL_MASK
+#define PAD_GPIO30_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO30_FUNC_SEL_SHIFT PAD_GPIO30_FUNC_SEL_MASK
+#define PAD_GPIO31_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO31_FUNC_SEL_SHIFT PAD_GPIO31_FUNC_SEL_MASK
+#define PAD_GPIO32_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO32_FUNC_SEL_SHIFT PAD_GPIO32_FUNC_SEL_MASK
+#define PAD_GPIO33_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO33_FUNC_SEL_SHIFT PAD_GPIO33_FUNC_SEL_MASK
+#define PAD_GPIO34_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO34_FUNC_SEL_SHIFT PAD_GPIO34_FUNC_SEL_MASK
+#define PAD_GPIO35_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO35_FUNC_SEL_SHIFT PAD_GPIO35_FUNC_SEL_MASK
+#define PAD_GPIO36_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO36_FUNC_SEL_SHIFT PAD_GPIO36_FUNC_SEL_MASK
+#define PAD_GPIO37_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO37_FUNC_SEL_SHIFT PAD_GPIO37_FUNC_SEL_MASK
+#define PAD_GPIO38_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO38_FUNC_SEL_SHIFT PAD_GPIO38_FUNC_SEL_MASK
+#define PAD_GPIO39_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO39_FUNC_SEL_SHIFT PAD_GPIO39_FUNC_SEL_MASK
+#define PAD_GPIO40_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO40_FUNC_SEL_SHIFT PAD_GPIO40_FUNC_SEL_MASK
+#define PAD_GPIO41_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO41_FUNC_SEL_SHIFT PAD_GPIO41_FUNC_SEL_MASK
+#define PAD_GPIO42_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO42_FUNC_SEL_SHIFT PAD_GPIO42_FUNC_SEL_MASK
+#define PAD_GPIO43_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO43_FUNC_SEL_SHIFT PAD_GPIO43_FUNC_SEL_MASK
+#define PAD_GPIO44_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO44_FUNC_SEL_SHIFT PAD_GPIO44_FUNC_SEL_MASK
+#define PAD_GPIO45_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO45_FUNC_SEL_SHIFT PAD_GPIO45_FUNC_SEL_MASK
+#define PAD_GPIO46_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO46_FUNC_SEL_SHIFT PAD_GPIO46_FUNC_SEL_MASK
+#define PAD_GPIO47_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO47_FUNC_SEL_SHIFT PAD_GPIO47_FUNC_SEL_MASK
+#define PAD_GPIO48_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO48_FUNC_SEL_SHIFT PAD_GPIO48_FUNC_SEL_MASK
+#define PAD_GPIO49_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO49_FUNC_SEL_SHIFT PAD_GPIO49_FUNC_SEL_MASK
+#define PAD_GPIO50_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO50_FUNC_SEL_SHIFT PAD_GPIO50_FUNC_SEL_MASK
+#define PAD_GPIO51_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO51_FUNC_SEL_SHIFT PAD_GPIO51_FUNC_SEL_MASK
+#define PAD_GPIO52_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO52_FUNC_SEL_SHIFT PAD_GPIO52_FUNC_SEL_MASK
+#define PAD_GPIO53_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO53_FUNC_SEL_SHIFT PAD_GPIO53_FUNC_SEL_MASK
+#define PAD_GPIO54_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO54_FUNC_SEL_SHIFT PAD_GPIO54_FUNC_SEL_MASK
+#define PAD_GPIO55_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO55_FUNC_SEL_SHIFT PAD_GPIO55_FUNC_SEL_MASK
+#define PAD_GPIO56_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO56_FUNC_SEL_SHIFT PAD_GPIO56_FUNC_SEL_MASK
+#define PAD_GPIO57_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO57_FUNC_SEL_SHIFT PAD_GPIO57_FUNC_SEL_MASK
+#define PAD_GPIO58_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO58_FUNC_SEL_SHIFT PAD_GPIO58_FUNC_SEL_MASK
+#define PAD_GPIO59_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO59_FUNC_SEL_SHIFT PAD_GPIO59_FUNC_SEL_MASK
+#define PAD_GPIO60_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO60_FUNC_SEL_SHIFT PAD_GPIO60_FUNC_SEL_MASK
+#define PAD_GPIO61_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO61_FUNC_SEL_SHIFT PAD_GPIO61_FUNC_SEL_MASK
+#define PAD_GPIO62_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO62_FUNC_SEL_SHIFT PAD_GPIO62_FUNC_SEL_MASK
+#define PAD_GPIO63_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO63_FUNC_SEL_SHIFT PAD_GPIO63_FUNC_SEL_MASK
+#define PAD_GPIO6_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO6_FUNC_SEL_SHIFT PAD_GPIO6_FUNC_SEL_MASK
+#define PAD_GPIO7_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO7_FUNC_SEL_SHIFT PAD_GPIO7_FUNC_SEL_MASK
+#define PAD_GPIO8_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO8_FUNC_SEL_SHIFT PAD_GPIO8_FUNC_SEL_MASK
#define PAD_GPIO9_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO9_FUNC_SEL_SHIFT PAD_GPIO9_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK
-#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK
-#define U0_SYS_CRG_DVP_CLK_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK
/************************sys_iomux***************************/
//aon ioconfig
#define IO(config) ((config) & 0xFF)
#define DOUT(dout) ((dout) & 0xFF)
-#define DOEN(doen) ((doen) & 0xFF)
+#define DOEN(doen) ((doen) & 0xFF)
#define DIN(din_reg) ((din_reg) & 0xFF)
//syscon value
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