drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations

Use pixel_rate rather than crtc_clock in the watermark calculations.
These are actually identical on gmch platforms for now since
we don't adjust the pixel rate based on pfit downscaling. But
pixel_rate is the thing we are actually interested here so use
the proper name for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211209144311.3221-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 23d3342..29d4fe8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -905,15 +905,13 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
 
        crtc = single_enabled_crtc(dev_priv);
        if (crtc) {
-               const struct drm_display_mode *pipe_mode =
-                       &crtc->config->hw.pipe_mode;
                const struct drm_framebuffer *fb =
                        crtc->base.primary->state->fb;
+               int pixel_rate = crtc->config->pixel_rate;
                int cpp = fb->format->cpp[0];
-               int clock = pipe_mode->crtc_clock;
 
                /* Display SR */
-               wm = intel_calculate_wm(clock, &pnv_display_wm,
+               wm = intel_calculate_wm(pixel_rate, &pnv_display_wm,
                                        pnv_display_wm.fifo_size,
                                        cpp, latency->display_sr);
                reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
@@ -923,7 +921,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
                drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
 
                /* cursor SR */
-               wm = intel_calculate_wm(clock, &pnv_cursor_wm,
+               wm = intel_calculate_wm(pixel_rate, &pnv_cursor_wm,
                                        pnv_display_wm.fifo_size,
                                        4, latency->cursor_sr);
                reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -932,7 +930,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
                intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 
                /* Display HPLL off SR */
-               wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
+               wm = intel_calculate_wm(pixel_rate, &pnv_display_hplloff_wm,
                                        pnv_display_hplloff_wm.fifo_size,
                                        cpp, latency->display_hpll_disable);
                reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -941,7 +939,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
                intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 
                /* cursor HPLL off SR */
-               wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
+               wm = intel_calculate_wm(pixel_rate, &pnv_cursor_hplloff_wm,
                                        pnv_display_hplloff_wm.fifo_size,
                                        4, latency->cursor_hpll_disable);
                reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
@@ -1144,7 +1142,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
        const struct drm_display_mode *pipe_mode =
                &crtc_state->hw.pipe_mode;
        unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
-       unsigned int clock, htotal, cpp, width, wm;
+       unsigned int pixel_rate, htotal, cpp, width, wm;
 
        if (latency == 0)
                return USHRT_MAX;
@@ -1165,21 +1163,21 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
            level != G4X_WM_LEVEL_NORMAL)
                cpp = max(cpp, 4u);
 
-       clock = pipe_mode->crtc_clock;
+       pixel_rate = crtc_state->pixel_rate;
        htotal = pipe_mode->crtc_htotal;
 
        width = drm_rect_width(&plane_state->uapi.dst);
 
        if (plane->id == PLANE_CURSOR) {
-               wm = intel_wm_method2(clock, htotal, width, cpp, latency);
+               wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
        } else if (plane->id == PLANE_PRIMARY &&
                   level == G4X_WM_LEVEL_NORMAL) {
-               wm = intel_wm_method1(clock, cpp, latency);
+               wm = intel_wm_method1(pixel_rate, cpp, latency);
        } else {
                unsigned int small, large;
 
-               small = intel_wm_method1(clock, cpp, latency);
-               large = intel_wm_method2(clock, htotal, width, cpp, latency);
+               small = intel_wm_method1(pixel_rate, cpp, latency);
+               large = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
 
                wm = min(small, large);
        }
@@ -1664,7 +1662,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        const struct drm_display_mode *pipe_mode =
                &crtc_state->hw.pipe_mode;
-       unsigned int clock, htotal, cpp, width, wm;
+       unsigned int pixel_rate, htotal, cpp, width, wm;
 
        if (dev_priv->wm.pri_latency[level] == 0)
                return USHRT_MAX;
@@ -1673,7 +1671,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
                return 0;
 
        cpp = plane_state->hw.fb->format->cpp[0];
-       clock = pipe_mode->crtc_clock;
+       pixel_rate = crtc_state->pixel_rate;
        htotal = pipe_mode->crtc_htotal;
        width = crtc_state->pipe_src_w;
 
@@ -1686,7 +1684,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
                 */
                wm = 63;
        } else {
-               wm = vlv_wm_method2(clock, htotal, width, cpp,
+               wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
                                    dev_priv->wm.pri_latency[level] * 10);
        }
 
@@ -2267,13 +2265,13 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
                        &crtc->config->hw.pipe_mode;
                const struct drm_framebuffer *fb =
                        crtc->base.primary->state->fb;
-               int clock = pipe_mode->crtc_clock;
+               int pixel_rate = crtc->config->pixel_rate;
                int htotal = pipe_mode->crtc_htotal;
                int hdisplay = crtc->config->pipe_src_w;
                int cpp = fb->format->cpp[0];
                int entries;
 
-               entries = intel_wm_method2(clock, htotal,
+               entries = intel_wm_method2(pixel_rate, htotal,
                                           hdisplay, cpp, sr_latency_ns / 100);
                entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
                srwm = I965_FIFO_SIZE - entries;
@@ -2284,7 +2282,7 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
                            "self-refresh entries: %d, wm: %d\n",
                            entries, srwm);
 
-               entries = intel_wm_method2(clock, htotal,
+               entries = intel_wm_method2(pixel_rate, htotal,
                                           crtc->base.cursor->state->crtc_w, 4,
                                           sr_latency_ns / 100);
                entries = DIV_ROUND_UP(entries,
@@ -2363,8 +2361,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
                fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
        crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
        if (intel_crtc_active(crtc)) {
-               const struct drm_display_mode *pipe_mode =
-                       &crtc->config->hw.pipe_mode;
                const struct drm_framebuffer *fb =
                        crtc->base.primary->state->fb;
                int cpp;
@@ -2374,7 +2370,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
                else
                        cpp = fb->format->cpp[0];
 
-               planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+               planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
                                               wm_info, fifo_size, cpp,
                                               pessimal_latency_ns);
                enabled = crtc;
@@ -2393,8 +2389,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
                fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
        crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
        if (intel_crtc_active(crtc)) {
-               const struct drm_display_mode *pipe_mode =
-                       &crtc->config->hw.pipe_mode;
                const struct drm_framebuffer *fb =
                        crtc->base.primary->state->fb;
                int cpp;
@@ -2404,7 +2398,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
                else
                        cpp = fb->format->cpp[0];
 
-               planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+               planeb_wm = intel_calculate_wm(crtc->config->pixel_rate,
                                               wm_info, fifo_size, cpp,
                                               pessimal_latency_ns);
                if (enabled == NULL)
@@ -2446,7 +2440,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
                        &enabled->config->hw.pipe_mode;
                const struct drm_framebuffer *fb =
                        enabled->base.primary->state->fb;
-               int clock = pipe_mode->crtc_clock;
+               int pixel_rate = enabled->config->pixel_rate;
                int htotal = pipe_mode->crtc_htotal;
                int hdisplay = enabled->config->pipe_src_w;
                int cpp;
@@ -2457,7 +2451,7 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
                else
                        cpp = fb->format->cpp[0];
 
-               entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
+               entries = intel_wm_method2(pixel_rate, htotal, hdisplay, cpp,
                                           sr_latency_ns / 100);
                entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
                drm_dbg_kms(&dev_priv->drm,
@@ -2494,7 +2488,6 @@ static void i9xx_update_wm(struct drm_i915_private *dev_priv)
 static void i845_update_wm(struct drm_i915_private *dev_priv)
 {
        struct intel_crtc *crtc;
-       const struct drm_display_mode *pipe_mode;
        u32 fwater_lo;
        int planea_wm;
 
@@ -2502,8 +2495,7 @@ static void i845_update_wm(struct drm_i915_private *dev_priv)
        if (crtc == NULL)
                return;
 
-       pipe_mode = &crtc->config->hw.pipe_mode;
-       planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
+       planea_wm = intel_calculate_wm(crtc->config->pixel_rate,
                                       &i845_wm_info,
                                       i845_get_fifo_size(dev_priv, PLANE_A),
                                       4, pessimal_latency_ns);