* For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
* For single lane PHYs: pcs_misc (optional) -> 3.
*/
- qphy->tx = of_iomap(np, 0);
- if (!qphy->tx)
- return -ENOMEM;
+ qphy->tx = devm_of_iomap(dev, np, 0, NULL);
+ if (IS_ERR(qphy->tx))
+ return PTR_ERR(qphy->tx);
- qphy->rx = of_iomap(np, 1);
- if (!qphy->rx)
- return -ENOMEM;
+ qphy->rx = devm_of_iomap(dev, np, 1, NULL);
+ if (IS_ERR(qphy->rx))
+ return PTR_ERR(qphy->rx);
- qphy->pcs = of_iomap(np, 2);
- if (!qphy->pcs)
- return -ENOMEM;
+ qphy->pcs = devm_of_iomap(dev, np, 2, NULL);
+ if (IS_ERR(qphy->pcs))
+ return PTR_ERR(qphy->pcs);
/*
* If this is a dual-lane PHY, then there should be registers for the
* offset from the first lane.
*/
if (cfg->is_dual_lane_phy) {
- qphy->tx2 = of_iomap(np, 3);
- qphy->rx2 = of_iomap(np, 4);
- if (!qphy->tx2 || !qphy->rx2) {
+ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
+ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL);
+ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) {
dev_warn(dev,
"Underspecified device tree, falling back to legacy register regions\n");
qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
} else {
- qphy->pcs_misc = of_iomap(np, 5);
+ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
}
} else {
- qphy->pcs_misc = of_iomap(np, 3);
+ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
}
- if (!qphy->pcs_misc &&
+ if (IS_ERR(qphy->pcs_misc) &&
of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
qphy->pcs_misc = qphy->pcs + 0x400;
- if (!qphy->pcs_misc) {
+ if (IS_ERR(qphy->pcs_misc)) {
if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec)
- return -EINVAL;
+ return PTR_ERR(qphy->pcs_misc);
}
qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);