MBB->end());
NewSuccessor->transferSuccessorsAndUpdatePHIs(MBB);
- // Copy the original liveIns of MBB to NewSuccessor.
- for (auto &LI : MBB->liveins())
- NewSuccessor->addLiveIn(LI);
-
- // After splitting the NewSuccessor block, Regs defined but not killed
- // in MBB should be treated as liveins of NewSuccessor.
- // Note: Cannot use stepBackward instead since we are using the Reg
- // liveness state at the end of MBB (liveOut of MBB) as the liveIn for
- // NewSuccessor. Otherwise, will cause cyclic dependence.
- LivePhysRegs LPR(*MF->getSubtarget<PPCSubtarget>().getRegisterInfo());
- SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 2> Clobbers;
- for (MachineInstr &MI : *MBB)
- LPR.stepForward(MI, Clobbers);
- for (auto &LI : LPR)
- NewSuccessor->addLiveIn(LI);
+ // Update the liveins for NewSuccessor.
+ LivePhysRegs LPR;
+ computeAndAddLiveIns(LPR, *NewSuccessor);
+
} else {
// Remove successor from MBB.
MBB->removeSuccessor(Successor);
bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
- if (IsADDIInstRequired) {
- // Copy the result into the destination if the condition is true.
+ // Copy the result into the destination if the condition is true.
+ if (IsADDIInstRequired)
BuildMI(*TrueBlock, TrueBlockI, dl,
TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI))
.add(Dest)
.add(TrueValue)
.add(MachineOperand::CreateImm(0));
- // Add the LiveIn registers required by true block.
- TrueBlock->addLiveIn(TrueValue.getReg());
- }
-
- if (IsORIInstRequired) {
- // Add the LiveIn registers required by false block.
- FalseBlock->addLiveIn(FalseValue.getReg());
- }
-
- if (NewSuccessor) {
- // Add the LiveIn registers required by NewSuccessor block.
- NewSuccessor->addLiveIn(Dest.getReg());
- NewSuccessor->addLiveIn(TrueValue.getReg());
- NewSuccessor->addLiveIn(FalseValue.getReg());
- NewSuccessor->addLiveIn(ConditionRegister.getReg());
- }
-
- // Copy the value into the destination if the condition is false.
+ // Copy the result into the destination if the condition is false.
if (IsORIInstRequired)
BuildMI(*FalseBlock, FalseBlockI, dl,
TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI))
NumExpanded++;
}
+
+ if (IsTrueBlockRequired) {
+ // Update the liveins for TrueBlock.
+ LivePhysRegs LPR;
+ computeAndAddLiveIns(LPR, *TrueBlock);
+ }
+
+ if (IsFalseBlockRequired) {
+ // Update the liveins for FalseBlock.
+ LivePhysRegs LPR;
+ computeAndAddLiveIns(LPR, *FalseBlock);
+ }
}
void PPCExpandISEL::expandMergeableISELs(BlockISELList &BIL) {
; CHECK-LABEL: name: expand_isel_liveness1
; CHECK: bb.1:
- ; CHECK: liveins: $x7
+ ; CHECK: liveins: $x3, $x4, $x7
; CHECK: renamable $x5 = ORI8 killed renamable $x7, 0
; CHECK: B %bb.3
; CHECK: bb.2:
- ; CHECK: liveins: $zero8
+ ; CHECK: liveins: $x3, $x4
; CHECK: renamable $x5 = ADDI8 $zero8, 0
; CHECK: bb.3:
- ; CHECK: liveins: $x3, $x4, $x5, $x6, $cr1lt, $cr1gt, $x3, $cr6lt, $cr0eq, $r3, $cr5un, $cr1eq, $cr1un, $cr6un, $cr0lt, $cr0gt, $cr6gt, $cr0un, $cr1, $cr6, $cr5eq, $x8, $r8, $cr6eq, $x4, $r4, $cr0, $cr5gt, $cr5, $cr5lt, $x7, $r7, $x5, $r5, $x5, $zero8, $x7, $cr5lt
+ ; CHECK: liveins: $x3, $x4, $x5
; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5
...
; CHECK: $r3 = ORI killed $r0, 0
; CHECK: B %bb.3
; CHECK: bb.2.entry:
- ; CHECK: liveins: $zero
+ ; CHECK-NOT: liveins: $zero
; CHECK: $r3 = ADDI $zero, 0
...