static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
{
unsigned int div;
+ int addr_config;
unsigned long freq, sclk;
struct dwmci_exynos_priv_data *priv = host->priv;
host->clksel = exynos_dwmci_clksel;
host->dev_index = index;
host->get_mmc_clk = exynos_dwmci_get_clk;
+
+ addr_config = DWMCI_GET_ADDR_CONFIG(dwmci_readl(host, DWMCI_HCON));
+ if (addr_config == 1)
+ /* host supports IDMAC in 64-bit address mode */
+ host->dma_64bit_address = 1;
+
/* Add the mmc channel to be registered with mmc core */
if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
printf("DWMMC%d registration failed\n", index);
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
+#define DWMCI_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
/**
* struct dwmci_host - Information about a designware MMC host
*
* @dev_id: Arbitrary device ID for use by controller
* @buswidth: Bus width in bits (8 or 4)
* @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
+ * @dma_64bit_address: True only for devices supporting 64 bit DMA
* @mmc: Pointer to generic MMC structure for this device
* @priv: Private pointer for use by controller
*/
int dev_id;
int buswidth;
u32 fifoth_val;
+ int dma_64bit_address;
struct mmc *mmc;
void *priv;