drm/amd/display: Fix primary EDP link detection

[HOW&WHY]
EDP link detection must
be updated to support a primary EDP with a
link index of greater than 0.

* SWDEV-342936 - dc: DSC bringup for SAG 1.5

[WHY]
SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5)
requires seamless switching between GPUs
with DSC enabled.

[HOW]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic to ensure the CRC checker provides valid
values for non-black frames
allowing the system to come out of forced PSR on
d2i.

Added additional logic to both generate a black
frame through setVisibility calls and keep track
of the CRCs values for this black frame when
coming out of forced PSR.

Updating logic for DalRegKey_DisableDSC to disable
DSC on EDP and all ports for systems.

[CLEANED]
dc: Moved DSC programming to before stream enablement

[HOW&WHY]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic.

Co-authored-by: sregolui <sregolui@amd.com>
Reviewed-by: Jayendran Ramani <Jayendran.Ramani@amd.com>
Reviewed-by: Harry Vanzylldejong <Harry.Vanzylldejong@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: sregolui <sregolui@amd.com>
Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 74db87f..38fa63d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4303,18 +4303,6 @@ void core_link_enable_stream(
                if (pipe_ctx->stream->dpms_off)
                        return;
 
-               /* Have to setup DSC before DIG FE and BE are connected (which happens before the
-                * link training). This is to make sure the bandwidth sent to DIG BE won't be
-                * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
-                * will be automatically set at a later time when the video is enabled
-                * (DP_VID_STREAM_EN = 1).
-                */
-               if (pipe_ctx->stream->timing.flags.DSC) {
-                       if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
-                                       dc_is_virtual_signal(pipe_ctx->stream->signal))
-                               dp_set_dsc_enable(pipe_ctx, true);
-               }
-
                status = enable_link(state, pipe_ctx);
 
                if (status != DC_OK) {

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 801206a..fe346e9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1577,6 +1577,19 @@ static enum dc_status apply_single_controller_ctx_to_hw(
        if (dc_is_dp_signal(pipe_ctx->stream->signal))
                dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
 
+       /* Have to setup DSC before DIG FE and BE are connected (which happens before the
+        * link training). This is to make sure the bandwidth sent to DIG BE won't be
+        * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
+        * will be automatically set at a later time when the video is enabled
+        * (DP_VID_STREAM_EN = 1).
+        */
+       if (pipe_ctx->stream->timing.flags.DSC) {
+               if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+                       dc_is_virtual_signal(pipe_ctx->stream->signal))
+                       dp_set_dsc_enable(pipe_ctx, true);
+
+       }
+
        if (!stream->dpms_off) {
                if (dc->hwss.update_phy_state)
                        dc->hwss.update_phy_state(context, pipe_ctx, TX_ON_SYMCLK_ON);