spi: soc: qcom: GENI SE SPI controller device tree binding

Move GENI SE SPI controller device-tree bindings
from devicetree/bindings/soc/qcom/qcom,geni-se.txt
to devicetree/bindings/spi/qcom,spi-geni-qcom.txt.

Signed-off-by: Dilip Kota <dkota@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
index b9d0c21..dab7ca9 100644 (file)
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -53,19 +53,8 @@ Required properties:
 - clocks:              Serial engine core clock needed by the device.
 
 Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
-
-Required properties:
-- compatible:          Must contain "qcom,geni-spi".
-- reg:                 Must contain SPI register location and length.
-- interrupts:          Must contain SPI controller interrupts.
-- clock-names:         Must contain "se".
-- clocks:              Serial engine core clock needed by the device.
-- #address-cells:      Must be <1> to define a chip select address on
-                       the SPI bus.
-- #size-cells:         Must be <0>.
-
-SPI slave nodes must be children of the SPI master node and conform to SPI bus
-binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+node binding is described in
+Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt.
 
 Example:
        geniqup@8c0000 {
@@ -102,16 +91,4 @@ Example:
                        pinctrl-1 = <&qup_1_uart_3_sleep>;
                };
 
-               spi0: spi@a84000 {
-                       compatible = "qcom,geni-spi";
-                       reg = <0xa84000 0x4000>;
-                       interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "se";
-                       clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
-                       pinctrl-names = "default", "sleep";
-                       pinctrl-0 = <&qup_1_spi_2_active>;
-                       pinctrl-1 = <&qup_1_spi_2_sleep>;
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-               };
        }

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
new file mode 100644 (file)
index 0000000..790311a
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
@@ -0,0 +1,39 @@
+GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
+
+The QUP v3 core is a GENI based AHB slave that provides a common data path
+(an output FIFO and an input FIFO) for serial peripheral interface (SPI)
+mini-core.
+
+SPI in master mode supports up to 50MHz, up to four chip selects, programmable
+data path from 4 bits to 32 bits and numerous protocol variants.
+
+Required properties:
+- compatible:          Must contain "qcom,geni-spi".
+- reg:                 Must contain SPI register location and length.
+- interrupts:          Must contain SPI controller interrupts.
+- clock-names:         Must contain "se".
+- clocks:              Serial engine core clock needed by the device.
+- #address-cells:      Must be <1> to define a chip select address on
+                       the SPI bus.
+- #size-cells:         Must be <0>.
+
+SPI Controller nodes must be child of GENI based Qualcomm Universal
+Peripharal. Please refer GENI based QUP wrapper controller node bindings
+described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt.
+
+SPI slave nodes must be children of the SPI master node and conform to SPI bus
+binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+
+Example:
+       spi0: spi@a84000 {
+               compatible = "qcom,geni-spi";
+               reg = <0xa84000 0x4000>;
+               interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+               clock-names = "se";
+               clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
+               pinctrl-names = "default", "sleep";
+               pinctrl-0 = <&qup_1_spi_2_active>;
+               pinctrl-1 = <&qup_1_spi_2_sleep>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };