drm/i915/xehp: CCS shares the render reset domain

The reset domain is shared between render and all compute engines,
so resetting one will affect the others.

Note:  Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impacting other clients (since some shared modules will be reset).  If
other engines are executing non-preemptable workloads, the impact is
unavoidable and some work may be lost.

Bspec: 52549
Original-author: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-3-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3190b7b..3150c08 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -341,6 +341,10 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
                        [VECS1] = GEN11_GRDOM_VECS2,
                        [VECS2] = GEN11_GRDOM_VECS3,
                        [VECS3] = GEN11_GRDOM_VECS4,
+                       [CCS0]  = GEN11_GRDOM_RENDER,
+                       [CCS1]  = GEN11_GRDOM_RENDER,
+                       [CCS2]  = GEN11_GRDOM_RENDER,
+                       [CCS3]  = GEN11_GRDOM_RENDER,
                };
                GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
                           !engine_reset_domains[id]);