ARM: tegra: Sort Tegra124 XUSB clocks correctly

Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 36566a7..e87da6c 100644 (file)
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -710,8 +710,8 @@
                         <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
                         <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
                         <&tegra_car TEGRA124_CLK_XUSB_SS>,
-                        <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
                         <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
+                        <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
                         <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
                         <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
                         <&tegra_car TEGRA124_CLK_PLL_U_480M>,
@@ -719,7 +719,7 @@
                         <&tegra_car TEGRA124_CLK_PLL_E>;
                clock-names = "xusb_host", "xusb_host_src",
                              "xusb_falcon_src", "xusb_ss",
-                             "xusb_ss_src", "xusb_ss_div2",
+                             "xusb_ss_div2", "xusb_ss_src",
                              "xusb_hs_src", "xusb_fs_src",
                              "pll_u_480m", "clk_m", "pll_e";
                resets = <&tegra_car 89>, <&tegra_car 156>,