arm64: dts: renesas: r9a07g054: Add OPP table

Add OPP table for RZ/V2L SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220308223324.7456-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index e4f1def..bdf0a10 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -42,6 +42,33 @@
                clock-frequency = <0>;
        };
 
+       cluster0_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-150000000 {
+                       opp-hz = /bits/ 64 <150000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <300000>;
+                       opp-suspend;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -65,6 +92,7 @@
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu1: cpu@100 {
@@ -74,6 +102,7 @@
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                L3_CA55: cache-controller-0 {