re PR target/78904 (zero-extracts are not effective)

	PR target/78904
	* config/i386/constraints.md (Bc): New special memory constraint.
	* config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use Bc
	constraint with nonimmediate_operand to allow constant memory operands.
	(*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
	(*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use Bc constraint
	with general_operand to allow constant memory operands.

testsuite/ChangeLog:

	PR target/78904
	* gcc.target/i386/pr78904-3.c: New test.

From-SVN: r243937

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 25a3edb..9900452 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/78904
+       * config/i386/constraints.md (Bc): New special memory constraint.
+       * config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use Bc
+       constraint with nonimmediate_operand to allow constant memory operands.
+       (*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
+       (*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use Bc constraint
+       with general_operand to allow constant memory operands.
+
 2016-12-27  Alexander Ivchenko  <alexander.ivchenko@intel.com>
 
        * c-family/c.opt (flag_chkp_flexible_struct_trailing_arrays):

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index b734ce4..6aa2e4f 100644 (file)
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -168,6 +168,7 @@
 ;;  f  FLAGS_REG
 ;;  g  GOT memory operand.
 ;;  m  Vector memory operand
+;;  c  Constant memory operand
 ;;  s  Sibcall memory operand, not valid for TARGET_X32
 ;;  w  Call memory operand, not valid for TARGET_X32
 ;;  z  Constant call address operand.
@@ -185,6 +186,11 @@
   "@internal Vector memory operand."
   (match_operand 0 "vector_memory_operand"))
 
+(define_special_memory_constraint "Bc"
+  "@internal Constant memory operand."
+  (and (match_operand 0 "memory_operand")
+       (match_test "constant_address_p (XEXP (op, 0))")))
+
 (define_constraint "Bs"
   "@internal Sibcall memory operand."
   (ior (and (not (match_test "TARGET_X32"))

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 706e1c4..13769f9 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1295,7 +1295,7 @@
 (define_insn "*cmpqi_ext_1"
   [(set (reg FLAGS_REG)
        (compare
-         (match_operand:QI 0 "nonimmediate_operand" "Q,m")
+         (match_operand:QI 0 "nonimmediate_operand" "QBc,m")
          (subreg:QI
            (zero_extract:SI
              (match_operand 1 "ext_register_operand" "Q,Q")
@@ -1340,7 +1340,7 @@
              (match_operand 0 "ext_register_operand" "Q,Q")
              (const_int 8)
              (const_int 8)) 0)
-         (match_operand:QI 1 "general_operand" "Qn,m")))]
+         (match_operand:QI 1 "general_operand" "QnBc,m")))]
   "ix86_match_ccmode (insn, CCmode)"
   "cmp{b}\t{%1, %h0|%h0, %1}"
   [(set_attr "isa" "*,nox64")
@@ -2781,7 +2781,7 @@
    (set_attr "mode" "SI")])
 
 (define_insn "*extvqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
         (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q,Q")
                          (const_int 8)
                          (const_int 8)))]
@@ -2836,7 +2836,7 @@
    (set_attr "mode" "SI")])
 
 (define_insn "*extzvqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
         (subreg:QI
          (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q")
                           (const_int 8)
@@ -2897,7 +2897,7 @@
   [(set (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "+Q,Q")
                             (const_int 8)
                             (const_int 8))
-       (match_operand:SWI248 1 "general_operand" "Qn,m"))]
+       (match_operand:SWI248 1 "general_operand" "QnBc,m"))]
   ""
 {
   if (CONST_INT_P (operands[1]))
@@ -6087,7 +6087,7 @@
              (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
                               (const_int 8)
                               (const_int 8)) 0)
-           (match_operand:QI 2 "general_operand" "Qn,m")) 0))
+           (match_operand:QI 2 "general_operand" "QnBc,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   ""
 {
@@ -7889,7 +7889,7 @@
              (zero_extract:SI (match_operand 0 "ext_register_operand" "Q,Q")
                               (const_int 8)
                               (const_int 8)) 0)
-           (match_operand:QI 1 "general_operand" "Qn,m"))
+           (match_operand:QI 1 "general_operand" "QnBc,m"))
          (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\t{%1, %h0|%h0, %1}"
@@ -8417,7 +8417,7 @@
              (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
                               (const_int 8)
                               (const_int 8)) 0)
-           (match_operand:QI 2 "general_operand" "Qn,m")) 0))
+           (match_operand:QI 2 "general_operand" "QnBc,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   ""
   "and{b}\t{%2, %h0|%h0, %2}"
@@ -8435,7 +8435,7 @@
              (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
                               (const_int 8)
                               (const_int 8)) 0)
-           (match_operand:QI 2 "general_operand" "Qn,m"))
+           (match_operand:QI 2 "general_operand" "QnBc,m"))
          (const_int 0)))
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q")
                         (const_int 8)
@@ -8804,7 +8804,7 @@
              (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
                               (const_int 8)
                               (const_int 8)) 0)
-           (match_operand:QI 2 "general_operand" "Qn,m")) 0))
+           (match_operand:QI 2 "general_operand" "QnBc,m")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
   "<logic>{b}\t{%2, %h0|%h0, %2}"
@@ -8914,7 +8914,7 @@
              (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
                               (const_int 8)
                               (const_int 8)) 0)
-           (match_operand:QI 2 "general_operand" "Qn,m"))
+           (match_operand:QI 2 "general_operand" "QnBc,m"))
          (const_int 0)))
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q")
                         (const_int 8)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d8eecd4..6fb5b25 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-12-27  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/78904
+       * gcc.target/i386/pr78904-3.c: New test.
+
 2016-12-27  Alexander Ivchenko  <alexander.ivchenko@intel.com>
 
        * gcc.target/i386/mpx/vla-trailing-1-lbv.c: New test.

diff --git a/gcc/testsuite/gcc.target/i386/pr78904-3.c b/gcc/testsuite/gcc.target/i386/pr78904-3.c
new file mode 100644 (file)
index 0000000..2827b38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-3.c
@@ -0,0 +1,42 @@
+/* PR target/78904 */
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+typedef __SIZE_TYPE__ size_t;
+
+struct S1
+{
+  unsigned char pad1;
+  unsigned char val;
+  unsigned short pad2;
+};
+
+extern struct S1 t[256];
+
+struct S1 test_and (struct S1 a, size_t i)
+{
+  a.val &= t[i].val;
+
+  return a;
+}
+
+struct S1 test_or (struct S1 a, size_t i)
+{
+  a.val |= t[i].val;
+
+  return a;
+}
+
+struct S1 test_xor (struct S1 a, size_t i)
+{
+  a.val ^= t[i].val;
+
+  return a;
+}
+
+struct S1 test_add (struct S1 a, size_t i)
+{
+  a.val += t[i].val;
+
+  return a;
+}