arm64: Add TRFCR_ELx definitions

Add definitions for the Arm v8.4 SelfHosted trace extensions registers.

[ split the register definitions to separate patch
  rename some of the symbols ]

Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-30-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8b5e7e5..4acff97 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -191,6 +191,7 @@
 #define SYS_GCR_EL1                    sys_reg(3, 0, 1, 0, 6)
 
 #define SYS_ZCR_EL1                    sys_reg(3, 0, 1, 2, 0)
+#define SYS_TRFCR_EL1                  sys_reg(3, 0, 1, 2, 1)
 
 #define SYS_TTBR0_EL1                  sys_reg(3, 0, 2, 0, 0)
 #define SYS_TTBR1_EL1                  sys_reg(3, 0, 2, 0, 1)
@@ -471,6 +472,7 @@
 
 #define SYS_SCTLR_EL2                  sys_reg(3, 4, 1, 0, 0)
 #define SYS_ZCR_EL2                    sys_reg(3, 4, 1, 2, 0)
+#define SYS_TRFCR_EL2                  sys_reg(3, 4, 1, 2, 1)
 #define SYS_DACR32_EL2                 sys_reg(3, 4, 3, 0, 0)
 #define SYS_SPSR_EL2                   sys_reg(3, 4, 4, 0, 0)
 #define SYS_ELR_EL2                    sys_reg(3, 4, 4, 0, 1)
@@ -829,6 +831,7 @@
 #define ID_AA64MMFR2_CNP_SHIFT         0
 
 /* id_aa64dfr0 */
+#define ID_AA64DFR0_TRACE_FILT_SHIFT   40
 #define ID_AA64DFR0_DOUBLELOCK_SHIFT   36
 #define ID_AA64DFR0_PMSVER_SHIFT       32
 #define ID_AA64DFR0_CTX_CMPS_SHIFT     28
@@ -1003,6 +1006,14 @@
 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
 #define SYS_MPIDR_SAFE_VAL     (BIT(31))
 
+#define TRFCR_ELx_TS_SHIFT             5
+#define TRFCR_ELx_TS_VIRTUAL           ((0x1UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_GUEST_PHYSICAL    ((0x2UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_PHYSICAL          ((0x3UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_EL2_CX                   BIT(3)
+#define TRFCR_ELx_ExTRE                        BIT(1)
+#define TRFCR_ELx_E0TRE                        BIT(0)
+
 #ifdef __ASSEMBLY__
 
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