net/mlx5: Make get_cqe routine not ethernet-specific
authorIlan Tayari <ilant@mellanox.com>
Mon, 19 Jun 2017 09:53:25 +0000 (12:53 +0300)
committerSaeed Mahameed <saeedm@mellanox.com>
Tue, 27 Jun 2017 13:36:47 +0000 (16:36 +0300)
Move mlx5e_get_cqe routine to wq.h and rename it to
mlx5_cqwq_get_cqe.

This allows it to be used by other CQ users outside of the
ethernet driver code.

A later patch in this patchset will make use of it from
FPGA code for the FPGA high-speed connection.

Signed-off-by: Ilan Tayari <ilant@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/en.h
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
drivers/net/ethernet/mellanox/mlx5/core/wq.h

index eef0a50e2388e812f4d760378a53660bb6c76a94..f93f44d1d1cfd835b6169c3d537ef0dea8e24e16 100644 (file)
@@ -833,7 +833,6 @@ void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
-struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 
 void mlx5e_rx_am(struct mlx5e_rq *rq);
 void mlx5e_rx_am_work(struct work_struct *work);
index 5f3c138c948d3b7bfefa7867786096a74de36743..574a96279340da2de57470ce635ab58b833a5650 100644 (file)
@@ -996,7 +996,7 @@ int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
                work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
 
        for (; work_done < budget; work_done++) {
-               struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
+               struct mlx5_cqe64 *cqe = mlx5_cqwq_get_cqe(&cq->wq);
 
                if (!cqe)
                        break;
@@ -1050,7 +1050,7 @@ bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
                u16 wqe_counter;
                bool last_wqe;
 
-               cqe = mlx5e_get_cqe(cq);
+               cqe = mlx5_cqwq_get_cqe(&cq->wq);
                if (!cqe)
                        break;
 
index 0433d69429f3d4fb4e1e3265875bb73666398ba7..ccec3b00e17c70383475126c1a115fa98b4d8a5f 100644 (file)
@@ -409,7 +409,7 @@ bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
                u16 wqe_counter;
                bool last_wqe;
 
-               cqe = mlx5e_get_cqe(cq);
+               cqe = mlx5_cqwq_get_cqe(&cq->wq);
                if (!cqe)
                        break;
 
index 5ca6714e3e02bd976515de96fa010d348b349458..92db28a9ed43a89edcaf92c8d43db4d71ad68976 100644 (file)
 
 #include "en.h"
 
-struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq)
-{
-       struct mlx5_cqwq *wq = &cq->wq;
-       u32 ci = mlx5_cqwq_get_ci(wq);
-       struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
-       u8 cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK;
-       u8 sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1;
-
-       if (cqe_ownership_bit != sw_ownership_val)
-               return NULL;
-
-       /* ensure cqe content is read after cqe ownership bit */
-       dma_rmb();
-
-       return cqe;
-}
-
 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
                                             struct mlx5e_icosq *sq,
                                             struct mlx5_cqe64 *cqe,
@@ -89,7 +72,7 @@ static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
        if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
                return;
 
-       cqe = mlx5e_get_cqe(cq);
+       cqe = mlx5_cqwq_get_cqe(&cq->wq);
        if (likely(!cqe))
                return;
 
index d8afed898c31d3719d6d44d3d46649e52e9baa10..9ded5d40ce6bf47a7c8d6ab3530e7edd81d2d1b7 100644 (file)
@@ -34,6 +34,7 @@
 #define __MLX5_WQ_H__
 
 #include <linux/mlx5/mlx5_ifc.h>
+#include <linux/mlx5/cq.h>
 
 struct mlx5_wq_param {
        int             linear;
@@ -146,6 +147,22 @@ static inline void mlx5_cqwq_update_db_record(struct mlx5_cqwq *wq)
        *wq->db = cpu_to_be32(wq->cc & 0xffffff);
 }
 
+static inline struct mlx5_cqe64 *mlx5_cqwq_get_cqe(struct mlx5_cqwq *wq)
+{
+       u32 ci = mlx5_cqwq_get_ci(wq);
+       struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
+       u8 cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK;
+       u8 sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1;
+
+       if (cqe_ownership_bit != sw_ownership_val)
+               return NULL;
+
+       /* ensure cqe content is read after cqe ownership bit */
+       dma_rmb();
+
+       return cqe;
+}
+
 static inline int mlx5_wq_ll_is_full(struct mlx5_wq_ll *wq)
 {
        return wq->cur_sz == wq->sz_m1;