BR 1828866: fix handling of LAR/LSL

Fix handling of LAR/LSL with various sized operands

diff --git a/insns.dat b/insns.dat
index c297fbf..f54d6cc 100644 (file)
--- a/insns.dat
+++ b/insns.dat
@@ -618,10 +618,16 @@ JRCXZ             imm                     \1\xE3\50                       X64
 LAHF           void                    \1\x9F                          8086
 LAR            reg16,mem               \320\2\x0F\x02\110              286,PROT,SW
 LAR            reg16,reg16             \320\2\x0F\x02\110              286,PROT
+LAR            reg16,reg32             \320\2\x0F\x02\110              386,PROT
+LAR            reg16,reg64             \320\323\2\x0F\x02\110          X64,PROT,ND
 LAR            reg32,mem               \321\2\x0F\x02\110              386,PROT,SW
 LAR            reg32,reg16             \321\2\x0F\x02\110              386,PROT
+LAR            reg32,reg32             \321\2\x0F\x02\110              386,PROT
+LAR            reg32,reg64             \321\323\2\x0F\x02\110          X64,PROT,ND
 LAR            reg64,mem               \324\2\x0F\x02\110              X64,PROT,SW
 LAR            reg64,reg16             \324\2\x0F\x02\110              X64,PROT
+LAR            reg64,reg32             \324\2\x0F\x02\110              X64,PROT
+LAR            reg64,reg64             \324\2\x0F\x02\110              X64,PROT
 LDS            reg16,mem               \320\1\xC5\110                  8086,NOLONG
 LDS            reg32,mem               \321\1\xC5\110                  386,NOLONG
 LEA            reg16,mem               \320\1\x8D\110                  8086
@@ -671,10 +677,16 @@ LOOPZ             imm,reg_ecx             \311\1\xE1\50                   386
 LOOPZ          imm,reg_rcx             \313\1\xE1\50                   X64
 LSL            reg16,mem               \320\2\x0F\x03\110              286,PROT,SW
 LSL            reg16,reg16             \320\2\x0F\x03\110              286,PROT
+LSL            reg16,reg32             \320\2\x0F\x03\110              386,PROT
+LSL            reg16,reg64             \320\323\2\x0F\x03\110          X64,PROT,ND
 LSL            reg32,mem               \321\2\x0F\x03\110              386,PROT,SW
 LSL            reg32,reg16             \321\2\x0F\x03\110              386,PROT
+LSL            reg32,reg32             \321\2\x0F\x03\110              386,PROT
+LSL            reg32,reg64             \321\323\2\x0F\x03\110          X64,PROT,ND
 LSL            reg64,mem               \324\2\x0F\x03\110              X64,PROT,SW
 LSL            reg64,reg16             \324\2\x0F\x03\110              X64,PROT
+LSL            reg64,reg32             \324\2\x0F\x03\110              X64,PROT
+LSL            reg64,reg64             \324\2\x0F\x03\110              X64,PROT
 LSS            reg16,mem               \320\2\x0F\xB2\110              386
 LSS            reg32,mem               \321\2\x0F\xB2\110              386
 LTR            mem                     \1\x0F\170\203                  286,PROT,PRIV

diff --git a/test/lar_lsl.asm b/test/lar_lsl.asm
new file mode 100644 (file)
index 0000000..69c56fc
--- /dev/null
+++ b/test/lar_lsl.asm
@@ -0,0 +1,122 @@
+; LAR/LSL\r
+;---------\r
+\r
+; 1x ; = invalid due to lack of REX\r
+; 3x ; = invalid due to Mw\r
+\r
+%macro m 1\r
+\r
+  bits 16\r
+\r
+       %1  ax, ax\r
+       %1  ax,eax\r
+;      %1  ax,rax\r
+\r
+       %1 eax, ax\r
+       %1 eax,eax\r
+;      %1 eax,rax\r
+\r
+;      %1 rax, ax\r
+;      %1 rax,eax\r
+;      %1 rax,rax\r
+\r
+       %1  ax,      [0]\r
+       %1  ax, word [0]\r
+;;;    %1  ax,dword [0]\r
+;      %1  ax,qword [0]\r
+\r
+       %1 eax,      [0]\r
+       %1 eax, word [0]\r
+;;;    %1 eax,dword [0]\r
+;      %1 eax,qword [0]\r
+\r
+;      %1 rax,      [0]\r
+;      %1 rax, word [0]\r
+;      %1 rax,dword [0]\r
+;      %1 rax,qword [0]\r
+\r
+  bits 32\r
+\r
+       %1  ax, ax\r
+       %1  ax,eax\r
+;      %1  ax,rax\r
+\r
+       %1 eax, ax\r
+       %1 eax,eax\r
+;      %1 eax,rax\r
+\r
+;      %1 rax, ax\r
+;      %1 rax,eax\r
+;      %1 rax,rax\r
+\r
+       %1  ax,      [0]\r
+       %1  ax, word [0]\r
+;;;    %1  ax,dword [0]\r
+;      %1  ax,qword [0]\r
+\r
+       %1 eax,      [0]\r
+       %1 eax, word [0]\r
+;;;    %1 eax,dword [0]\r
+;      %1 eax,qword [0]\r
+\r
+;      %1 rax,      [0]\r
+;      %1 rax, word [0]\r
+;      %1 rax,dword [0]\r
+;      %1 rax,qword [0]\r
+\r
+  bits 64\r
+\r
+       %1  ax, ax\r
+       %1  ax,eax\r
+       %1  ax,rax      ; $TODO: shouldn't emit REX.W $\r
+\r
+       %1 eax, ax\r
+       %1 eax,eax\r
+       %1 eax,rax      ; $TODO: shouldn't emit REX.W $\r
+\r
+       %1 rax, ax\r
+       %1 rax,eax\r
+       %1 rax,rax\r
+\r
+       %1  ax,      [0]\r
+       %1  ax, word [0]\r
+;;;    %1  ax,dword [0]\r
+;;;    %1  ax,qword [0]\r
+\r
+       %1 eax,      [0]\r
+       %1 eax, word [0]\r
+;;;    %1 eax,dword [0]\r
+;;;    %1 eax,qword [0]\r
+\r
+       %1 rax,      [0]\r
+       %1 rax, word [0]\r
+;;;    %1 rax,dword [0]\r
+;;;    %1 rax,qword [0]\r
+\r
+%endmacro\r
+\r
+m lar\r
+\r
+m lsl\r
+\r
+bits 16\r
+lar ax,[ si]\r
+lar ax,[esi]\r
+bits 32\r
+lar ax,[ si]\r
+lar ax,[esi]\r
+bits 64\r
+lar ax,[esi]\r
+lar ax,[rsi]\r
+\r
+bits 16\r
+lsl ax,[ si]\r
+lsl ax,[esi]\r
+bits 32\r
+lsl ax,[ si]\r
+lsl ax,[esi]\r
+bits 64\r
+lar ax,[esi]\r
+lsl ax,[rsi]\r
+\r
+; EOF\r