ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 3355c48..c465404 100644 (file)
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -68,6 +68,7 @@
                             <0 143 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
                clock-names = "fck";
+               power-domains = <&cpg_clocks>;
 
                renesas,channels-mask = <0x60>;
 
@@ -87,6 +88,7 @@
                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
                clock-names = "fck";
+               power-domains = <&cpg_clocks>;
 
                renesas,channels-mask = <0xff>;
 
@@ -109,6 +111,7 @@
                             <0 16 IRQ_TYPE_LEVEL_HIGH>,
                             <0 17 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
+               power-domains = <&cpg_clocks>;
        };
 
        scif0: serial@e6e60000 {
@@ -117,6 +120,7 @@
                interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
@@ -126,6 +130,7 @@
                interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
@@ -134,6 +139,7 @@
                reg = <0 0xee700000 0 0x400>;
                interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
+               power-domains = <&cpg_clocks>;
                phy-mode = "rmii";
                #address-cells = <1>;
                #size-cells = <0>;
@@ -164,6 +170,7 @@
                        clock-output-names = "main", "pll0", "pll1", "pll3",
                                             "lb", "qspi", "sdh", "sd0", "z",
                                             "rcan", "adsp";
+                       #power-domain-cells = <0>;
                };
 
                /* Variable factor clocks */