drm/i915/lmem: Enable lmem for platforms with Flat CCS

A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.

v2:
  Addressed the small bar related issue [Matt]
  Removed a reduntant check [Matt]
v3:
  removed a variable
  s/DRM_ERROR/drm_err [Lucas]

Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220218184752.7524-15-ramalingam.c@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index db7fe97..beb33b1 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -908,6 +908,25 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
        return intel_uncore_read_fw(gt->uncore, reg);
 }
 
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
+{
+       int type;
+       u8 sliceid, subsliceid;
+
+       for (type = 0; type < NUM_STEERING_TYPES; type++) {
+               if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+                       intel_gt_get_valid_steering(gt, type, &sliceid,
+                                                   &subsliceid);
+                       return intel_uncore_read_with_mcr_steering(gt->uncore,
+                                                                  reg,
+                                                                  sliceid,
+                                                                  subsliceid);
+               }
+       }
+
+       return intel_uncore_read(gt->uncore, reg);
+}
+
 void intel_gt_info_print(const struct intel_gt_info *info,
                         struct drm_printer *p)
 {

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 2dad46c..0f571c8 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -85,6 +85,7 @@ static inline bool intel_gt_needs_read_steering(struct intel_gt *gt,
 }
 
 u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
 
 void intel_gt_info_print(const struct intel_gt_info *info,
                         struct drm_printer *p);

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 2709675..7f711c1 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -97,8 +97,29 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
        if (!IS_DGFX(i915))
                return ERR_PTR(-ENODEV);
 
-       /* Stolen starts from GSMBASE on DG1 */
-       lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+       if (HAS_FLAT_CCS(i915)) {
+               u64 tile_stolen, flat_ccs_base;
+
+               lmem_size = pci_resource_len(pdev, 2);
+               flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
+               flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
+
+               if (GEM_WARN_ON(lmem_size < flat_ccs_base))
+                       return ERR_PTR(-ENODEV);
+
+               tile_stolen = lmem_size - flat_ccs_base;
+
+               /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */
+               if (tile_stolen == lmem_size)
+                       drm_err(&i915->drm,
+                               "CCS_BASE_ADDR register did not have expected value\n");
+
+               lmem_size -= tile_stolen;
+       } else {
+               /* Stolen starts from GSMBASE without CCS */
+               lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
+       }
+
 
        io_start = pci_resource_start(pdev, 2);
        if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f95bbb1..4b95c94 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12645,6 +12645,9 @@ enum skl_power_gate {
 #define   SGGI_DIS                     REG_BIT(15)
 #define   SGR_DIS                      REG_BIT(13)
 
+#define XEHPSDV_FLAT_CCS_BASE_ADDR     _MMIO(0x4910)
+#define   XEHPSDV_CCS_BASE_SHIFT       8
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */