dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA
authorWalker Chen <walker.chen@starfivetech.com>
Tue, 14 Mar 2023 08:35:36 +0000 (16:35 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 28 Mar 2023 03:23:12 +0000 (12:23 +0900)
Add DMA reset operation in device probe and use different configuration
on CH_CFG registers according to match data. Update all uses of
of_device_is_compatible with of_device_get_match_data.

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
drivers/dma/dw-axi-dmac/dw-axi-dmac.h

index 152c5d9..f077d3f 100644 (file)
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/of_dma.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/property.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 
        DMA_SLAVE_BUSWIDTH_32_BYTES     | \
        DMA_SLAVE_BUSWIDTH_64_BYTES)
 
+#define AXI_DMA_FLAG_HAS_APB_REGS      BIT(0)
+#define AXI_DMA_FLAG_HAS_RESETS                BIT(1)
+#define AXI_DMA_FLAG_USE_CFG2          BIT(2)
+
 static inline void
 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
 {
@@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
 
        cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
                  config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
-       if (chan->chip->dw->hdata->reg_map_8_channels) {
+       if (chan->chip->dw->hdata->reg_map_8_channels &&
+           !chan->chip->dw->hdata->use_cfg2) {
                cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
                         config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
                         config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
@@ -1140,7 +1147,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
        axi_chan_disable(chan);
 
        ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
-                                       !(val & chan_active), 1000, 10000);
+                                       !(val & chan_active), 1000, 200000);
        if (ret == -ETIMEDOUT)
                dev_warn(dchan2dev(dchan),
                         "%s failed to stop\n", axi_chan_name(chan));
@@ -1367,11 +1374,12 @@ static int parse_device_properties(struct axi_dma_chip *chip)
 
 static int dw_probe(struct platform_device *pdev)
 {
-       struct device_node *node = pdev->dev.of_node;
        struct axi_dma_chip *chip;
        struct resource *mem;
        struct dw_axi_dma *dw;
        struct dw_axi_dma_hcfg *hdata;
+       struct reset_control *resets;
+       unsigned int flags;
        u32 i;
        int ret;
 
@@ -1400,12 +1408,25 @@ static int dw_probe(struct platform_device *pdev)
        if (IS_ERR(chip->regs))
                return PTR_ERR(chip->regs);
 
-       if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+       flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
+       if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
                chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
                if (IS_ERR(chip->apb_regs))
                        return PTR_ERR(chip->apb_regs);
        }
 
+       if (flags & AXI_DMA_FLAG_HAS_RESETS) {
+               resets = devm_reset_control_array_get_exclusive(&pdev->dev);
+               if (IS_ERR(resets))
+                       return PTR_ERR(resets);
+
+               ret = reset_control_deassert(resets);
+               if (ret)
+                       return ret;
+       }
+
+       chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
+
        chip->core_clk = devm_clk_get(chip->dev, "core-clk");
        if (IS_ERR(chip->core_clk))
                return PTR_ERR(chip->core_clk);
@@ -1556,8 +1577,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
 };
 
 static const struct of_device_id dw_dma_of_id_table[] = {
-       { .compatible = "snps,axi-dma-1.01a" },
-       { .compatible = "intel,kmb-axi-dma" },
+       {
+               .compatible = "snps,axi-dma-1.01a"
+       }, {
+               .compatible = "intel,kmb-axi-dma",
+               .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
+       }, {
+               .compatible = "starfive,jh7110-axi-dma",
+               .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
+       },
        {}
 };
 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
index e9d5eb0..eb267cb 100644 (file)
@@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
        /* Register map for DMAX_NUM_CHANNELS <= 8 */
        bool    reg_map_8_channels;
        bool    restrict_axi_burst_len;
+       bool    use_cfg2;
 };
 
 struct axi_dma_chan {