return 0;
}
-#if !IS_ENABLED(CONFIG_DM_PCI)
-static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 *value)
-{
- struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
-
- *value = 0xffffffff;
- return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
-}
-
-static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 value)
-{
- struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
- u32 data = value;
-
- return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
-}
-
-void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
- unsigned long sys_size, unsigned long mem_bus,
- unsigned long mem_phys, unsigned long mem_size,
- unsigned long io_bus, unsigned long io_phys,
- unsigned long io_size)
-{
- static struct gt64120_pci_controller global_gt;
- struct gt64120_pci_controller *gt;
- struct pci_controller *hose;
-
- gt = &global_gt;
- gt->regs = regs;
-
- hose = >->hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* System memory space */
- pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-}
-#else
static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint where, ulong *val,
enum pci_size_t size)
.probe = gt64120_pci_probe,
.priv_auto = sizeof(struct gt64120_pci_controller),
};
-#endif