arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl

With the Hantro G1 and G2 now setup to run independently, update
the device tree to allow both to operate.  This requires the
vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
certain clock enabled to handle the gating of the G1 and G2
fuses, the clock-parents and clock-rates for the various VPU's
to be moved into the pgc_vpu because they cannot get re-parented
once enabled, and the pgc_vpu is the highest in the chain.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 94d09dc..c4d4895 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -737,7 +737,21 @@
                                        pgc_vpu: power-domain@6 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8M_POWER_DOMAIN_VPU>;
-                                               clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+                                               clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
+                                                        <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+                                                        <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+                                               assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+                                                                 <&clk IMX8MQ_CLK_VPU_G2>,
+                                                                 <&clk IMX8MQ_CLK_VPU_BUS>,
+                                                                 <&clk IMX8MQ_VPU_PLL_BYPASS>;
+                                               assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+                                                                        <&clk IMX8MQ_VPU_PLL_OUT>,
+                                                                        <&clk IMX8MQ_SYS1_PLL_800M>,
+                                                                        <&clk IMX8MQ_VPU_PLL>;
+                                               assigned-clock-rates = <600000000>,
+                                                                      <600000000>,
+                                                                      <800000000>,
+                                                                      <0>;
                                        };
 
                                        pgc_disp: power-domain@7 {
@@ -1457,30 +1471,31 @@
                        status = "disabled";
                };
 
-               vpu: video-codec@38300000 {
-                       compatible = "nxp,imx8mq-vpu";
-                       reg = <0x38300000 0x10000>,
-                             <0x38310000 0x10000>,
-                             <0x38320000 0x10000>;
-                       reg-names = "g1", "g2", "ctrl";
-                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "g1", "g2";
+               vpu_g1: video-codec@38300000 {
+                       compatible = "nxp,imx8mq-vpu-g1";
+                       reg = <0x38300000 0x10000>;
+                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
+                       power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
+               };
+
+               vpu_g2: video-codec@38310000 {
+                       compatible = "nxp,imx8mq-vpu-g2";
+                       reg = <0x38310000 0x10000>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+                       power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
+               };
+
+               vpu_blk_ctrl: blk-ctrl@38320000 {
+                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
+                       reg = <0x38320000 0x100>;
+                       power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
+                       power-domain-names = "bus", "g1", "g2";
                        clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
-                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
-                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
-                       clock-names = "g1", "g2", "bus";
-                       assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
-                                         <&clk IMX8MQ_CLK_VPU_G2>,
-                                         <&clk IMX8MQ_CLK_VPU_BUS>,
-                                         <&clk IMX8MQ_VPU_PLL_BYPASS>;
-                       assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
-                                                <&clk IMX8MQ_VPU_PLL_OUT>,
-                                                <&clk IMX8MQ_SYS1_PLL_800M>,
-                                                <&clk IMX8MQ_VPU_PLL>;
-                       assigned-clock-rates = <600000000>, <600000000>,
-                                              <800000000>, <0>;
-                       power-domains = <&pgc_vpu>;
+                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+                       clock-names = "g1", "g2";
+                       #power-domain-cells = <1>;
                };
 
                pcie0: pcie@33800000 {