#define CONFIG_SYS_CLK_FREQ_C210 24000000
#endif
+unsigned long (*get_uclk)(void);
unsigned long (*get_pclk)(void);
unsigned long (*get_arm_clk)(void);
unsigned long (*get_pll_clk)(int);
struct s5pc210_clock *clk =
(struct s5pc210_clock *)samsung_get_base_clock();
unsigned long div;
- unsigned long dout_apll, armclk;
+ unsigned long dout_apll;
unsigned int apll_ratio;
div = readl(&clk->div_cpu0);
apll_ratio = (div >> 24) & 0x7;
dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
- armclk = dout_apll;
- return armclk;
+ return dout_apll;
}
/* s5pc210: return peripheral clock frequency */
return get_pll_clk(MPLL);
}
+/* s5pc210: return uart clock frequency */
+static unsigned long s5pc210_get_uclk(int dev_index)
+{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long uclk, sclk;
+ unsigned int uart_sel;
+ unsigned int uart_ratio;
+
+ uart_sel = readl(&clk->src_peril0);
+ uart_sel = (uart_sel >> (dev_index << 2)) & 0xf;
+
+ if (uart_sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (uart_sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (uart_sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ uart_ratio = readl(&clk->div_peril0);
+ uart_ratio = (uart_ratio >> (dev_index << 2)) & 0xf;
+
+ uclk = sclk / (uart_ratio + 1);
+
+ return uclk;
+}
+
void s5p_clock_init(void)
{
if (cpu_is_s5pc210()) {
get_pll_clk = s5pc210_get_pll_clk;
get_arm_clk = s5pc210_get_arm_clk;
get_pclk = s5pc210_get_pclk;
+ get_uclk = s5pc210_get_uclk;
}
}