crypto: ccp - Add support for PCI device 0x17E0
authorMario Limonciello <mario.limonciello@amd.com>
Fri, 19 May 2023 03:24:13 +0000 (22:24 -0500)
committerHerbert Xu <herbert@gondor.apana.org.au>
Fri, 2 Jun 2023 10:21:32 +0000 (18:21 +0800)
PCI device 0x17E0 includes new TEE offsets, doesn't support a
platform mailbox, and does support platform doorbell
so introduce a new structure to represent it.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/ccp/sp-pci.c

index aa15bc4..d0d70af 100644 (file)
@@ -361,6 +361,14 @@ static const struct tee_vdata teev1 = {
        .ring_rptr_reg          = 0x10554,      /* C2PMSG_21 */
 };
 
+static const struct tee_vdata teev2 = {
+       .cmdresp_reg            = 0x10944,      /* C2PMSG_17 */
+       .cmdbuff_addr_lo_reg    = 0x10948,      /* C2PMSG_18 */
+       .cmdbuff_addr_hi_reg    = 0x1094c,      /* C2PMSG_19 */
+       .ring_wptr_reg          = 0x10950,      /* C2PMSG_20 */
+       .ring_rptr_reg          = 0x10954,      /* C2PMSG_21 */
+};
+
 static const struct platform_access_vdata pa_v1 = {
        .cmdresp_reg            = 0x10570,      /* C2PMSG_28 */
        .cmdbuff_addr_lo_reg    = 0x10574,      /* C2PMSG_29 */
@@ -369,6 +377,11 @@ static const struct platform_access_vdata pa_v1 = {
        .doorbell_cmd_reg       = 0x10a40,      /* C2PMSG_80 */
 };
 
+static const struct platform_access_vdata pa_v2 = {
+       .doorbell_button_reg    = 0x10a24,      /* C2PMSG_73 */
+       .doorbell_cmd_reg       = 0x10a40,      /* C2PMSG_80 */
+};
+
 static const struct psp_vdata pspv1 = {
        .sev                    = &sevv1,
        .feature_reg            = 0x105fc,      /* C2PMSG_63 */
@@ -399,6 +412,14 @@ static const struct psp_vdata pspv4 = {
        .intsts_reg             = 0x10694,      /* P2CMSG_INTSTS */
 };
 
+static const struct psp_vdata pspv5 = {
+       .tee                    = &teev2,
+       .platform_access        = &pa_v2,
+       .feature_reg            = 0x109fc,      /* C2PMSG_63 */
+       .inten_reg              = 0x10510,      /* P2CMSG_INTEN */
+       .intsts_reg             = 0x10514,      /* P2CMSG_INTSTS */
+};
+
 #endif
 
 static const struct sp_dev_vdata dev_vdata[] = {
@@ -453,6 +474,12 @@ static const struct sp_dev_vdata dev_vdata[] = {
                .psp_vdata = &pspv3,
 #endif
        },
+       {       /* 7 */
+               .bar = 2,
+#ifdef CONFIG_CRYPTO_DEV_SP_PSP
+               .psp_vdata = &pspv5,
+#endif
+       },
 };
 static const struct pci_device_id sp_pci_table[] = {
        { PCI_VDEVICE(AMD, 0x1537), (kernel_ulong_t)&dev_vdata[0] },
@@ -463,6 +490,7 @@ static const struct pci_device_id sp_pci_table[] = {
        { PCI_VDEVICE(AMD, 0x14CA), (kernel_ulong_t)&dev_vdata[5] },
        { PCI_VDEVICE(AMD, 0x15C7), (kernel_ulong_t)&dev_vdata[6] },
        { PCI_VDEVICE(AMD, 0x1649), (kernel_ulong_t)&dev_vdata[6] },
+       { PCI_VDEVICE(AMD, 0x17E0), (kernel_ulong_t)&dev_vdata[7] },
        /* Last entry must be zero */
        { 0, }
 };