#include <hw/hw.h>
#include <hw/pc.h>
#include <hw/pci.h>
+#include <hw/isa.h>
#include "qemu-error.h"
#include "qemu-timer.h"
#include "sysemu.h"
bus->dma = &ide_dma_nop;
}
-void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
+static const MemoryRegionPortio ide_portio_list[] = {
+ { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
+ { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
+ { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
+ PORTIO_END_OF_LIST(),
+};
+
+static const MemoryRegionPortio ide_portio2_list[] = {
+ { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
+ PORTIO_END_OF_LIST(),
+};
+
+void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
{
- register_ioport_write(iobase, 8, 1, ide_ioport_write, bus);
- register_ioport_read(iobase, 8, 1, ide_ioport_read, bus);
+ /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
+ bridge has been setup properly to always register with ISA. */
+ isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
+
if (iobase2) {
- register_ioport_read(iobase2, 1, 1, ide_status_read, bus);
- register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus);
+ isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
}
-
- /* data ports */
- register_ioport_write(iobase, 2, 2, ide_data_writew, bus);
- register_ioport_read(iobase, 2, 2, ide_data_readw, bus);
- register_ioport_write(iobase, 4, 4, ide_data_writel, bus);
- register_ioport_read(iobase, 4, 4, ide_data_readl, bus);
}
static bool is_identify_set(void *opaque, int version_id)
* non-internal declarations are in hw/ide.h
*/
#include <hw/ide.h>
+#include <hw/isa.h>
#include "iorange.h"
#include "dma.h"
#include "sysemu.h"
void ide_init2(IDEBus *bus, qemu_irq irq);
void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
DriveInfo *hd1, qemu_irq irq);
-void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
+void ide_init_ioport(IDEBus *bus, ISADevice *isa, int iobase, int iobase2);
void ide_exec_cmd(IDEBus *bus, uint32_t val);
void ide_dma_cb(void *opaque, int ret);
ISAIDEState *s = DO_UPCAST(ISAIDEState, dev, dev);
ide_bus_new(&s->bus, &s->dev.qdev, 0);
- ide_init_ioport(&s->bus, s->iobase, s->iobase2);
+ ide_init_ioport(&s->bus, dev, s->iobase, s->iobase2);
isa_init_irq(dev, &s->irq, s->isairq);
- isa_init_ioport_range(dev, s->iobase, 8);
- isa_init_ioport(dev, s->iobase2);
ide_init2(&s->bus, s->irq);
vmstate_register(&dev->qdev, 0, &vmstate_ide_isa, s);
return 0;
}
static void pci_piix_init_ports(PCIIDEState *d) {
- int i;
- struct {
+ static const struct {
int iobase;
int iobase2;
int isairq;
{0x1f0, 0x3f6, 14},
{0x170, 0x376, 15},
};
+ int i;
for (i = 0; i < 2; i++) {
ide_bus_new(&d->bus[i], &d->dev.qdev, i);
- ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
+ ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
+ port_info[i].iobase2);
ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
}
static void vt82c686b_init_ports(PCIIDEState *d) {
- int i;
- struct {
+ static const struct {
int iobase;
int iobase2;
int isairq;
{0x1f0, 0x3f6, 14},
{0x170, 0x376, 15},
};
+ int i;
for (i = 0; i < 2; i++) {
ide_bus_new(&d->bus[i], &d->dev.qdev, i);
- ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
+ ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
+ port_info[i].iobase2);
ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
bmdma_init(&d->bus[i], &d->bmdma[i], d);