TEXT_BASE = 0xfff00000
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float
#include <common.h>
#include <command.h>
-static unsigned char srom[128];
extern u16 read_srom_word(int);
extern void write_srom_word(int offset, u16 val);
/*
* cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
- * DDR2 controller (non Denali Core). Those are 440SP/SPe.
+ * DDR2 controller (non Denali Core). Those currently are:
+ *
+ * 405: 405EX
+ * 440/460: 440SP/440SPe/460EX/460GT
*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
if (num_banks == 4)
ind = 0;
else
- ind = 5;
+ ind = 5 << 8;
switch (num_col_addr) {
case 0x08:
mode |= (SDRAM_BXCF_M_AM_0 + ind);
/* */
/****************************************************************************/
/* mk@tbd: Fix this! */
-#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS)
+#undef RCSR
#undef ICMR
#undef OSMR3
#undef OSCR
#undef OWER
#undef OIER
-#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_PXA250
-#undef RCSR
#undef CCCR
-#endif /* CONFIG_PXA250 */
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
#ifdef CFG_VSC8601_SKEWFIX
{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
+ {MIIM_EXT_PAGE_ACCESS,1,NULL},
+#define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
+ {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
+ {MIIM_EXT_PAGE_ACCESS,0,NULL},
+#endif
#endif
{miim_end,}
},
#define MIIM_GBIT_CONTROL 0x9
#define MIIM_GBIT_CONTROL_INIT 0xe00
+#define MIIM_EXT_PAGE_ACCESS 0x1f
+
/* Broadcom BCM54xx -- taken from linux sungem_phy */
#define MIIM_BCM54xx_AUXSTATUS 0x19
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
/* Vitesse VSC8601 Extended PHY Control Register 1 */
-#define MIIM_VSC8601_EPHY_CON 0x17
+#define MIIM_VSC8601_EPHY_CON 0x17
#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
+#define MIIM_VSC8601_SKEW_CTRL 0x1c
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
/* 88E1111 PHY LED Control Register */
-#define MIIM_88E1111_PHY_LED_CONTROL 24
-#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
-#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
+#define MIIM_88E1111_PHY_LED_CONTROL 24
+#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
debug ("%s\n", __FUNCTION__);
i = 0;
- while (reg_arr[i])
- *((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++];
+ while (reg_arr[i]) {
+ (*(volatile unsigned int *) reg_arr[i]) |= reg_arr[i + 1];
+ i += 2;
+ }
udelay (1000);
debug ("%s: programmed mem controller \n", __FUNCTION__);
#ifdef CONFIG_EXADRON1
/*define useful BCR masks */
-#define BCR_CF_INIT_VAL 0x00007230
+#define BCR_CF_INIT_VAL 0x00007230
#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231
#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233
#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213
tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f);
tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f);
tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
- tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f) - 1;
+ tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f);
/* assume 20YY not 19YY, and ignore the Century Bit */
/* U-Boot needs to add 1900 here */
buf[M41T62_REG_DAY] =
BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
buf[M41T62_REG_MON] =
- BIN2BCD(tm->tm_mon + 1) | (buf[M41T62_REG_MON] & ~0x1f);
+ BIN2BCD(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
/* assume 20YY not 19YY */
buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100);
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerious
+ * big endian mode connectivity is in place, as described by numerous
* ARM documents:
*
* PCI: D0-D7 D8-D15 D16-D23 D24-D31
#include <devices.h>
#include <version.h>
#include <net.h>
+#include <serial.h>
#ifdef CONFIG_DRIVER_SMC91111
#include "../drivers/net/smc91111.h"
#include <status_led.h>
#endif
#include <net.h>
+#include <serial.h>
#if defined(CONFIG_CMD_BEDBUG)
#include <cmd_bedbug.h>
#endif
* enabled. This will only work for the same memory
* configuration as used here:
*
- * Crucial CT6464AC53E.4FE - 512MB SO-DIMM
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM
*
*/
mtsdram(SDRAM_MCOPT2, 0x00000000);
- mtsdram(SDRAM_MCOPT1, 0x05322000);
+ mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_MODT0, 0x01000000);
- mtsdram(SDRAM_CODT, 0x00800021);
+ mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201);
+ mtsdram(SDRAM_MB1CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243);
- mtsdram(SDRAM_SDTR3, 0x0A0D0D1A);
+ mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
mtsdram(SDRAM_MMODE, 0x00000632);
mtsdram(SDRAM_MEMODE, 0x00000040);
mtsdram(SDRAM_INITPLR0, 0xB5380000);
wait_init_complete();
- mtdcr(SDRAM_R0BAS, 0x0000F000); /* MQ0_B0BAS */
+ mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
+ mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
mtsdram(SDRAM_RDCC, 0x40000000);
mtsdram(SDRAM_RQDC, 0x80000038);
extern int errno;
#ifndef MAP_FAILED
-#define MAP_FAILED (-1)
+#define MAP_FAILED (void *)(-1)
#endif
extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len);
exit (EXIT_FAILURE);
}
- ptr = (unsigned char *)mmap(0, sbuf.st_size,
- PROT_READ, MAP_SHARED, ifd, 0);
- if ((caddr_t)ptr == (caddr_t)-1) {
+ ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0);
+ if (ptr == MAP_FAILED) {
fprintf (stderr, "%s: Can't read %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
exit (EXIT_FAILURE);
}
- ptr = (unsigned char *)mmap(0, sbuf.st_size,
- PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0);
- if (ptr == (unsigned char *)MAP_FAILED) {
+ ptr = mmap(0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0);
+ if (ptr == MAP_FAILED) {
fprintf (stderr, "%s: Can't map %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
exit (EXIT_FAILURE);
}
- ptr = (unsigned char *)mmap(0, sbuf.st_size,
- PROT_READ, MAP_SHARED, dfd, 0);
- if (ptr == (unsigned char *)MAP_FAILED) {
+ ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0);
+ if (ptr == MAP_FAILED) {
fprintf (stderr, "%s: Can't read %s: %s\n",
cmdname, datafile, strerror(errno));
exit (EXIT_FAILURE);
exit (EXIT_FAILURE);
}
- ptr = (unsigned char *)mmap (0, sbuf.st_size,
- PROT_READ|PROT_WRITE, MAP_SHARED, tfd, 0);
- if ((caddr_t)ptr == (caddr_t)-1) {
+ ptr = mmap (0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, tfd, 0);
+ if (ptr == MAP_FAILED) {
fprintf (stderr, "%s: Can't read %s: %s\n",
cmdname, tmpfile, strerror(errno));
unlink (tmpfile);