ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL

This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index a0d971a..66be7df 100644 (file)
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -88,6 +88,16 @@
        u-boot,dm-pre-reloc;
 };
 
+&cpu0_opp_table {
+       u-boot,dm-spl;
+       opp-650000000 {
+               u-boot,dm-spl;
+       };
+       opp-800000000 {
+               u-boot,dm-spl;
+       };
+};
+
 &gpioa {
        u-boot,dm-pre-reloc;
 };

diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index e13dade..7b8c1c1 100644 (file)
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -133,15 +133,6 @@
                CLK_LPTIM45_LSE
        >;
 
-       /* VCO = 1300.0 MHz => P = 650 (CPU) */
-       pll1: st,pll@0 {
-               compatible = "st,stm32mp1-pll";
-               reg = <0>;
-               cfg = < 2 80 0 0 0 PQR(1,0,0) >;
-               frac = < 0x800 >;
-               u-boot,dm-pre-reloc;
-       };
-
        /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
        pll2: st,pll@1 {
                compatible = "st,stm32mp1-pll";

diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index b16dc28..ef3e7f4 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -129,15 +129,6 @@
                CLK_LPTIM45_LSE
        >;
 
-       /* VCO = 1300.0 MHz => P = 650 (CPU) */
-       pll1: st,pll@0 {
-               compatible = "st,stm32mp1-pll";
-               reg = <0>;
-               cfg = < 2 80 0 0 0 PQR(1,0,0) >;
-               frac = < 0x800 >;
-               u-boot,dm-pre-reloc;
-       };
-
        /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
        pll2: st,pll@1 {
                compatible = "st,stm32mp1-pll";

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index df63ad4..69c5af4 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -235,15 +235,6 @@
                CLK_LPTIM45_LSE
        >;
 
-       /* VCO = 1300.0 MHz => P = 650 (CPU) */
-       pll1: st,pll@0 {
-               compatible = "st,stm32mp1-pll";
-               reg = <0>;
-               cfg = < 2 80 0 0 0 PQR(1,0,0) >;
-               frac = < 0x800 >;
-               u-boot,dm-pre-reloc;
-       };
-
        /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
        pll2: st,pll@1 {
                compatible = "st,stm32mp1-pll";

diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index bd4c2ad..7529068 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -114,15 +114,6 @@
                CLK_LPTIM45_LSE
        >;
 
-       /* VCO = 1300.0 MHz => P = 650 (CPU) */
-       pll1: st,pll@0 {
-               compatible = "st,stm32mp1-pll";
-               reg = <0>;
-               cfg = < 2 80 0 0 0 PQR(1,0,0) >;
-               frac = < 0x800 >;
-               u-boot,dm-pre-reloc;
-       };
-
        /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
        pll2: st,pll@1 {
                compatible = "st,stm32mp1-pll";