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arm64: dts: qcom: align DWC3 USB interrupts with DT schema
authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Wed, 4 May 2022 13:19:23 +0000 (15:19 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 5 May 2022 20:06:44 +0000 (22:06 +0200)
Align order of interrupts with Qualcomm DWC3 USB DT schema.  No
functional impact expected.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504131923.214367-14-krzysztof.kozlowski@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm64/boot/dts/qcom/sc7280.dtsi patch | blob | history
arch/arm64/boot/dts/qcom/sm8450.dtsi patch | blob | history

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fd959fe..5620926 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2934,11 +2934,13 @@
                        assigned-clock-rates = <19200000>, <200000000>;
 
                        interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 17 IRQ_TYPE_EDGE_BOTH>,
                                              <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
-                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-                                         "dm_hs_phy_irq", "ss_phy_irq";
+                                             <&pdc 14 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hs_phy_irq",
+                                         "ss_phy_irq",
+                                         "dm_hs_phy_irq",
+                                         "dp_hs_phy_irq";
 
                        power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
 
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index e8cc036..f9f7f17 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1462,11 +1462,13 @@
                        assigned-clock-rates = <19200000>, <200000000>;
 
                        interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
                                              <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
-                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-                                         "dm_hs_phy_irq", "ss_phy_irq";
+                                             <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
+                       interrupt-names = "hs_phy_irq",
+                                         "ss_phy_irq",
+                                         "dm_hs_phy_irq",
+                                         "dp_hs_phy_irq";
 
                        power-domains = <&gcc USB30_PRIM_GDSC>;
 
Domain: System / Kernel;