[AArch64][SVE] Add missing movprfx attribute to some ternary arithmetic patterns

The two affected SVE2 patterns in this patch output a movprfx'ed instruction in their second alternative
but don't set the "movprfx" attribute, which will result in the wrong instruction length being assumed by the midend.

This patch fixes that in the same way as the other SVE patterns in the backend.

Bootstrapped and tested on aarch64-none-linux-gnu.

2020-03-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
	Specify movprfx attribute.
	(@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 843c49e..957c4cc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
+       Specify movprfx attribute.
+       (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
+
 2020-03-06  David Edelsohn  <dje.gcc@gmail.com>
 
        PR target/94065

diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index f82e60e..e18b9fe 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -690,6 +690,7 @@
   "@
    <sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>
    movprfx\t%0, %1\;<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>"
+  [(set_attr "movprfx" "*,yes")]
 )
 
 (define_insn "@aarch64_sve_<sve_int_op>_lane_<mode>"
@@ -706,6 +707,7 @@
   "@
    <sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>[%4]
    movprfx\t%0, %1\;<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>[%4]"
+  [(set_attr "movprfx" "*,yes")]
 )
 
 ;; -------------------------------------------------------------------------