drm/amd/display: Add green_sardine support to DC
authorRoman Li <Roman.Li@amd.com>
Thu, 8 Oct 2020 17:28:41 +0000 (13:28 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 Nov 2020 13:40:42 +0000 (08:40 -0500)
Display Core support for green_sardine

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/Kconfig
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drivers/gpu/drm/amd/display/include/dal_asic_id.h

index 60dfdd432aba0ed47e723d259e6313a5dad4557a..2a30a9bd178cab36c6060f76185cc7e83841f6c3 100644 (file)
@@ -17,6 +17,14 @@ config DRM_AMD_DC_DCN
        help
          Raven, Navi and Renoir family support for display engine
 
+config DRM_AMD_DC_GREEN_SARDINE
+       bool "Green Sardine support"
+       default y
+       depends on DRM_AMD_DC_DCN
+        help
+            Choose this option if you want to have
+            Green Sardine support for display engine
+
 config DRM_AMD_DC_DCN3_0
         bool "DCN 3.0 family"
         depends on DRM_AMD_DC && X86
index efb909ef7a0f732ca6e905cc5efc3575c150562f..7fb6655a41e7b9c80491981eee2ff708c830c555 100644 (file)
@@ -166,6 +166,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
                        rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
                        break;
                }
+
+#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
+               if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
+                       rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+                       break;
+               }
+#endif
                if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
                        rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
                        break;
index e430148e47cf4f25ea109011ab31127a1d6e2dbc..36a344a441c22327882d9d283a6603f9ddfe9c4a 100644 (file)
@@ -120,6 +120,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
                        dc_version = DCN_VERSION_1_01;
                if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
                        dc_version = DCN_VERSION_2_1;
+#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
+               if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
+                       dc_version = DCN_VERSION_2_1;
+#endif
                break;
 #endif
 
index b267987aed068e69f03634f90da72d4c28e39e66..52fedddecada772a23c68bf7bb8427a8be96132d 100644 (file)
@@ -205,6 +205,12 @@ enum {
 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define ASICREV_IS_SIENNA_CICHLID_P(eChipRev)        ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
 #endif
+#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
+#define GREEN_SARDINE_A0 0xA1
+#ifndef ASICREV_IS_GREEN_SARDINE
+#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
+#endif
+#endif
 
 /*
  * ASIC chip ID